CN109478563A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN109478563A
CN109478563A CN201780044650.8A CN201780044650A CN109478563A CN 109478563 A CN109478563 A CN 109478563A CN 201780044650 A CN201780044650 A CN 201780044650A CN 109478563 A CN109478563 A CN 109478563A
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active groove
groove grid
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CN109478563B (zh
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河野宪司
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Denso Corp
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Denso Corp
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Abstract

半导体装置具备多个开关元件、和半导体基板。多个开关元件并联地连接而被驱动，多个开关元件形成于半导体基板。在半导体基板的平面视图下，多个开关元件分别具有：单元区域(111)，形成有被施加栅极电压的有源沟槽栅极(G1)，作为IGBT发挥功能；外周区域(112)，形成芯片外形；以及非单元区域(113)，形成为将单元区域和外周区域分离，设置有对向单元区域的电连接进行中继的焊盘(114)。在半导体基板的平面视图下，有源沟槽栅极在非单元区域中还形成在不与焊盘重叠的位置。

Description

半导体装置
关联申请的相互参照
本申请基于2016年7月21日提出申请的日本专利申请第2016－143300号主张优先权，这里引用其记载内容。
技术领域
本发明涉及多个开关元件被并联驱动的导体装置。
背景技术
已知一种半导体装置，其通过使多个开关元件并联地连接并以适当的定时进行接通或断开，能够减小开关时的损失而进行输出电流的控制。
在并联驱动的半导体装置中，在开关元件间产生寄生电感。因此，在开关时产生感应电动势，产生电压振动及伴随着电压振动的输出电流的振动。
例如在开关元件是IGBT元件的情况下，已知在栅极－发射极间追加电容而抑制电压振动的方法。在专利文献1中，记载了利用沟槽栅型的IGBT元件的栅极电极与发射极电极间的寄生电容的例子。此外，也可以考虑在安装基板上追加芯片电容的方法。
现有技术文献
专利文献
专利文献1：日本特开2011－192822号公报
发明概要
在专利文献1所记载的半导体装置中，在芯片中的不作为IGBT元件发挥功能的外周区域中的、被用作电极的焊盘下追加沟槽栅极而得到寄生电容。但是，由于焊盘在引线键合时受到比较大的应力，所以在焊盘下形成有用于电容追加的构造在有关电容追加的功能方面、以及有关电连接的可靠性方面都是不好的。此外，发现了以下课题，即：在安装基板上另外追加芯片电容的形态下，在用来连接芯片电容的布线中产生寄生电感，不能充分得到抑制由寄生电感引起的电压振动的效果。
发明内容
因此，本发明的目的在于提供一种半导体装置，用于不损害焊盘的连接可靠性地抑制电压振动。
本发明的一技术方案的半导体装置，具备多个开关元件、和半导体基板。多个开关元件并联地连接而被驱动。多个开关元件形成于半导体基板。在半导体基板的平面视图下，多个开关元件分别具有：单元区域，形成有被施加栅极电压的有源沟槽栅极，作为IGBT发挥功能；外周区域，形成芯片外形；以及非单元区域，形成为将上述单元区域和上述外周区域分离，设置有对向上述单元区域的电连接进行中继的焊盘。在半导体基板的平面视图下，有源沟槽栅极在非单元区域中还形成在不与上述焊盘重叠的位置。
由此，在单元区域以外的非单元区域中也能够在栅极－发射极间追加电容作为寄生电容。由于电容的追加不取决于芯片电容的外部连接，所以能够不受寄生电感的不良影响而增加栅极－发射极间电容。
进而，由于形成寄生电容的有源沟槽栅极避开焊盘的形成位置而形成，所以不会降低焊盘的可靠性。
这样，根据该半导体装置，能够不损害可靠性而增加栅极－发射极间电容，进而能够抑制由IGBT元件的并联连接引起的电压振动。
附图说明
关于本发明的上述目的及其他目的、特征及优点一边参照附图一边通过下述详细的记述会变得更明确。
图1是表示第1实施方式的半导体装置的结构的等价电路图。
图2是表示开关元件的概略结构的俯视图。
图3是表示沿着图2的III－III线的截面的剖视图。
图4是表示沿着图2的IV－IV线的截面的剖视图。
图5是表示非单元区域中的有源沟槽栅极的引绕的俯视图。
图6是表示集电极电压及发射极电压的变化的图。
图7是表示相对于追加电容比而言的电压振动比的变化的图。
图8是第2实施方式的半导体装置的剖视图。
图9是第3实施方式的半导体装置的剖视图。
图10是第4实施方式的半导体装置的剖视图。
具体实施方式
以下，基于附图对本发明的实施方式进行说明。另外，在以下的各图相互间，对于相互相同或等同的部分附加相同的标号。
(第1实施方式)
首先，参照图1对本实施方式的半导体装置100的概略结构进行说明。
本实施方式的半导体装置例如用于将多个逆导通绝缘栅双极型晶体管(RC－IGBT)并联连接而得到输出电流的开关电路。
图1是本实施方式的半导体装置100的等价电路。如图1所示，半导体装置100将在从电源VCC到作为基准电位的地电位(GND)之间串联连接的开关元件110并联连接2组而成。即，多个开关元件110相对于电源VCC并联地连接。开关元件110具备IGBT元件Tr。在本实施方式中，2个IGBT元件Tr在电源VCC与输出OUT之间并联地连接。高压侧的IGBT元件Tr的集电极端子被连接到电源VCC侧，发射极端子是输出OUT侧。此外，能够对各IGBT元件Tr的栅极端子施加栅极电压。另外，低压侧的IGBT元件Tr的集电极端子被连接到输出OUT侧，发射极端子是GND侧。低压侧的IGBT元件Tr也相对于输出OUT并联地连接。
另外，如后述那样，构成本实施方式的半导体装置100的开关元件110是RC－IGBT，具备续流二极管元件Di，但在图1所示的等价电路中省略。
开关元件110在IGBT元件Tr的栅极端子与发射极端子之间具备寄生电容C。产生寄生电容C的构造性理由在后面说明。
在并联连接的开关元件110之间产生寄生电感L。在图1中，作为代表例而示出了在电源VCC与开关元件110的连接布线、栅极布线、IGBT元件Tr的发射极布线中产生寄生电感L的例子，但是例如在开尔文发射极布线或其他布线中也会产生寄生电感L。
接着，参照图2～图5，对IGBT元件Tr及寄生电容C的详细结构进行说明。多个开关元件110相互等价，并且各IGBT元件Tr、各续流二极管元件Di以及寄生电容C分别等价，所以对一个开关元件110进行说明。
另外，图3是沿着图2中的III－III线的剖视图。此外，图4是沿着图2中的IV－IV线的剖视图。在图3及图4中，对后述的沟槽栅极G1、G2及p导电型的半导体区域施加了影线，对n导电型的半导体区域没有施加影线。
开关元件110形成于半导体基板，如图2所示，具备：单元区域111，形成有IGBT元件Tr和续流二极管(FWD)元件Di；外周区域112，位于单元区域111的外周，形成开关元件110的外形；以及非单元区域113，在单元区域111的外周形成以将单元区域111与外周区域112分离。
单元区域111具有IGBT元件Tr和FWD元件Di。IGBT元件Tr和FWD元件Di成为彼此在相同的方向上延伸设置、并且在与延伸设置方向正交的方向上交替地配置的条带构造。IGBT元件Tr及FWD元件Di分别相当于IGBT区域、FWD区域。
参照图3对IGBT元件Tr及FWD元件Di的详细构造进行说明。如图3所示，以虚线为边界，纸面左侧是IGBT元件Tr，纸面右侧是FWD元件Di。
IGBT元件Tr中，作为半导体区域，具备n导电型的漂移区域10、p导电型的集电极区域11、p导电型的基极(base)区域13和n导电型的发射极区域14。此外，IGBT元件Tr具备沟槽栅极G1。
漂移区域10层叠在集电极区域11上。基极区域13层叠在漂移区域10上。基极区域13在半导体基板的表面13a露出，未图示的发射极电极与基极区域13连接。沟槽栅极G1从表面13a将基极区域13贯通而到达漂移区域10。沟槽栅极G1隔着未图示的绝缘膜而与基极区域13及漂移区域10相接。另外，在基极区域13中的被发射极区域14夹着的表面13a露出的部分，形成了与基极区域13和发射极电极的接合有关的接触区域15。
属于IGBT元件Tr的沟槽栅极中的与发射极区域14相接的沟槽栅极G1是能够被施加栅极电压的有源沟槽栅极。在图3及图4中，对沟槽栅极中的有源沟槽栅极附加标号G1，对不被施加栅极电压的伪栅极附加标号G2。在图3中，表示了属于IGBT元件Tr的全部沟槽栅极是有源沟槽栅极G1的例子，但也可以是以规定的周期包含伪栅极G2的结构。
另一方面，FWD元件Di中，作为半导体区域，具备与IGBT元件Tr共通的漂移区域10、与IGBT元件Tr共通的基极区域13、以及形成在漂移区域10的与基极区域13相反侧的n导电型的阴极区域12。另外，阴极区域12形成在与IGBT元件Tr的集电极区域11相同的面内。FWD元件Di中的基极区域13还能够改称作阳极区域。形成于FWD元件Di的沟槽栅极全部是伪栅极G2，其电位被设为与发射极电位(例如地电位：GND)相同的电位。此外，FWD元件Di中的基极区域13被设为发射极电位(GND)。
外周区域112是形成开关元件110的芯片外形的区域，是开关元件110的最外侧区域。如图4所示，在外周区域112，形成有用来使漂移区域10中的电场均匀的保护环16。保护环16是在表面13a的表层形成的p导电性的半导体区域。在半导体基板的平面视图中，保护环16将非单元区域113及单元区域111包围而形成为环状。单元区域111及非单元区域113被多重的保护环16包围。另外，如果将保护环16在与基极区域13相同的工序中形成，则能够抑制制造工序数，但不妨碍形成为与基极区域13不同的浓度及深度。
在非单元区域113中，如图2所示，形成有用于与外部电连接的焊盘114。在焊盘114，连接着未图示的键合线，例如电源VCC、栅极电压等经由该焊盘114被输入到单元区域111。电源VCC与开关元件110的连接布线、栅极布线、IGBT元件Tr的发射极布线及开尔文发射极布线等布线类从焊盘114延伸形成并到达单元区域111。如果将并联连接的多个开关元件110相互接近地安装，则在这些布线间会产生寄生电感L。
在本实施方式的非单元区域113中，如图4所示，形成有基极区域13及有源沟槽栅极G1。另外，在本实施方式中，基极区域13包括属于单元区域111的第1基极区域13b、和属于非单元区域113的第2基极区域13c。在本实施方式中，第1基极区域13b的形成工序和第2基极区域13c的形成工序分别地设置。即，第1基极区域13b和第2基极区域13c作为不同的扩散层而形成。
另一方面，没有形成发射极区域14及接触区域15。因此，对于非单元区域113，并不积极地期待作为IGBT元件Tr或FWD元件Di的功能。但是，在非单元区域113中形成的沟槽栅极是能够被施加栅极电压的有源沟槽栅极G1，在与发射极电极之间形成栅极－发射极间电容。即，与在非单元区域113中没有形成有源沟槽栅极G1的形态相比，能够形成追加的寄生电容C作为栅极－发射极间电容。
另外，在本实施方式中，在非单元区域113中相当于基极区域13的p导电型的第2基极区域13c一直形成到比单元区域111中的第1基极区域13b深的位置，将沟槽栅极的整体覆盖。有源沟槽栅极G1以与在单元区域111中形成的沟槽栅极相同的间隔、相同的深度形成为条带状。
此外，在非单元区域113中，有源沟槽栅极G1如图5所示，在正面观察半导体基板时，形成为不与焊盘114重叠。在本实施方式中，形成在单元区域111中的有源沟槽栅极G1以向非单元区域113大致延伸的方式形成。有源沟槽栅极G1以避开焊盘114的形成位置的方式引绕。
有源沟槽栅极G1的引绕方式并不限定于图5所示的具体例，能够任意地设计。另外，在图5中没有图示伪沟槽栅极G2。
接着，参照图6，说明开关元件110的集电极电压Vc、并联连接的2个IGBT元件Tr的发射极间电压ΔVe的动态。
如图6所示，在对有源沟槽栅极G1施加栅极电压的情况下IGBT元件导通。由此集电极电压下降。在集电极电压Vc下降而达到应收敛的大致一定值的定时，由于寄生电感L而产生电压振动。具体而言，在发射极电压Ve中由于寄生电感L而产生电压振动，结果，并联连接的2个IGBT元件Tr的发射极间电压ΔVe振动。将与该振动有关的振幅的最大值定义为电压振动dVe。
另外，在图6中，图示了来源于IGBT元件Tr的接通的电压振动dVe，但关于关断也是同样的。
接着，参照图7对采用本实施方式的半导体装置100的作用效果进行说明。
通过模拟，求出了当对形成在单元区域111中的栅极－发射极间电容以某种方法追加栅极－发射极间电容时、相对于追加的电容的电压振动dVe的变化。所述的某种方法，例如是将芯片电容安装到IGBT元件Tr的栅极－发射极间的方法，或者是如本实施方式那样在非单元区域113中形成基极区域13及有源沟槽栅极G1而故意地产生寄生电容C的方法。
图7是表示其结果的曲线图。图7中的横轴示出了追加的电容C相对于单元区域111中的栅极－发射极间电容即电容追加前的电容C0的比C/C0。纵轴示出了电容追加后的电压振动dVe相对于电容追加前的电压振动dVe0的比dVe/dVe0。
根据图6，由芯片电容的安装带来的栅极－发射极间电容的追加使电压振动dVe增加。推测这是因为将芯片电容向开关元件110连接时的布线使寄生电感增加。另一方面，在通过如本实施方式那样在非单元区域113中形成基极区域13及有源沟槽栅极G1而形成寄生电容C的形态下，在追加电容比为3以下的范围中，与没有追加电容的形态相比，能够降低电压振动dVe。
进而，由于将非单元区域113中的有源沟槽栅极G1避开形成焊盘114的位置而形成，所以不会使焊盘114的强度下降。
进而，由于非单元区域113中的基极区域13以将有源沟槽栅极G1的整体覆盖的方式形成到比单元区域111的基极区域13深的位置，所以能够使寄生电容C更大。
如上述那样，本实施方式的半导体装置100能够不损害焊盘114的可靠性地使栅极－发射极间的寄生电容变大，能够抑制电压振动dVe。
(第2实施方式)
在第1实施方式中，结合图4说明了在非单元区域113中将有源沟槽栅极G1以与单元区域111中的沟槽栅极相同的间隔形成的例子。相对于此，本实施方式的半导体装置100如图8所示，与单元区域111相比，使非单元区域113中的有源沟槽栅极G1的形成间隔较窄。
换言之，非单元区域113中的有源沟槽栅极G1在至少一部分区域中与单元区域111中的有源沟槽栅极G1的形成密度相比被形成为高密度。
由此，能够增大有源沟槽栅极G1与基极区域13的隔着绝缘膜的接触面积，所以能够使寄生电容C更大。
(第3实施方式)
在第1实施方式中，结合图4说明了在非单元区域113中将有源沟槽栅极G1形成为与单元区域111中的沟槽栅极相同深度的例子。相对于此，本实施方式的半导体装置100如图9所示，使非单元区域113中的有源沟槽栅极G1的形成深度比单元区域111深。
换言之，非单元区域113中的有源沟槽栅极G1，在至少一部分区域中与单元区域111中的有源沟槽栅极G1相比到达半导体基板的更深的位置。
由此，能够使有源沟槽栅极G1与基极区域13的隔着绝缘膜的接触面积变大，所以能够使寄生电容C更大。
通过第2实施方式中的有源沟槽栅极G1的形成密度的提高、并且使有源沟槽栅极G1的形成深度较深，能够更有效地使寄生电容C变大。
(第4实施方式)
除了上述各实施方式以外，如图10所示，通过在单元区域111的IGBT元件Tr和FWD元件Di的边界部分将FWD元件Di的一部分伪沟槽栅极G2替换为有源沟槽栅极G1，能够增大栅极－发射极间电容。另外，如本实施方式那样，在使FWD元件Di的一部分作为寄生电容C发挥功能的结构中，通过使FWD元件Di内的有源沟槽栅极G1的形成密度增加、使有源沟槽栅极G1的形成深度变深，能够使寄生电容C更大。
(其他实施方式)
以上，对本发明的优选的实施方式进行了说明，但本发明完全不受上述实施方式限制，在不脱离本发明的主旨的范围中能够各种各样地变形而实施。
在上述各实施方式中，关于非单元区域113中的有源沟槽栅极G1的引绕，例如如图5所示那样示出了是从单元区域111延伸的条带状的例子，但并不限定于该例。有源沟槽栅极G1能够以任意的形状形成在非单元区域113。
此外，在上述各实施方式中，示出了开关元件110是RC－IGBT的例子，但也可以是在单元区域111中没有形成FWD元件Di的单纯的IGBT。但是，在开关元件110是单纯的IGBT的情况下，无法如在第4实施方式中说明的那样在FWD元件Di侧形成寄生电容C。
将本发明依据实施例进行了记述，但应理解的是本发明并不限定于该实施例及构造。本发明也包含各种各样的变形例及等价范围内的变形。除此以外，将各种各样的组合及形态、还有在它们中仅包含一要素、其以上或其以下的组合或形态也包含在本发明的范畴或思想范围中。

Claims (6)

1.一种半导体装置，其特征在于，
具备：
多个开关元件；以及
半导体基板；
上述多个开关元件并联地连接而被驱动；
上述多个开关元件形成于半导体基板；
在上述半导体基板的平面视图下，上述多个开关元件分别具有：
单元区域(111)，形成有被施加栅极电压的有源沟槽栅极(G1)，作为IGBT发挥功能；
外周区域(112)，形成芯片外形；以及
非单元区域(113)，形成为将上述单元区域和上述外周区域分离，设置有对向上述单元区域的电连接进行中继的焊盘(114)；
在上述半导体基板的平面视图下，上述有源沟槽栅极还在上述非单元区域中形成在不与上述焊盘重叠的位置。
2.如权利要求1所述的半导体装置，其特征在于，
上述非单元区域中的上述有源沟槽栅极在至少一部分区域中相比于上述单元区域中的上述有源沟槽栅极的形成密度而言以高密度形成。
3.如权利要求1或2所述的半导体装置，其特征在于，
上述非单元区域中的上述有源沟槽栅极在至少一部分区域中相比于上述单元区域中的上述有源沟槽栅极而言到达上述半导体基板的更深位置而形成。
4.如权利要求1～3中任一项所述的半导体装置，其特征在于，
上述多个开关元件分别还具有形成在形成上述有源沟槽栅极的上述半导体基板的表层、由于上述有源沟槽栅极被施加上述栅极电压而产生沟道的基极区域；
上述基极区域具有属于上述单元区域的第1基极区域和属于上述非单元区域的第2基极区域；
在上述半导体基板的剖面视图下，上述第2基极区域在至少一部分区域中相比于上述第1基极区域的形成深度而言到达上述半导体基板的更深位置而形成。
5.如权利要求1～4中任一项所述的半导体装置，其特征在于，
上述单元区域具备作为IGBT发挥功能的IGBT区域(Tr)和作为续流二极管发挥功能的FWD区域(Di)；
上述有源沟槽栅极还形成在上述FWD区域中的与上述IGBT区域邻接的一部分区域。
6.如权利要求1～5中任一项所述的半导体装置，其特征在于，
上述非单元区域中的上述有源沟槽栅极与发射极电极之间的寄生电容相对于上述单元区域中的栅极－发射极间的寄生电容的电容比为3以下。
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