WO2018016284A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2018016284A1
WO2018016284A1 PCT/JP2017/023903 JP2017023903W WO2018016284A1 WO 2018016284 A1 WO2018016284 A1 WO 2018016284A1 JP 2017023903 W JP2017023903 W JP 2017023903W WO 2018016284 A1 WO2018016284 A1 WO 2018016284A1
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WIPO (PCT)
Prior art keywords
region
cell region
trench gate
active trench
gate
Prior art date
Application number
PCT/JP2017/023903
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English (en)
French (fr)
Inventor
河野　憲司
Original Assignee
株式会社デンソー
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Publication date
Application filed by 株式会社デンソー filed Critical 株式会社デンソー
Priority to CN201780044650.8A priority Critical patent/CN109478563B/zh
Publication of WO2018016284A1 publication Critical patent/WO2018016284A1/ja
Priority to US16/250,056 priority patent/US10734375B2/en

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Definitions

  • This disclosure relates to a semiconductor device in which a plurality of switching elements are driven in parallel.
  • a semiconductor device that can reduce switching loss and control output current by connecting a plurality of switching elements in parallel and turning on or off at an appropriate timing is known.
  • Parasitic inductance occurs between switching elements in parallel-driven semiconductor devices. For this reason, an induced electromotive force is generated at the time of switching, and the voltage oscillation and the oscillation of the output current accompanying the voltage oscillation are generated.
  • Patent Document 1 describes an example in which a parasitic capacitance between a gate electrode and an emitter electrode of a trench gate type IGBT element is used. A method of adding a chip capacitor on the mounting substrate is also conceivable.
  • a parasitic capacitance is obtained by adding a trench gate under a pad used as an electrode in an outer peripheral region that does not function as an IGBT element in a chip.
  • the structure for adding the capacitance is formed under the pad, which is functionally related to the addition of the capacitance and is reliable for the electrical connection. This is also not preferable.
  • parasitic inductance is generated in the wiring for connecting the chip capacitor, and the effect of suppressing voltage oscillation caused by the parasitic inductance cannot be sufficiently obtained.
  • an object of the present disclosure is to provide a semiconductor device for suppressing voltage oscillation without impairing the connection reliability of the pad.
  • a semiconductor device includes a plurality of switching elements and a semiconductor substrate.
  • the plurality of switching elements are connected and driven in parallel.
  • the plurality of switching elements are formed on a semiconductor substrate.
  • Each of the plurality of switching elements includes a cell region in which an active trench gate to which a gate voltage is applied is formed to function as an IGBT when the semiconductor substrate is viewed in plan, an outer peripheral region forming a chip outer shape, the cell region, A non-cell region formed so as to be separated from the outer peripheral region and provided with a pad that mediates electrical connection to the cell region.
  • the active trench gate is also formed at a position where it does not overlap the pad in the non-cell region when the semiconductor substrate is viewed in plan.
  • the active trench gate forming the parasitic capacitance is formed avoiding the formation position of the pad, the reliability related to the pad is not lowered.
  • the gate-emitter capacitance can be increased without impairing the reliability, and as a result, the voltage oscillation caused by the parallel connection of the IGBT elements can be suppressed.
  • FIG. 1 is an equivalent circuit diagram showing the configuration of the semiconductor device according to the first embodiment.
  • FIG. 2 is a top view showing a schematic configuration of the switching element
  • FIG. 3 is a cross-sectional view showing a cross section taken along line III-III in FIG.
  • FIG. 4 is a cross-sectional view showing a cross section taken along line IV-IV in FIG.
  • FIG. 5 is a top view showing the routing of the active trench gate in the non-cell region
  • FIG. 6 is a diagram showing changes in the collector voltage and the emitter voltage
  • FIG. 7 is a diagram showing a change in the voltage oscillation ratio with respect to the additional capacity ratio.
  • FIG. 8 is a cross-sectional view of the semiconductor device according to the second embodiment.
  • FIG. 9 is a cross-sectional view of the semiconductor device according to the third embodiment
  • FIG. 10 is a cross-sectional view of the semiconductor device according to the fourth embodiment.
  • the semiconductor device is used, for example, for a switch circuit in which a plurality of reverse conducting insulated gate bipolar transistors (RC-IGBT) are connected in parallel to obtain an output current.
  • RC-IGBT reverse conducting insulated gate bipolar transistors
  • FIG. 1 is an equivalent circuit of the semiconductor device 100 according to this embodiment.
  • the semiconductor device 100 includes a switching element 110 connected in series between a power supply VCC and a ground potential (GND) as a reference potential. Two sets are connected in parallel. That is, the plurality of switching elements 110 are connected in parallel to the power supply VCC.
  • the switching element 110 includes an IGBT element Tr.
  • two IGBT elements Tr are connected in parallel between the power supply VCC and the output OUT.
  • the collector terminal of the IGBT element Tr on the high side is connected to the power supply VCC side, and the emitter terminal is on the output OUT side.
  • a gate voltage can be applied to the gate terminal of each IGBT element Tr.
  • the collector terminal of the IGBT element Tr on the low side is connected to the output OUT side, and the emitter terminal is on the GND side.
  • the low-side IGBT element Tr is also connected in parallel to the output OUT.
  • the switching element 110 constituting the semiconductor device 100 in this embodiment is an RC-IGBT and includes a freewheeling diode element Di, but is omitted from the equivalent circuit shown in FIG.
  • the switching element 110 includes a parasitic capacitance C between the gate terminal and the emitter terminal of the IGBT element Tr. The structural reason why the parasitic capacitance C occurs will be described later.
  • Parasitic inductance L is generated between switching elements 110 connected in parallel.
  • FIG. 1 shows an example in which parasitic inductance L is generated in the connection wiring between the power source VCC and the switching element 110, the gate wiring, and the emitter wiring of the IGBT element Tr as a representative example. Parasitic inductance L may occur.
  • FIG. 3 is a cross-sectional view taken along the line III-III in FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 3 and 4, the trench gates G1 and G2 described later and the p-conductivity type semiconductor region are hatched, and the n-conductivity type semiconductor region is not hatched.
  • the switching element 110 is formed on a semiconductor substrate. As shown in FIG. 2, the switching element 110 is located on the periphery of the cell region 111 in which the IGBT element Tr and the free wheel diode (FWD) element Di are formed. An outer peripheral region 112 that forms an outer shape and a non-cell region 113 that is an outer periphery of the cell region 111 and is formed to separate the cell region 111 and the outer peripheral region 112 are provided.
  • the cell region 111 has an IGBT element Tr and an FWD element Di.
  • the IGBT element Tr and the FWD element Di have a strap structure that extends in the same direction and is alternately arranged in a direction orthogonal to the extending direction.
  • the IGBT element Tr and the FWD element Di correspond to an IGBT region and an FWD region, respectively.
  • the IGBT element Tr and the FWD element Di Detailed structures of the IGBT element Tr and the FWD element Di will be described with reference to FIG. As shown in FIG. 3, the left side of the drawing with the broken line as a boundary is the IGBT element Tr, and the right side of the drawing is the FWD element Di.
  • the IGBT element Tr includes an n conductivity type drift region 10, a p conductivity type collector region 11, a p conductivity type base region 13, and an n conductivity type emitter region 14 as semiconductor regions.
  • the IGBT element Tr includes a trench gate G1.
  • the drift region 10 is stacked on the collector region 11.
  • the base region 13 is stacked on the drift region 10.
  • Base region 13 is exposed at surface 13 a of the semiconductor substrate, and an emitter electrode (not shown) is connected to base region 13.
  • the trench gate G1 penetrates the base region 13 from the surface 13a and reaches the drift region 10.
  • Trench gate G1 is in contact with base region 13 and drift region 10 via an insulating film (not shown).
  • a contact region 15 related to the junction between the base region 13 and the emitter electrode is formed in a portion exposed to the surface 13 a sandwiched between the emitter regions 14.
  • the trench gate G1 with which the emitter region 14 is in contact is an active trench gate to which a gate voltage can be applied.
  • the active trench gate among the trench gates is denoted by reference numeral G1
  • the dummy gate to which no gate voltage is applied is denoted by reference numeral G2.
  • FIG. 3 shows an example in which all trench gates belonging to the IGBT element Tr are active trench gates G1, a configuration including a dummy gate G2 at a predetermined period may be adopted.
  • the FWD element Di is formed as a semiconductor region, the drift region 10 common to the IGBT element Tr, the base region 13 common to the IGBT element Tr, and the base region 13 opposite to the drift region 10.
  • the cathode region 12 is formed in the same plane as the collector region 11 in the IGBT element Tr.
  • the base region 13 in the FWD element Tr can also be called an anode region.
  • the trench gates formed in the FWD element Di are all dummy gates G2, and the potential thereof is the same as the emitter potential (for example, ground potential: GND). Further, the base region 13 in the FWD element Di is set to the emitter potential (GND).
  • the outer peripheral area 112 is an area for forming the chip outline of the switching element 110 and is the outermost area of the switching element 110.
  • a guard ring 16 for making the electric field in the drift region 10 uniform is formed in the outer peripheral region 112.
  • the guard ring 16 is a p-conductive semiconductor region formed on the surface layer of the surface 13a.
  • the guard ring 16 is formed in an annular shape so as to surround the non-cell region 113 and the cell region 111 when the semiconductor substrate is viewed in plan.
  • the cell region 111 and the non-cell region 113 are surrounded by multiple guard rings 16. If the guard ring 16 is formed in the same process as the base region 13, the number of manufacturing steps can be suppressed, but it does not prevent the guard ring 16 from being formed at a concentration and depth different from that of the base region 13.
  • a pad 114 is formed for electrical connection with the outside.
  • a bonding wire (not shown) is connected to the pad 114, and for example, a power supply VCC or a gate voltage is input to the cell region 111 via the pad 114.
  • Wirings such as a connection wiring between the power supply VCC and the switching element 110, a gate wiring, an emitter wiring of the IGBT element Tr, and a Kelvin emitter wiring are formed extending from the pad 114 to reach the cell region 111.
  • the base region 13 includes a first base region 13b belonging to the cell region 111 and a second base region 13c belonging to the non-cell region 113.
  • a process for forming the first base region 13b and a process for forming the second base region 13c are provided separately. That is, the first base region 13b and the second base region 13c are formed as different diffusion layers.
  • the non-cell region 113 is not expected to actively function as the IGBT element Tr or the FWD element Di.
  • the trench gate formed in the non-cell region 113 is an active trench gate G1 to which a gate voltage can be applied, and forms a gate-emitter capacitance with the emitter electrode. That is, an additional parasitic capacitance C can be formed as a gate-emitter capacitance as compared with the case where the active trench gate G1 is not formed in the non-cell region 113.
  • the p-conductivity type second base region 13c corresponding to the base region 13 in the non-cell region 113 is formed to a position deeper than the first base region 13a in the cell region 111, and the entire trench gate is formed. It is made to cover.
  • the active trench gate G1 is formed in stripes at the same interval and the same depth as the trench gate formed in the cell region 111.
  • the active trench gate G1 is formed so as not to overlap the pad 114 when the semiconductor substrate is viewed from the front, as shown in FIG.
  • the active trench gate G ⁇ b> 1 formed in the cell region 111 is formed so as to extend substantially to the non-cell region 113.
  • the active trench gate G1 is routed so as to avoid the position where the pad 114 is formed.
  • the way of routing the active trench gate G1 is not limited to the specific example shown in FIG. 5, and can be arbitrarily designed. Note that the dummy trench gate G2 is not shown in FIG.
  • FIG. 6 shows the voltage oscillation dVe derived from the turn-on of the IGBT element Tr, the same applies to the turn-off.
  • the chip capacitor is mounted between the gate and the emitter of the IGBT element Tr, or the parasitic region C is formed by forming the base region 13 and the active trench gate G1 in the non-cell region 113 as in the present embodiment. Is a method of intentionally generating
  • FIG. 7 is a graph showing the results.
  • the horizontal axis in FIG. 7 indicates the ratio C / C 0 of the added capacitance C to the gate-emitter capacitance in the cell region 111, that is, the capacitance C 0 before the addition of the capacitance.
  • the vertical axis represents the ratio dVe / dVe 0 of the voltage oscillation dVe after the addition of the capacitance to the voltage oscillation dVe 0 before the addition of the capacitance.
  • the addition of the gate-emitter capacitance by mounting the chip capacitor increases the voltage oscillation dVe.
  • the wiring when connecting the chip capacitor to the switching element 110 increases the parasitic inductance.
  • the parasitic capacitance C is formed by forming the base region 13 and the active trench gate G1 in the non-cell region 113 as in the present embodiment, there is no additional capacitance when the additional capacitance ratio is 3 or less. Compared to the above, the voltage oscillation dVe can be reduced.
  • the active trench gate G1 in the non-cell region 113 is formed avoiding the position where the pad 114 is formed, the strength of the pad 114 is not lowered.
  • the parasitic capacitance C is made larger. Can do.
  • the semiconductor device 100 can increase the parasitic capacitance between the gate and the emitter without impairing the reliability related to the pad 114, and can suppress the voltage oscillation dVe.
  • the formation interval of the active trench gate G1 in the non-cell region 113 is narrower than that of the cell region 111.
  • the active trench gate G1 in the non-cell region 113 is formed at a higher density than at least a part of the active trench gate G1 in the cell region 111.
  • the contact area between the active trench gate G1 and the base region 13 through the insulating film can be increased, the parasitic capacitance C can be further increased.
  • the formation depth of the active trench gate G1 in the non-cell region 113 is deeper than that of the cell region 111.
  • the active trench gate G1 in the non-cell region 113 is formed so as to reach a deeper position in the semiconductor substrate than in the active trench gate G1 in the cell region 111 in at least a part of the region.
  • the contact area between the active trench gate G1 and the base region 13 through the insulating film can be increased, the parasitic capacitance C can be further increased.
  • the parasitic capacitance C can be increased more effectively by increasing the formation density of the active trench gate G1 and increasing the formation depth of the active trench gate G1 in the second embodiment.
  • the active trench gate G1 is routed in the non-cell region 113 as shown in FIG. 5, for example, in the form of a stripe extending from the cell region 111.
  • the present invention is not limited to this example. It is not something.
  • the active trench gate G1 can be formed in the non-cell region 113 in any shape.
  • the switching element 110 is an RC-IGBT.
  • a simple IGBT in which the FWD element Di is not formed in the cell region 111 may be used.
  • the switching element 110 is a simple IGBT, the parasitic capacitance C cannot be formed on the FWD element Di side as described in the fourth embodiment.

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Abstract

半導体装置は、複数のスイッチング素子と、半導体基板と、を備える。複数のスイッチング素子は、並列に接続されて駆動されており、複数のスイッチング素子は半導体基板に形成されて成る。複数のスイッチング素子の各々は、半導体基板を平面視したとき、ゲート電圧が印加されるアクティブトレンチゲート（Ｇ１）が形成されてＩＧＢＴとして機能するセル領域（１１１）と、チップ外形を成す外周領域（１１２）と、セル領域と外周領域とを分離するように形成され、セル領域への電気的接続を仲介するパッド（１１４）が設置される非セル領域（１１３）と、を有する。アクティブトレンチゲートは、半導体基板を平面視したとき、非セル領域においてパッドにオーバーラップしない位置にも形成される。

Description

半導体装置 関連出願の相互参照
　本出願は、２０１６年７月２１日に出願された日本特許出願番号２０１６－１４３３００号に基づくもので、ここにその記載内容を援用する。
　本開示は、複数のスイッチング素子が並列駆動される半導体装置に関する。
　複数のスイッチング素子を並列に接続して適切なタイミングでオンまたはオフを行うことにより、スイッチング時の損失を低減したり出力電流の制御をしたりできる半導体装置が知られている。
　並列駆動の半導体装置ではスイッチング素子間に寄生インダクタンスが生じる。このため、スイッチング時に誘導起電力を生じてしまい、電圧振動および電圧振動に伴う出力電流の振動を生じてしまう。
　例えばスイッチング素子がＩＧＢＴ素子の場合には、ゲート－エミッタ間に容量を追加して電圧振動を抑制する方法が知られている。特許文献１では、トレンチゲート型のＩＧＢＴ素子のゲート電極とエミッタ電極間の寄生容量を利用する例が記載されている。また、実装基板上にチップコンデンサを追加する方法も考えられる。
特開２０１１－１９２８２２号公報
　特許文献１に記載の半導体装置では、チップのうちＩＧＢＴ素子として機能しない外周領域のうち、電極として利用されるパッド下にトレンチゲートを追加して寄生容量を得る。しかしながら、パッドはワイヤボンディングの際に比較的大きな応力を受けるため、パッド下に容量追加のための構造が形成されていることは、容量追加に係る機能的にも、電気的接続に係る信頼性的にも好ましくない。また、実装基板上に別途チップコンデンサを追加する形態では、チップコンデンサを接続するための配線に寄生インダクタンスを生じてしまい、寄生インダクタンスに起因する電圧振動を抑制する効果を十分に得られないという課題が見出された。
　そこで、本開示は、パッドの接続信頼性を損なうことなく、電圧振動を抑制するための半導体装置を提供することを目的とする。
　本開示の一態様に係る半導体装置は、複数のスイッチング素子と、半導体基板と、を備える。複数のスイッチング素子は、並列に接続されて駆動されている。複数のスイッチング素子は半導体基板に形成されて成る。複数のスイッチング素子の各々は、半導体基板を平面視したとき、ゲート電圧が印加されるアクティブトレンチゲートが形成されてＩＧＢＴとして機能するセル領域と、チップ外形を成す外周領域と、前記セル領域と前記外周領域とを分離するように形成され、前記セル領域への電気的接続を仲介するパッドが設置される非セル領域と、を有する。アクティブトレンチゲートは、半導体基板を平面視したとき、非セル領域において前記パッドにオーバーラップしない位置にも形成される。
　これによれば、セル領域以外の非セル領域においてもゲート－エミッタ間に、寄生容量として容量を追加することができる。容量の追加がチップコンデンサの外部接続によるものではないため、寄生インダクタンスの悪影響を受けることなく、ゲート－エミッタ間容量を増加することができる。
　さらに、寄生容量を形成するアクティブトレンチゲートはパッドの形成位置を避けて形成されるので、パッドに係る信頼性を低下されることがない。
　このように、この半導体装置によれば、信頼性を損なうことなくゲート－エミッタ間容量を増加することができ、ひいてはＩＧＢＴ素子の並列接続に起因する電圧振動を抑制することができる。
　本開示についての上記目的およびその他の目的、特徴や利点は、添付の図面を参照しながら下記の詳細な記述により、より明確になる。その図面は、
図１は、第１実施形態にかかる半導体装置の構成を示す等価回路図であり、 図２は、スイッチング素子の概略構成を示す上面図であり、 図３は、図２におけるＩＩＩ－ＩＩＩ線に沿う断面を示す断面図であり、 図４は、図２におけるＩＶ－ＩＶ線に沿う断面を示す断面図であり、 図５は、非セル領域におけるアクティブトレンチゲートの引き回しを示す上面図であり、 図６は、コレクタ電圧およびエミッタ電圧の変化を示す図であり、 図７は、追加容量比に対する電圧振動比の変化をしめす図であり、 図８は、第２実施形態にかかる半導体装置の断面図であり、 図９は、第３実施形態にかかる半導体装置の断面図であり、及び、 図１０は、第４実施形態にかかる半導体装置の断面図である。
　以下、本開示の実施の形態を図面に基づいて説明する。なお、以下の各図相互において、互いに同一もしくは均等である部分に、同一符号を付与する。
　（第１実施形態）
　最初に、図１を参照して、本実施形態に係る半導体装置１００の概略構成について説明する。
　本実施形態における半導体装置は、例えば、複数の逆導通絶縁ゲートバイポーラトランジスタ（ＲＣ－ＩＧＢＴ）が並列に接続されて出力電流を得るスイッチ回路に供される。
　図１は本実施形態における半導体装置１００の等価回路である図１に示すように、半導体装置１００は、電源ＶＣＣから基準電位たるグランド電位（ＧＮＤ）の間に直列接続されたスイッチング素子１１０が、２組並列に接続されて成る。すなわち、複数のスイッチング素子１１０が電源ＶＣＣに対して並列に接続されている。スイッチング素子１１０はＩＧＢＴ素子Ｔｒを備えている。本実施形態では、２個のＩＧＢＴ素子Ｔｒが電源ＶＣＣと出力ＯＵＴの間で並列に接続されている。ハイサイド側におけるＩＧＢＴ素子Ｔｒのコレクタ端子は電源ＶＣＣ側に接続され、エミッタ端子は出力ＯＵＴ側である。また、各ＩＧＢＴ素子Ｔｒのゲート端子にはゲート電圧が印加可能にされている。なお、ローサイド側におけるＩＧＢＴ素子Ｔｒのコレクタ端子は出力ＯＵＴ側に接続され、エミッタ端子はＧＮＤ側である。ローサイド側のＩＧＢＴ素子Ｔｒも出力ＯＵＴに対して並列に接続されている。
　なお、後述するように、本実施形態における半導体装置１００を構成するスイッチング素子１１０はＲＣ－ＩＧＢＴであり、還流ダイオード素子Ｄｉを備えているが、図１に示す等価回路では省略している。
　スイッチング素子１１０は、ＩＧＢＴ素子Ｔｒのゲート端子とエミッタ端子との間に寄生容量Ｃを備えている。寄生容量Ｃが生じる構造的理由は追って説明する。
　並列接続されたスイッチング素子１１０の間には寄生インダクタンスＬが生じる。図１においては、代表例として電源ＶＣＣとスイッチング素子１１０との接続配線、ゲート配線、ＩＧＢＴ素子Ｔｒのエミッタ配線に寄生インダクタンスＬが生じる例を示しているが、例えばケルビンエミッタ配線やほかの配線でも、寄生インダクタンスＬが生じうる。
　次に、図２～図５を参照して、ＩＧＢＴ素子Ｔｒおよび寄生容量Ｃの詳しい構成について説明する。複数のスイッチング素子１１０は互いに等価であり、ひいては各ＩＧＢＴ素子Ｔｒ、各還流ダイオード素子Ｄｉ、および、寄生容量Ｃはそれぞれ等価であるから、ひとつのスイッチング素子１１０について説明する。
　なお、図３は、図２におけるＩＩＩ－ＩＩＩ線に沿う断面図である。また、図４は、図２におけるＩＶ－ＩＶ線に沿う断面図である。図３および図４では、後述するトレンチゲートＧ１，Ｇ２およびｐ導電型の半導体領域にハッチングを付し、ｎ導電型の半導体領域にはハッチングを付していない。
　スイッチング素子１１０は半導体基板に形成され、図２に示すように、ＩＧＢＴ素子Ｔｒと還流ダイオード（ＦＷＤ）素子Ｄｉが形成されたセル領域１１１と、セル領域１１１の外周に位置し、スイッチング素子１１０の外形を成す外周領域１１２と、セル領域１１１の外周であってセル領域１１１と外周領域１１２とを分離するように形成された非セル領域１１３とを備えている。
　セル領域１１１は、ＩＧＢＴ素子Ｔｒと、ＦＷＤ素子Ｄｉとを有している。ＩＧＢＴ素子ＴｒとＦＷＤ素子Ｄｉは互いに同一方向に延設され、延設方向と直交する方向に交互に配置されたストラップ構造となっている。ＩＧＢＴ素子ＴｒおよびＦＷＤ素子Ｄｉは、それぞれ、ＩＧＢＴ領域、ＦＷＤ領域に相当する。
　ＩＧＢＴ素子ＴｒおよびＦＷＤ素子Ｄｉの詳しい構造について図３を参照して説明する。図３に示すように、破線を境界として紙面左側がＩＧＢＴ素子Ｔｒであり、紙面右側がＦＷＤ素子Ｄｉである。
　ＩＧＢＴ素子Ｔｒは、半導体領域として、ｎ導電型のドリフト領域１０と、ｐ導電型のコレクタ領域１１と、ｐ導電型のベース領域１３と、ｎ導電型のエミッタ領域１４と、を備えている。また、ＩＧＢＴ素子Ｔｒは、トレンチゲートＧ１を備えている。
　ドリフト領域１０はコレクタ領域１１上に積層されている。ベース領域１３はドリフト領域１０上に積層されている。ベース領域１３は半導体基板の表面１３ａに露出しており図示しないエミッタ電極がベース領域１３に接続される。トレンチゲートＧ１は、表面１３ａからベース領域１３を貫通してドリフト領域１０に達している。トレンチゲートＧ１は図示しない絶縁膜を介してベース領域１３およびドリフト領域１０に接している。なお、ベース領域１３のうち、エミッタ領域１４に挟まれる表面１３ａに露出した部分には、ベース領域１３とエミッタ電極との接合に係るコンタクト領域１５が形成されている。
　ＩＧＢＴ素子Ｔｒに属するトレンチゲートのうち、エミッタ領域１４が接するようにされたトレンチゲートＧ１はゲート電圧が印加可能にされたアクティブトレンチゲートである。図３および図４ではトレンチゲートのうちアクティブトレンチゲートに符号Ｇ１を付し、ゲート電圧が印加されないダミーゲートには符号Ｇ２を付す。図３では、ＩＧＢＴ素子Ｔｒに属するすべてのトレンチゲートがアクティブトレンチゲートＧ１である例を示したが、所定の周期でダミーゲートＧ２を含む構成としても良い。
　一方、ＦＷＤ素子Ｄｉは、半導体領域として、ＩＧＢＴ素子Ｔｒと共通のドリフト領域１０と、ＩＧＢＴ素子Ｔｒと共通のベース領域１３と、ドリフト領域１０に対してベース領域１３とは反対側に形成されたｎ導電型のカソード領域１２と、を備えている。なお、カソード領域１２はＩＧＢＴ素子Ｔｒにおけるコレクタ領域１１と同一面内に形成されている。ＦＷＤ素子Ｔｒにおけるベース領域１３はアノード領域と別名することもできる。ＦＷＤ素子Ｄｉに形成されたトレンチゲートはすべてダミーゲートＧ２であり、その電位はエミッタ電位（例えばグランド電位：ＧＮＤ）と同電位とされている。また、ＦＷＤ素子Ｄｉにおけるベース領域１３はエミッタ電位（ＧＮＤ）とされている。
　外周領域１１２は、スイッチング素子１１０のチップ外形を形成する領域であり、スイッチング素子１１０の最外領域である。図４に示すように、外周領域１１２には、ドリフト領域１０における電界を均一にするためのガードリング１６が形成されている。ガードリング１６は、表面１３ａの表層に形成されるｐ導電性の半導体領域である。ガードリング１６は、半導体基板を平面視したとき、非セル領域１１３ひいてはセル領域１１１を取り囲むように環状に形成される。セル領域１１１および非セル領域１１３は幾重のガードリング１６に取り囲まれている。なお、ガードリング１６はベース領域１３と同一工程で形成されるようにすれば、製造工程数を抑制することができるが、ベース領域１３と異なる濃度および深さに形成することを妨げない。
　非セル領域１１３には、図２に示すように、外部との電気的接続を担うパッド１１４が形成されている。パッド１１４には、図示しないボンディングワイヤが接続され、例えば電源ＶＣＣやゲート電圧などが該パッド１１４を介してセル領域１１１に入力される。電源ＶＣＣとスイッチング素子１１０との接続配線、ゲート配線、ＩＧＢＴ素子Ｔｒのエミッタ配線およびケルビンエミッタ配線などの配線類はパッド１１４から延びて形成されてセル領域１１１に至る。並列接続される複数のスイッチング素子１１０が互いに近傍に実装されると、それら配線間に寄生インダクタンスＬが生じることとなる。
　本実施形態における非セル領域１１３には、図４に示すように、ベース領域１３およびアクティブトレンチゲートＧ１が形成されている。なお、本実施形態において、ベース領域１３は、セル領域１１１に属する第１ベース領域１３ｂと、非セル領域１１３に属する第２ベース領域１３ｃとにより構成されている。本実施形態では、第１ベース領域１３ｂの形成工程と第２ベース領域１３ｃの形成工程は別に設けられている。すなわち、第１ベース領域１３ｂと第２ベース領域１３ｃとは、異なる拡散層として形成されている。
　一方で、エミッタ領域１４およびコンタクト領域１５は形成されていない。このため、非セル領域１１３はＩＧＢＴ素子ＴｒあるいはＦＷＤ素子Ｄｉとしての機能が積極的に期待されるものではない。しかしながら、非セル領域１１３に形成されたトレンチゲートはゲート電圧が印加され得るアクティブトレンチゲートＧ１であり、エミッタ電極との間にゲート－エミッタ間容量を成す。すなわち、非セル領域１１３にアクティブトレンチゲートＧ１が形成されていない態様に較べて、ゲート－エミッタ間容量として、追加の寄生容量Ｃを形成することができる。
　なお、本実施形態では、非セル領域１１３においてベース領域１３に相当するｐ導電型の第２ベース領域１３ｃは、セル領域１１１における第１ベース領域１３ａよりも深い位置まで形成され、トレンチゲートの全体を覆うようにされている。アクティブトレンチゲートＧ１は、セル領域１１１に形成されたトレンチゲートと同一間隔、同一深さでストライプ状に形成されている。
　また、非セル領域１１３において、アクティブトレンチゲートＧ１は、図５に示すように、半導体基板を正面視したときに、パッド１１４にオーバーラップしないように形成されている。本実施形態では、セル領域１１１に形成されたアクティブトレンチゲートＧ１が非セル領域１１３に略延伸するように形成されている。アクティブトレンチゲートＧ１はパッド１１４の形成位置を避けるように引き回される。
　アクティブトレンチゲートＧ１の引き回し方は、図５に示される具体例に限定されることはなく、任意に設計することができる。なお、図５にはダミートレンチゲートＧ２は図示していない。
　次に、図６を参照して、スイッチング素子１１０におけるコレクタ電圧Ｖｃ、並列接続された２つのＩＧＢＴ素子Ｔｒのエミッタ間電圧ΔＶｅの挙動について説明する。
　図６に示すように、アクティブトレンチゲートＧ１にゲート電圧が印加されるとＩＧＢＴ素子がオンする。これによりコレクタ電圧は低下する。コレクタ電圧Ｖｃが低下して収束すべき略一定値に達するタイミングで、寄生インダクタンスＬに起因して電圧振動を生じる。具体的には、エミッタ電圧Ｖｅにおいて寄生インダクタンスＬに起因して電圧振動を生じ、その結果、並列接続された２つのＩＧＢＴ素子Ｔｒのエミッタ間電圧ΔＶｅが振動する。この振動にかかる振幅の最大値を電圧振動ｄＶｅと定義する。
　なお、図６においては、ＩＧＢＴ素子Ｔｒのターンオンに由来する電圧振動ｄＶｅについて図示しているが、ターンオフについても同様である。
　次に、図７を参照して、本実施形態に係る半導体装置１００を採用することによる作用効果について説明する。
　セル領域１１１に形成されるゲート－エミッタ間容量に対して、何らかの方法でゲート－エミッタ間容量を追加するとき、追加する容量に対する電圧振動ｄＶｅの変化がシミュレーションにより求められた。何らかの方法とは、例えばチップコンデンサをＩＧＢＴ素子Ｔｒのゲート－エミッタ間に実装する方法、あるいは、本実施形態のように非セル領域１１３にベース領域１３およびアクティブトレンチゲートＧ１を形成して寄生容量Ｃを意図的に生じさせる方法である。
　図７はその結果を示すグラフである。図７における横軸は、セル領域１１１におけるゲート－エミッタ間容量、すなわち容量の追加前の容量Ｃ０に対する、追加する容量Ｃの比Ｃ／Ｃ０を示している。縦軸は容量の追加前の電圧振動ｄＶｅ０に対する、容量追加後の電圧振動ｄＶｅの比ｄＶｅ／ｄＶｅ０を示している。
　図６によれば、チップコンデンサの実装によるゲート－エミッタ間容量の追加は、電圧振動ｄＶｅを増加させてしまう。これは、チップコンデンサをスイッチング素子１１０に接続する際の配線が、寄生インダクタンスを増加させてしまうことに起因すると推察される。一方、本実施形態のように非セル領域１１３にベース領域１３およびアクティブトレンチゲートＧ１を形成することにより寄生容量Ｃを形成する形態では、追加容量比が３以下の範囲において、追加容量が無い形態に較べて、電圧振動ｄＶｅを低減することができる。
　さらに、非セル領域１１３におけるアクティブトレンチゲートＧ１は、パッド１１４が形成される位置を避けて形成されるので、パッド１１４の強度を低下させることがない。
　さらに、非セル領域１１３におけるベース領域１３は、アクティブトレンチゲートＧ１の全体を覆うように、セル領域１１１のベース領域１３に較べて深い位置まで形成されているから、寄生容量Ｃをより大きくすることができる。
　上記したように、本実施形態における半導体装置１００は、パッド１１４に係る信頼性を損なうことなく、ゲート－エミッタ間の寄生容量を大きくすることができ、電圧振動ｄＶｅを抑制することができる。
　（第２実施形態）
　第１実施形態では、非セル領域１１３において、アクティブトレンチゲートＧ１が、セル領域１１１におけるトレンチゲートと同一間隔で形成されている例を、図４とともに説明した。これに対して、本実施形態における半導体装置１００は、図８に示すように、非セル領域１１３におけるアクティブトレンチゲートＧ１の形成間隔が、セル領域１１１に較べて狭くされている。
　換言すれば、非セル領域１１３におけるアクティブトレンチゲートＧ１は、少なくとも一部の領域において、セル領域１１１におけるアクティブトレンチゲートＧ１の形成密度に較べて、高密度に形成されている。
　これによれば、アクティブトレンチゲートＧ１とベース領域１３との絶縁膜を介した接触面積を大きくできるから、寄生容量Ｃをより大きくすることができる。
　（第３実施形態）
　第１実施形態では、非セル領域１１３において、アクティブトレンチゲートＧ１が、セル領域１１１におけるトレンチゲートと同一深さで形成されている例を、図４とともに説明した。これに対して、本実施形態における半導体装置１００は、図９に示すように、非セル領域１１３におけるアクティブトレンチゲートＧ１の形成深さが、セル領域１１１に較べて深くされている。
　換言すれば、非セル領域１１３におけるアクティブトレンチゲートＧ１は、少なくとも一部の領域において、セル領域１１１におけるアクティブトレンチゲートＧ１に較べて、半導体基板の深い位置に達するように形成されている。
　これによれば、アクティブトレンチゲートＧ１とベース領域１３との絶縁膜を介した接触面積を大きくできるから、寄生容量Ｃをより大きくすることができる。
　第２実施形態におけるアクティブトレンチゲートＧ１の形成密度を高めることと共に、アクティブトレンチゲートＧ１の形成深さを深くすることにより、より効果的に寄生容量Ｃを大きくすることができる。
　（第４実施形態）
　上記した各実施形態に加えて、図１０に示すように、セル領域１１１のＩＧＢＴ素子ＴｒとＦＷＤ素子Ｄｉの境界部分において、ＦＷＤ素子Ｄｉの一部のダミートレンチゲートＧ２を、アクティブトレンチゲートＧ１に置き換えることにより、ゲート－エミッタ間容量を増大することができる。なお、本実施形態のように、ＦＷＤ素子Ｄｉの一部が寄生容量Ｃとして機能するようにされた構成においては、ＦＷＤ素子Ｄｉ内のアクティブトレンチゲートＧ１の形成密度を増加させたり、アクティブトレンチゲートＧ１の形成深さを深くしたりすることにより、より寄生容量Ｃを大きくすることができる。
　（その他の実施形態）
　以上、本開示の好ましい実施形態について説明したが、本開示は上記した実施形態になんら制限されることなく、本開示の主旨を逸脱しない範囲において、種々変形して実施することが可能である。
　上記した各実施形態では、非セル領域１１３におけるアクティブトレンチゲートＧ１の引き回しについて、例えば図５に示したように、セル領域１１１から延伸したストライプ状である例を示したが、この例に限定されるものではない。アクティブトレンチゲートＧ１は任意の形状で非セル領域１１３に形成することができる。
　また、上記した各実施形態では、スイッチング素子１１０がＲＣ－ＩＧＢＴである例を示したが、セル領域１１１にＦＷＤ素子Ｄｉが形成されていない単なるＩＧＢＴでも良い。ただし、スイッチング素子１１０が単なるＩＧＢＴである場合には、第４実施形態で説明したようにＦＷＤ素子Ｄｉ側に寄生容量Ｃを形成することはできない。
　本開示は、実施例に準拠して記述されたが、本開示は当該実施例や構造に限定されるものではないと理解される。本開示は、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。

Claims (6)

  1. 　複数のスイッチング素子と、
    　半導体基板と、を備え、
    　前記複数のスイッチング素子は、並列に接続されて駆動されており、
    　前記複数のスイッチング素子は半導体基板に形成されて成り、
    　前記複数のスイッチング素子の各々は、前記半導体基板を平面視したとき、
    　ゲート電圧が印加されるアクティブトレンチゲート（Ｇ１）が形成されてＩＧＢＴとして機能するセル領域（１１１）と、
    　チップ外形を成す外周領域（１１２）と、
    　前記セル領域と前記外周領域とを分離するように形成され、前記セル領域への電気的接続を仲介するパッド（１１４）が設置される非セル領域（１１３）と、を有し、
    　前記アクティブトレンチゲートは、前記半導体基板を平面視したとき、前記非セル領域において前記パッドにオーバーラップしない位置にも形成される半導体装置。
  2. 　前記非セル領域における前記アクティブトレンチゲートは、少なくとも一部の領域において、前記セル領域における前記アクティブトレンチゲートの形成密度に較べて、高密度に形成される請求項１に記載の半導体装置。
  3. 　前記非セル領域における前記アクティブトレンチゲートは、少なくとも一部の領域において、前記セル領域における前記アクティブトレンチゲートに較べて、前記半導体基板の深い位置に達するように形成される請求項１または請求項２に記載の半導体装置。
  4. 　前記複数のスイッチング素子の各々は、前記アクティブトレンチゲートが形成される前記半導体基板の表層に形成され、前記アクティブトレンチゲートに前記ゲート電圧が印加されることによりチャネルを生じるベース領域をさらに有し、
    　前記ベース領域は、前記セル領域に属する第１ベース領域と、前記非セル領域に属する第２ベース領域とを有し、
    　前記第２ベース領域は、少なくとも一部の領域において、前記半導体基板を断面視したとき、前記第１ベース領域の形成深さに較べて、前記半導体基板の深い位置に達するように形成される請求項１～３のいずれか１項に記載の半導体装置。
  5. 　前記セル領域は、ＩＧＢＴとして機能するＩＧＢＴ領域（Ｔｒ）と、還流ダイオードとして機能するＦＷＤ領域（Ｄｉ）とを備え、
    　前記アクティブトレンチゲートは、前記ＦＷＤ領域における前記ＩＧＢＴ領域に隣接する一部の領域にも形成される請求項１～４のいずれか１項に記載の半導体装置。
  6. 　前記非セル領域における前記アクティブトレンチゲートとエミッタ電極との間の寄生容量は、前記セル領域におけるゲート－エミッタ間の寄生容量に対する容量比として、３以下とされる請求項１～５のいずれか１項に記載の半導体装置。
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US10734375B2 (en) 2020-08-04
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