CN107924942B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN107924942B
CN107924942B CN201680049102.XA CN201680049102A CN107924942B CN 107924942 B CN107924942 B CN 107924942B CN 201680049102 A CN201680049102 A CN 201680049102A CN 107924942 B CN107924942 B CN 107924942B
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河野宪司
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Abstract

一种半导体装置,具备半导体基板(10),该半导体基板(10)具有:第1导电型的漂移层(11)、形成于漂移层的表层部的第2导电型的基极层(12)、以及形成于漂移层中的与基极层侧相反的一侧的第2导电型的集电极层(21)以及第1导电型的阴极层(22)。将半导体基板中的作为IGBT元件动作的区域设为IGBT区域(1a),并且将作为二极管元件动作的区域设为二极管区域(1b),交替地重复形成有IGBT区域和二极管区域。IGBT区域和二极管区域由集电极层与阴极层的边界划分。将集电极层设为第1集电极层,半导体装置在半导体基板中的形成有第1集电极层以及阴极层的一侧的面上设置有第2导电型杂质浓度高于第1集电极层的第2集电极层。

Description

半导体装置
相关申请的彼此参照
本申请基于2015年8月28日申请的日本专利申请2015-169396号,这里引用其记载内容。
技术领域
本公开涉及一种半导体装置,其具有形成有绝缘栅型场效应晶体管(以下,称作IGBT(Insulated Gate Bipolar Transistor))的IGBT区域和形成有续流二极管(以下,称作FWD(Free Wheeling Diode))的二极管区域。
背景技术
以往,例如作为逆变器等中所使用的开关元件,提出了一种具有将FWD与IGBT一起设置于1个芯片中的RC-IGBT(逆导IGBT(Reverse-Conducting IGBT)的简称)构造的半导体装置(例如,参照专利文献1)。
在该半导体装置中,在构成N-型的漂移层的半导体基板的表层部形成有基极层,并以贯通基极层的方式形成有沟槽栅极构造。另外,在半导体基板的背面侧形成有P型的集电极层以及N型的阴极层,在基极层中的位于集电极层上的部分形成有N型的发射极区域。另外,在漂移层中的集电极层与发射极层的边界位置,形成有N型的场阻挡(以下,称作FS(FieldStop))层。而且,在半导体基板的表面侧形成有与基极层以及发射极区域电连接的上部电极,在半导体基板的背面侧形成有与集电极层以及阴极层电连接的下部电极。
在这样的构成中,在半导体基板的背面侧将形成有集电极层的区域设为IGBT区域,将形成有阴极层的区域设为二极管区域。换句话说,上述半导体装置以集电极层与阴极层的边界作为IGBT区域与二极管区域的边界。
现有技术文献
专利文献
专利文献1:日本特开2011-181886号公报
发明内容
然而,在将IGBT区域与FWD区域设置于1个芯片的构造中,考虑IGBT的开关损耗而将P型的集电极层设为相对较低的浓度。因此,在FWD的恢复动作时,不会从形成于IGBT区域的低浓度的集电极层充分注入空穴,恢复波形振动,浪涌电压容易增加。
与此相对,如果提高集电极层的杂质浓度,则空穴注入量增加,能够抑制恢复波形的振动,并且能够抑制浪涌电压,但将会导致IGBT的开关损耗增加。即,恢复时的浪涌电压的抑制与IGBT的开关损耗的减少处于此消彼长的关系,难以实现兼得。特别是,在近年来的缩窄了沟槽栅极构造的间隔的微小单元构造中,空穴的蓄积效应高,因此空穴容易堆积于半导体基板内,为了避免开关损耗,需要降低背面侧的集电极层的杂质浓度。由此,FWD的恢复波形的振动变得更加显著。
本公开的目的在于,提供一种能够同时实现恢复时的浪涌电压的抑制以及IGBT的开关损耗的减少的半导体装置。
根据本公开的第一方式,半导体装置具备半导体基板,该半导体基板具有:第1导电型的漂移层;第2导电型的基极层,形成于漂移层的表层部;以及第2导电型的集电极层及第1导电型的阴极层,形成于漂移层中的与基极层侧相反的一侧。在半导体装置中,将半导体基板中的作为IGBT元件动作的区域设为IGBT区域,并且将作为二极管元件动作的区域设为二极管区域,交替地重复形成有IGBT区域和二极管区域,IGBT区域和二极管区域由集电极层与阴极层的边界划分。集电极层以及阴极层沿着半导体基板的一面的一个方向延伸设置,并且在与该一个方向正交的方向上交替地重复形成。将上述集电极层设为第1集电极层,在半导体基板中的形成有第1集电极层以及阴极层的一侧的面设置有第2导电型杂质浓度高于第1集电极层的第2集电极层。
这样,设置有第2导电型杂质浓度高于第1集电极层的第2集电极层。由此,能够抑制恢复波形的振动即振动电压,能够抑制浪涌电压。而且,由于仅将集电极的一部分作为第2集电极层,因此还能够抑制开关损耗。
根据本公开的第二方式,半导体装置具备半导体基板,该半导体基板具有:第1导电型的漂移层;第2导电型的基极层,形成于漂移层的表层部;FS层,形成于漂移层中的与基极层侧相反的一侧,第1导电型杂质浓度高于漂移层;以及第2导电型的集电极层及第1导电型的阴极层,隔着FS层形成于与漂移层相反的一侧。在半导体装置中,将半导体基板中的作为IGBT元件动作的区域设为IGBT区域,并且将作为二极管元件动作的区域设为二极管区域,交替地重复形成有IGBT区域和二极管区域,IGBT区域和二极管区域由集电极层与阴极层的边界划分,在FS层中,在对应于集电极层与阴极层之间的位置,设置有与比该位置靠IGBT区域的内侧且靠二极管区域的内侧的位置相比第1导电型杂质浓度更低的低浓度FS层。
这样,在采用具备低浓度FS层的构造的情况下,能够控制PN结的杂质浓度的平衡,成为第2导电型杂质变多的状态。因此,能够抑制浪涌电压,并且抑制开关损耗。
根据本公开的第三方式,半导体装置具备半导体基板,该半导体基板具有:第1导电型的漂移层;第2导电型的基极层,形成于漂移层的表层部;以及第2导电型的集电极层及第1导电型的阴极层,形成于漂移层中的与基极层侧相反的一侧。在半导体装置中,将半导体基板中的作为IGBT元件动作的区域设为IGBT区域,并且将作为二极管元件动作的区域设为二极管区域,交替地重复形成有IGBT区域和二极管区域,IGBT区域和二极管区域由集电极层与阴极层的边界划分,在半导体基板中的形成有集电极层以及阴极层的一侧的面,在集电极层与阴极层之间,形成有比该集电极层以及阴极层深的槽部,并且设置有配置于该槽部内的绝缘层。
这样,在IGBT区域与二极管区域之间具备绝缘层的构造中,恢复电流流经浓度比较低的漂移层内,绝缘层的宽度对应的电位下降量变大。因此,由集电极层以及漂移层构成的PN结中的PN偏置中的载流子注入量增加。因此,能够抑制浪涌电压,并且能够抑制开关损耗。
附图说明
关于本公开的上述目的以及其他目的、特征、优点,一边参照附图一边根据下述的详细记述而变得更清楚。在附图中:
图1是本公开的第1实施方式中的半导体装置的俯视示意图。
图2是沿着图1中的II-II线的剖面图。
图3A是表示恢复动作时的栅极电压Vg、集电极电流Ic、集电极电压Vc、阳极-阴极间电压Vak、恢复电流Ir的波形的图。
图3B是由图3A中的单点划线包围的部分的放大图。
图4A是作为比较例使用于模拟的以往的半导体装置的剖面图。
图4B是将使用于模拟的高浓度集电极层配置于二极管区域内时的半导体装置的剖面图。
图4C是将使用于模拟的高浓度集电极层配置于IGBT区域内时的半导体装置的剖面图。
图5是表示高浓度集电极层的形成位置与振动电压Vak-pp以及二极管正向电压Vf的关系的图。
图6是表示浓度比与振动电压Vak-pp的关系的图。
图7是本公开的第2实施方式的半导体装置的剖面图。
图8是表示恢复动作时的栅极电压Vg、集电极电流Ic、集电极电压Vc、阳极-阴极间电压Vak、恢复电流Ir的波形的图。
图9是本公开的第3实施方式的半导体装置的剖面图。
图10是表示恢复动作时的栅极电压Vg、集电极电流Ic、集电极电压Vc、阳极-阴极间电压Vak、恢复电流Ir的波形的图。
具体实施方式
以下,基于附图说明本公开的实施方式。另外,在以下的各实施方式中,对相互相同或等同的部分赋予相同的标号来进行说明。
(第1实施方式)
对本公开的第1实施方式的半导体装置进行说明。本实施方式的半导体装置由将在基板厚度方向上流经电流的纵向型(Vertical type)的IGBT与FWD配备于一个基板的RC-IGBT构造构成。该半导体装置例如适合被用作在逆变器、DC/DC转换器等电源电路中使用的功率开关元件。具体而言,本实施方式的半导体装置如以下那样构成。
如图1所示,半导体装置具备单元区域1与包围该单元区域1的外周区域2。
单元区域1如图1以及图2所示,设为交替地形成有IGBT区域1a以及二极管区域1b的构成,该IGBT区域1a形成有IGBT元件,该二极管区域1b形成有二极管元件。
具体而言,这些IGBT区域1a以及二极管区域1b均如图2所示,形成于作为漂移层11发挥功能的N-型的半导体基板10,从而成为1个芯片。IGBT区域1a以及二极管区域1b沿半导体基板10的一面10a的一方向(图1中纸面上下方向)延伸设置,沿与延伸设置方向正交的方向交替地形成。
在漂移层11之上、换句话说是半导体基板10的一面10a侧形成有P型的基极层(Base layer)12。而且,以贯通基极层12而到达漂移层11的方式形成有多个沟槽13,利用该沟槽13将基极层12分离为多个。
此外,在本实施方式中,多个沟槽13沿半导体基板10的一面10a的面方向中的一方向(换句话说是图2中纸面深度方向)等间隔地形成。另外,半导体基板10的一面10a由基极层12中的与漂移层11相反的一侧的一面构成。
基极层12在IGBT区域1a中作为沟道区域发挥功能。而且,在作为沟道区域的基极层12即IGBT区域1a的基极层12形成有N+型的发射极区域14、以及被发射极区域14夹着的P+型的主体区域15。
发射极区域14以比漂移层11高的杂质浓度构成,形成为在基极层12内终止并且与沟槽13的侧面相接。另一方面,主体区域15以比基极层12高的杂质浓度构成,与发射极区域14同样地形成为在基极层12内终止。
更详细地说,发射极区域14设为如下构造:在沟槽13间的区域中沿沟槽13的长边方向与沟槽13的侧面相接地呈棒状延伸设置,且在比沟槽13的前端靠内侧终止。另外,主体区域15被两个发射极区域14夹着,并且在沟槽13的长边方向上、换句话说是沿发射极区域14呈棒状延伸设置。此外,本实施方式的主体区域15以半导体基板10的一面10a为基准形成得比发射极区域14深。
另外,各沟槽13内被以覆盖各沟槽13的内壁表面的方式形成的栅极绝缘膜16、以及形成于该栅极绝缘膜16之上的由多晶硅等构成的栅电极17埋入。由此,构成了沟槽栅极构造。
在半导体基板10的一面10a侧,在基极层12之上形成有由BPSG等构成的层间绝缘膜18。而且,在层间绝缘膜18,在IGBT区域1a形成有使发射极区域14的一部分以及主体区域15露出的接触孔18a,在二极管区域1b形成有使基极层12露出的接触孔18b。
在层间绝缘膜18上形成有上部电极19。该上部电极19在IGBT区域1a中经由接触孔18a而与发射极区域14以及主体区域15电连接。另外,上部电极19在二极管区域1b中经由接触孔18b而与基极层12电连接。换句话说,上部电极19在IGBT区域1a中作为发射极电极发挥功能,在二极管区域1b中作为阳极电极发挥功能。
另外,在漂移层11中的与基极层12侧相反的一侧、换句话说是半导体基板10的另一面10b侧形成有N型杂质浓度比漂移层11高的FS层20。该FS层20不是必须的,但为了防止耗尽层的扩散来实现耐压与稳态损耗(Steady loss)的性能提高、并且控制从半导体基板10的另一面10b侧注入的空穴的注入量而设置。例如,FS层20的N型杂质浓度设为1×1015~1×1016cm-3
而且,在IGBT区域1a中,在隔着FS层20而与漂移层11相反的一侧,形成有相当于第1集电极层的P型的集电极层21,在二极管区域1b中,在隔着FS层20而与漂移层11相反的一侧形成有N型的阴极层22。换句话说,IGBT区域1a与二极管区域1b通过形成于半导体基板10的另一面10b侧的层是集电极层21还是阴极层22来划分。例如,集电极层21的P型杂质浓度设为1×1017~1×1018cm-3,集电极层21与阴极层22的排列方向上的宽度设为~1500μm。另外,阴极层22的N型杂质浓度设为1×1019cm-3,集电极层21与阴极层22的排列方向上的宽度设为~500μm。大体来说,集电极层21以及阴极层22的形成周期设为500μm~2mm。
并且,在IGBT区域1a与二极管区域1b之间,形成有杂质浓度高于集电极层21的相当于第2集电极层的高浓度集电极层21a。具体而言,如图1中虚线所示,高浓度集电极层21a在IGBT区域1a与二极管区域1b的边界位置,沿沟槽栅极构造的长边方向形成。在本实施方式中,高浓度集电极层21a的长边方向的两前端位置形成至外周区域2。
高浓度集电极层21a与集电极层21一起构成IGBT中的集电极,但相比于集电极层21杂质浓度更高,由此能够在FWD的恢复动作时注入较多的空穴。例如,高浓度集电极层21a的P型杂质浓度设为集电极层21的2倍以上,优选的是高1个数量级以上,在本实施方式中设为1×1018~1×1019cm-3。另外,高浓度集电极层21a在集电极层21与阴极层22的排列方向上的宽度设为~100μm,并设为阴极层22的相同方向的宽度的10%以上。
此外,在本实施方式中,半导体基板10的另一面10b包括基于集电极层21及高浓度集电极层21a的集电极以及阴极层22。另外,在本实施方式中,集电极层21隔着FS层20形成于与形成有发射极区域14以及主体区域15的基极层12相反的一侧。而且,阴极层22隔着FS层20形成于与未形成有发射极区域14以及主体区域15的基极层12相反的一侧。另外,高浓度集电极层21a配置于集电极层21与阴极层22之间。
换句话说,在本实施方式中,IGBT区域1a与二极管区域1b的边界设为形成有发射极区域14以及主体区域15的基极层12和未形成有发射极区域14以及主体区域15的基极层12的边界。而且,在该边界位置配置有高浓度集电极层21a。
另外,如上述那样,在半导体基板10中,在一面10a侧形成有基极层12,在另一面10b侧形成有集电极层21以及阴极层22。因此,半导体基板10也可以通过依次层叠集电极层21以及阴极层22、FS层20、漂移层11、基极层12而构成。
在集电极层21、高浓度集电极层21a以及阴极层22上(半导体基板10的另一面10b)形成有下部电极23。该下部电极23在IGBT区域1a中作为集电极电极发挥功能,在二极管区域1b中作为阴极电极发挥功能。
而且,通过如上述那样构成,在IGBT区域1a中构成以基极层12为基极、以发射极区域14为发射极、以集电极层21以及高浓度集电极层21a为集电极的IGBT元件。另外,在二极管区域1b中,以基极层12为阳极、以漂移层11、FS层20、阴极层22为阴极而构成PN结的二极管元件。
另外,在半导体基板10的一面10a侧以及另一面10b侧形成有损伤区域(Damageregion)24。具体而言,一面10a侧的损伤区域24形成于二极管区域1b,并且从该二极管区域1b形成至IGBT区域1a。换句话说,损伤区域24形成于二极管区域1b以及IGBT区域1a中的与二极管区域1b的边界侧的部分。另外,另一面10b侧的损伤区域24形成于二极管区域1b与IGBT区域1a的整个区域。
通过具备这样的损伤区域24,使得IGBT区域1a中的漂移层11的空穴(换句话说是过剩载流子)与形成于IGBT区域1a的损伤区域24再次结合而消失。因此,能够抑制从IGBT区域1a向二极管区域1b注入空穴。
这里,对如上述那样构成的高浓度集电极层21a的功能等进行说明。
如以往那样,在无高浓度集电极层21a的构造中,如上所述,FWD的恢复波形振动,浪涌电压容易增加。具体而言,恢复动作时的栅极电压Vg、集电极电流Ic、集电极电压Vc、阳极-阴极间电压Vak、恢复电流Ir成为图3A以及图3B那样的波形。根据这些图可知阳极-阴极间电压Vak振动。在FWD的恢复动作时,若另一面10b侧的载流子枯竭,则寄生电容与外部电路的寄生电感成为主要因素而产生阳极-阴极间电压Vak的振动。
因此,在另一面10b侧除了集电极层21以外还形成高浓度集电极层21a,将集电极层21设为低杂质浓度,从而避免开关损耗,并且在恢复时经过高浓度集电极层21a进行空穴注入。通过这样的构造,能够抑制在FWD的恢复动作时另一面10b侧的载流子枯竭,并抑制阳极-阴极间电压Vak的振动。这样的效果可通过在另一面10b侧局部形成杂质浓度高于集电极层21的高浓度集电极层21a而得到。而且,特别是确认到,通过在IGBT区域1a与二极管区域1b之间、换句话说是集电极层21与阴极层22之间配置高浓度集电极层21a,可进一步获得该效果。
具体而言,改变高浓度集电极层21a的形成位置,得到了由二极管正向电压Vf以及阳极-阴极间电压Vak的极大值与极小值之差表示的振动电压Vak-pp。图5是示出其结果的图。在本图中,高浓度集电极层21a的形成位置以IGBT区域1a与二极管区域1b的边界位置为0,以向IGBT区域1a侧的移动为负,以向二极管区域1b侧的移动为正来表示。另外,作为参考,在图中用虚线箭头示出了图4A所示的构造a、换句话说是不具备高浓度集电极层21a的以往构造中的二极管正向电压Vf与振动电压Vak-pp。
此外,图5中所示的构造b~d示出了错开高浓度集电极层21a的形成位置时相应的状态。构造b是图2所示的本实施方式的构造、换句话说是将高浓度集电极层21a配置于IGBT区域1a与二极管区域1b之间的构造。构造c是如图4B所示将高浓度集电极层21a配置于二极管区域1b的中央位置的构造。构造d是如图4C所示将高浓度集电极层21a配置于IGBT区域1a的中央位置的构造。这里,将高浓度集电极层21a的宽度设定为二极管区域1b的一半的宽度而进行了模拟。另外,关于杂质浓度,将FS层20设定为1×1015~1×1016cm-3,将集电极层21设定为1×1017~1×1018cm-3,将阴极层22设定为1×1019cm-3。关于高浓度集电极层21a,设定为比集电极层21高1个数量级的杂质浓度。
若观察图5中所示的振动电压Vak-pp,与作为以往构造的构造a比较,在构造d的情况下,虽然不太变化,但在构造b、c的情况下大幅度降低。特别是,关于构造b,可以使振动电压Vak-pp降低至40V左右。
另一方面,若观察图5中所示的二极管正向电压Vf,与作为以往构造的构造a比较,在构造d的情况下,虽然不太变化,但在构造b、c的情况下增加。具体而言,二极管正向电压Vf在构造a、d的情况下为2.5V左右,相对于此,在构造b的情况下为2.8V左右,在构造c的情况下为3.1V左右。构造b、c这两方相比于构造a、d,二极管正向电压Vf都增加,但并不是将高浓度集电极层21a形成于宽范围,而仅仅形成在局部,因此二极管正向电压Vf的增加量比较小。特别是,关于构造b,相比于构造c,二极管正向电压Vf的增加量较小。
如以上说明那样,通过具备高浓度集电极层21a,能够不使二极管正向电压Vf增加地抑制恢复波形的振动即振动电压Vak-pp,能够抑制浪涌电压。而且,由于仅将集电极的一部分作为高浓度集电极层21a,因此还能够抑制开关损耗。特别是,通过选择高浓度集电极层21a的形成位置,即配置于IGBT区域1a与二极管区域1b之间,能够进一步抑制浪涌电压。
另外,在本实施方式中,将高浓度集电极层21a的P型杂质浓度设定为集电极层21的2倍以上。由此,能够进一步减小振动电压Vak-pp。关于这一点,在本实施方式的构造中,改变高浓度集电极层21a与集电极层21的杂质浓度之比调查了振动电压Vak-pp。将其结果表示在图6中。
如图6所示,浓度比越高,振动电压Vak-pp越降低,若为2倍以上,则振动电压Vak-pp大致恒定。因此,如本实施方式那样,通过以使浓度比为2倍以上的方式设定高浓度集电极层21a的P型杂质浓度,能够有效地减少振动电压Vak-pp。由此,能够进一步抑制浪涌电压。
此外,关于本实施方式的半导体装置,基本能够通过与以往相同的制造方法制造。但是,关于高浓度集电极层21a,需要通过使用了与形成集电极层21时使用的掩模不同的掩模的离子注入等来形成。
(第2实施方式)
对本公开的第2实施方式进行说明。本实施方式相对于第1实施方式变更了半导体基板10的另一面10b的构造,关于其他与第1实施方式相同,因此仅对与第1实施方式不同的部分进行说明。
如图7所示,在本实施方式中,在IGBT区域1a与二极管区域1b之间具备集电极层21,但不具备第1实施方式那种高浓度集电极层21a。取而代之,采用了在IGBT区域1a与二极管区域1b之间、换句话说是与集电极层21和阴极层22的边界位置对应的位置具备使FS层20的杂质浓度比其他区域低的低浓度FS层20a的构造。例如,相对于FS层20中的低浓度FS层20a以外的部分的N型杂质浓度为1×1015~1×1016cm-3,低浓度FS层20a的N型杂质浓度被设为其一半的0.5×1015~0.5×1016cm-3
这样,在设为具备低浓度FS层20a的构造的情况下,能够控制PN结的杂质浓度的平衡,成为来自P型杂质的空穴注入变多的状态。因此,与第1实施方式同样,能够抑制浪涌电压并且抑制开关损耗。
具体地说,关于本实施方式的构造,调查了恢复动作时中的集电极电流Ic、集电极电压Vc、阳极-阴极间电压Vak、恢复电流Ir的结果,成为图8那样的波形。根据该图,成为浪涌电压的原因的阳极-阴极间电压Vak的振动比图3A所示的以往的构造的情况小。由此也可知获得了上述效果。
(第3实施方式)
对本公开的第3实施方式进行说明。本实施方式也相对于第1实施方式变更了半导体基板10的另一面10b的构造,关于其他与第1实施方式相同,因此仅对与第1实施方式不同的部分进行说明。
如图9所示,在本实施方式中,在IGBT区域1a与二极管区域1b的边界位置,形成比集电极层21以及阴极层22深、优选的是比FS层20深的槽部30,在槽部30内配置有绝缘层31。IGBT区域1a与二极管区域1b的排列方向上的槽部30的宽度、换句话说是绝缘层31的宽度例如设为5μm,槽部30的深度、换句话说是绝缘层31的厚度例如设为2.5μm。
这样,在IGBT区域1a与二极管区域1b之间具备绝缘层31的构造中,恢复电流流经浓度比较低的漂移层11内,绝缘层31的宽度对应的电位下降量(参照图9)变大。因此,由集电极层21和FS层20以及漂移层11构成的PN结中的PN偏置中的空穴注入量增加。因此,与第1实施方式同样,能够抑制浪涌电压,并且能够抑制开关损耗。
具体地说,关于本实施方式的构造,调查了恢复动作时中的集电极电流Ic、集电极电压Vc、阳极-阴极间电压Vak、恢复电流Ir的结果,成为图10那样的波形。根据该图,成为浪涌电压的原因的阳极-阴极间电压Vak的振动比图3A所示的以往的构造的情况小。由此也可知获得了上述效果。
(其他实施方式)
本公开并不限定于上述实施方式,例如,也能够如下述那样适当地变更。
例如,在IGBT区域1b中,采用了在各沟槽栅极构造之间全部形成沟道的构造,但也可以设为例如每隔规定间隔不形成发射极区域14从而不形成沟道的间除构造。另外,也可以在作为间除构造而不形成沟道的部分,在基极层12形成空穴阻挡层(HS:空穴止挡层)。
另外,在上述各实施方式中,列举以第1导电型为n型、以第2导电型为p型的n沟道型的IGBT为例进行了说明,但也能够对使各构成要素的导电型反转而得的p沟道型的IGBT应用本公开。
根据实施方式记述了本公开,但应为理解本公开不限于该实施方式及构造。本公开也包含各种变形例和等效范围内的变形。除此之外,各种组合及形态、还有在它们中仅包含一个要素、一个以上或一个以下要素的其他组合及形态也落入本公开的范围及思想范围内。

Claims (4)

1.一种半导体装置,
具备半导体基板(10),该半导体基板(10)具有:
第1导电型的漂移层(11);
第2导电型的基极层(12),形成在上述漂移层的表层部;以及
第2导电型的集电极层(21)以及第1导电型的阴极层(22),形成在上述漂移层中的与上述基极层侧相反的一侧,
将上述半导体基板中的作为IGBT元件动作的区域设为IGBT区域(1a),并且将作为二极管元件动作的区域设为二极管区域(1b),交替地重复形成有上述IGBT区域和上述二极管区域,
上述IGBT区域和上述二极管区域由上述集电极层与上述阴极层的边界划分,
上述集电极层以及上述阴极层沿着上述半导体基板的一面的一个方向延伸设置,并且在与该一个方向正交的方向上交替地重复形成,
在上述二极管区域、以及上述IGBT区域中的与上述二极管区域的边界侧的部分,形成有损伤区域(24),该损伤区域(24)使在上述漂移层上所产生的过剩载流子与该损伤区域(24)再次结合而消失,
将上述集电极层设为第1集电极层,在上述半导体基板中的形成有上述第1集电极层以及上述阴极层的一侧的面上且在上述半导体基板中的上述第1集电极层与上述阴极层之间设置有第2导电型杂质浓度比上述第1集电极层高的第2集电极层(21a)。
2.如权利要求1所述的半导体装置,其中,
上述第2集电极层的第2导电型杂质浓度被设为上述第1集电极层的2倍以上。
3.一种半导体装置,
具备半导体基板(10),该半导体基板(10)具有:
第1导电型的漂移层(11);
第2导电型的基极层(12),形成在上述漂移层的表层部;
场阻挡层(20),形成在上述漂移层中的与上述基极层侧相反的一侧,第1导电型杂质浓度高于上述漂移层;以及
第2导电型的集电极层(21)以及第1导电型的阴极层(22),隔着上述场阻挡层形成在与上述漂移层相反的一侧,
将上述半导体基板中的作为IGBT元件动作的区域设为IGBT区域(1a),并且将作为二极管元件动作的区域设为二极管区域(1b),交替地重复形成有上述IGBT区域和上述二极管区域,
上述IGBT区域和上述二极管区域由上述集电极层与上述阴极层的边界划分,
在上述二极管区域、以及上述IGBT区域中的与上述二极管区域的边界侧的部分,形成有损伤区域(24),该损伤区域(24)使在上述漂移层上所产生的过剩载流子与该损伤区域(24)再次结合而消失,
在上述场阻挡层中,在对应于上述集电极层与上述阴极层之间的位置,设置有与比该位置靠上述IGBT区域的内侧并且靠上述二极管区域的内侧的位置相比第1导电型杂质浓度更低的低浓度场阻挡层(20a)。
4.一种半导体装置,
具备半导体基板(10),该半导体基板(10)具有:
第1导电型的漂移层(11);
第2导电型的基极层(12),形成在上述漂移层的表层部;以及
第2导电型的集电极层(21)以及第1导电型的阴极层(22),形成在上述漂移层中的与上述基极层侧相反的一侧,
将上述半导体基板中的作为IGBT元件动作的区域设为IGBT区域(1a),并且将作为二极管元件动作的区域设为二极管区域(1b),交替地重复形成有上述IGBT区域和上述二极管区域,
上述IGBT区域和上述二极管区域由上述集电极层与上述阴极层的边界划分,
在上述二极管区域、以及上述IGBT区域中的与上述二极管区域的边界侧的部分,形成有损伤区域(24),该损伤区域(24)使在上述漂移层上所产生的过剩载流子与该损伤区域(24)再次结合而消失,
在上述半导体基板中的形成有上述集电极层以及上述阴极层的一侧的面,在上述集电极层与上述阴极层之间,形成有比该集电极层以及上述阴极层深的槽部(30),并且设置有配置在该槽部内的绝缘层(31)。
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Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6589817B2 (ja) * 2016-10-26 2019-10-16 株式会社デンソー 半導体装置
JP7139309B2 (ja) 2017-03-10 2022-09-20 株式会社小糸製作所 照明装置
JP7013668B2 (ja) * 2017-04-06 2022-02-01 富士電機株式会社 半導体装置
WO2019013286A1 (ja) * 2017-07-14 2019-01-17 富士電機株式会社 半導体装置
US10141300B1 (en) 2017-10-19 2018-11-27 Alpha And Omega Semiconductor (Cayman) Ltd. Low capacitance transient voltage suppressor
DE112018001627T5 (de) 2017-11-15 2020-01-16 Fuji Electric Co., Ltd. Halbleitervorrichtung
CN110574146B (zh) 2017-11-16 2024-02-13 富士电机株式会社 半导体装置
JP6992476B2 (ja) * 2017-12-14 2022-01-13 富士電機株式会社 半導体装置
US11393812B2 (en) * 2017-12-28 2022-07-19 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
JP7102808B2 (ja) 2018-03-15 2022-07-20 富士電機株式会社 半導体装置
JP7187787B2 (ja) 2018-03-15 2022-12-13 富士電機株式会社 半導体装置
JP7131003B2 (ja) 2018-03-16 2022-09-06 富士電機株式会社 半導体装置
JP7010184B2 (ja) * 2018-09-13 2022-01-26 株式会社デンソー 半導体装置
JP7230434B2 (ja) 2018-10-30 2023-03-01 富士電機株式会社 半導体装置の製造方法
DE112019003399T5 (de) 2019-02-27 2021-03-18 Fuji Electric Co., Ltd. Halbleitervorrichtung
JP7404702B2 (ja) * 2019-08-09 2023-12-26 富士電機株式会社 半導体装置
CN110797404B (zh) * 2019-10-18 2023-11-28 上海睿驱微电子科技有限公司 一种rc-igbt半导体器件
CN113990927B (zh) * 2021-10-26 2023-11-28 电子科技大学 一种减小米勒电容的新型rc-igbt结构

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101000911A (zh) * 2006-01-10 2007-07-18 株式会社电装 具有igbt和二极管的半导体器件
CN101764139A (zh) * 2008-12-24 2010-06-30 株式会社电装 包括绝缘栅极双极晶体管和二极管的半导体器件
CN102412288A (zh) * 2010-09-21 2012-04-11 株式会社东芝 逆导型绝缘栅双极晶体管

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2050694B (en) 1979-05-07 1983-09-28 Nippon Telegraph & Telephone Electrode structure for a semiconductor device
US4969028A (en) 1980-12-02 1990-11-06 General Electric Company Gate enhanced rectifier
JPH0266977A (ja) 1988-09-01 1990-03-07 Fuji Electric Co Ltd 半導体ダイオード
US6204717B1 (en) 1995-05-22 2001-03-20 Hitachi, Ltd. Semiconductor circuit and semiconductor device for use in equipment such as a power converting apparatus
JP2001196606A (ja) 2000-01-11 2001-07-19 Mitsubishi Electric Corp ダイオード
JP2007184486A (ja) * 2006-01-10 2007-07-19 Denso Corp 半導体装置
JP2008192737A (ja) * 2007-02-02 2008-08-21 Denso Corp 半導体装置
JP4957840B2 (ja) 2010-02-05 2012-06-20 株式会社デンソー 絶縁ゲート型半導体装置
JP5190485B2 (ja) * 2010-04-02 2013-04-24 株式会社豊田中央研究所 半導体装置
CN102822968B (zh) * 2010-04-02 2016-08-03 丰田自动车株式会社 具备具有二极管区和绝缘栅双极性晶体管区的半导体基板的半导体装置
US8564097B2 (en) * 2010-04-15 2013-10-22 Sinopower Semiconductor, Inc. Reverse conducting IGBT
JP5321669B2 (ja) 2010-11-25 2013-10-23 株式会社デンソー 半導体装置
JP5737102B2 (ja) * 2011-09-19 2015-06-17 株式会社デンソー 半導体装置
JP2014103376A (ja) * 2012-09-24 2014-06-05 Toshiba Corp 半導体装置
US9960165B2 (en) 2013-11-05 2018-05-01 Toyota Jidosha Kabushiki Kaisha Semiconductor device having adjacent IGBT and diode regions with a shifted boundary plane between a collector region and a cathode region
JP6119593B2 (ja) * 2013-12-17 2017-04-26 トヨタ自動車株式会社 半導体装置
JP2015154000A (ja) * 2014-02-18 2015-08-24 トヨタ自動車株式会社 半導体装置および半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101000911A (zh) * 2006-01-10 2007-07-18 株式会社电装 具有igbt和二极管的半导体器件
CN101764139A (zh) * 2008-12-24 2010-06-30 株式会社电装 包括绝缘栅极双极晶体管和二极管的半导体器件
CN102412288A (zh) * 2010-09-21 2012-04-11 株式会社东芝 逆导型绝缘栅双极晶体管

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