JP2017045949A - 半導体装置 - Google Patents
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Abstract
【解決手段】コレクタ層21よりも高不純物濃度とされた高濃度コレクタ層21aを備える。これにより、リカバリ波形の振動、つまり振動電圧Vak−ppを抑制することが可能となり、サージ電圧を抑制することが可能となる。そして、コレクタの一部のみしか高濃度コレクタ層21aにしていないことから、スイッチング損失についても抑制できる。特に、高濃度コレクタ層21aの形成位置を選択すること、すなわちIGBT領域1aとダイオード領域1bの間に配置することで、サージ電圧を更に抑制することが可能となる。
【選択図】図2
Description
本発明の第1実施形態にかかる半導体装置について説明する。本実施形態にかかる半導体装置は、基板厚み方向に電流を流す縦型のIGBTとFWDとが1つの基板に備えられたRC−IGBT構造により構成されている。この半導体装置は、例えば、インバータ、DC/DCコンバータ等の電源回路に使用されるパワースイッチング素子として利用されると好適である。具体的には、本実施形態にかかる半導体装置は、以下のように構成されている。
本発明の第2実施形態について説明する。本実施形態は、第1実施形態に対して半導体基板10の他面10bの構造を変更したものであり、その他については第1実施形態と同様であるため、第1実施形態と異なる部分についてのみ説明する。
本発明の第3実施形態について説明する。本実施形態も、第1実施形態に対して半導体基板10の他面10bの構造を変更したものであり、その他については第1実施形態と同様であるため、第1実施形態と異なる部分についてのみ説明する。
本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。
1b ダイオード領域
10 半導体基板
11 ドリフト層
12 ベース層
20 FS層
20a 低濃度FS層
21 コレクタ層
21a 高濃度コレクタ層
22 カソード層
Claims (5)
- 第1導電型のドリフト層(11)と、
前記ドリフト層の表層部に形成された第2導電型のベース層(12)と、
前記ドリフト層のうちの前記ベース層側と反対側に形成された第2導電型のコレクタ層(21)および第1導電型のカソード層(22)と、を有する半導体基板(10)を備え、
前記半導体基板のうちのIGBT素子として動作する領域をIGBT領域(1a)とすると共にダイオード素子として動作する領域をダイオード領域(1b)として、前記IGBT領域と前記ダイオード領域とが交互に繰り返し形成されており、
前記IGBT領域と前記ダイオード領域とは、前記コレクタ層と前記カソード層との境界によって区画され、
前記コレクタ層を第1コレクタ層として、前記半導体基板のうちの前記第1コレクタ層および前記カソード層が形成された側の面に、前記第1コレクタ層よりも第2導電型不純物濃度が高くされた第2コレクタ層が備えられている半導体装置。 - 前記第2コレクタ層が前記半導体基板のうちの前記第1コレクタ層と前記カソード層との間に備えられている請求項1に記載の半導体装置。
- 前記第2コレクタ層の第2導電型不純物濃度が前記第1コレクタ層の2倍以上とされている請求項1または2に記載の半導体装置。
- 第1導電型のドリフト層(11)と、
前記ドリフト層の表層部に形成された第2導電型のベース層(12)と、
前記ドリフト層のうちの前記ベース層側と反対側に形成され、前記ドリフト層よりも第1導電型不純物濃度が高くされたフィールドストップ層(20)と、前記フィールドストップ層を挟んで前記ドリフト層と反対側に形成された第2導電型のコレクタ層(21)および第1導電型のカソード層(22)とを有する半導体基板(10)を備え、
前記半導体基板のうちのIGBT素子として動作する領域をIGBT領域(1a)とすると共にダイオード素子として動作する領域をダイオード領域(1b)として、前記IGBT領域と前記ダイオード領域とが交互に繰り返し形成されており、
前記IGBT領域と前記ダイオード領域とは、前記コレクタ層と前記カソード層との境界によって区画され、
前記フィールドストップ層に、前記コレクタ層と前記カソード層との間と対応する位置において、当該位置よりも前記IGBT領域の内側および前記ダイオード領域の内側の位置と比較して第1導電型不純物濃度が低くされた低濃度フィールドストップ層(20a)が備えられている半導体装置。 - 第1導電型のドリフト層(11)と、
前記ドリフト層の表層部に形成された第2導電型のベース層(12)と、
前記ドリフト層のうちの前記ベース層側と反対側に形成された第2導電型のコレクタ層(21)および第1導電型のカソード層(22)と、を有する半導体基板(10)を備え、
前記半導体基板のうちのIGBT素子として動作する領域をIGBT領域(1a)とすると共にダイオード素子として動作する領域をダイオード領域(1b)として、前記IGBT領域と前記ダイオード領域とが交互に繰り返し形成されており、
前記IGBT領域と前記ダイオード領域とは、前記コレクタ層と前記カソード層との境界によって区画され、
前記半導体基板のうち前記コレクタ層および前記カソード層が形成された側の面に、前記コレクタ層と前記カソード層との間において、該コレクタ層および前記カソード層よりも深い溝部(30)が形成されていると共に、該溝部内に配置された絶縁層(31)が備えられている半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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JP2015169396A JP6443267B2 (ja) | 2015-08-28 | 2015-08-28 | 半導体装置 |
US15/740,573 US10170607B2 (en) | 2015-08-28 | 2016-08-08 | Semiconductor device |
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US20180197977A1 (en) | 2018-07-12 |
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WO2017038389A1 (ja) | 2017-03-09 |
US10170607B2 (en) | 2019-01-01 |
CN107924942A (zh) | 2018-04-17 |
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