JP6798377B2 - 半導体集積回路装置 - Google Patents
半導体集積回路装置 Download PDFInfo
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- JP6798377B2 JP6798377B2 JP2017053178A JP2017053178A JP6798377B2 JP 6798377 B2 JP6798377 B2 JP 6798377B2 JP 2017053178 A JP2017053178 A JP 2017053178A JP 2017053178 A JP2017053178 A JP 2017053178A JP 6798377 B2 JP6798377 B2 JP 6798377B2
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- 239000000758 substrate Substances 0.000 claims description 83
- 239000002344 surface layer Substances 0.000 claims description 18
- 239000012535 impurity Substances 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 description 223
- 230000016507 interphase Effects 0.000 description 62
- 238000000926 separation method Methods 0.000 description 61
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- 230000007257 malfunction Effects 0.000 description 21
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- 238000002347 injection Methods 0.000 description 14
- 239000007924 injection Substances 0.000 description 14
- 230000002093 peripheral effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 238000005036 potential barrier Methods 0.000 description 5
- 230000002265 prevention Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 108091006149 Electron carriers Proteins 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910052770 Uranium Inorganic materials 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- 230000008054 signal transmission Effects 0.000 description 1
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
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Description
実施の形態1にかかる半導体集積回路装置の構造について、実施の形態1にかかる半導体集積回路装置を、3相インバータを駆動するゲートドライバICとして用いる場合を例に説明する。まず、一般的な3相インバータの回路構成について説明する。図1は、一般的な3相インバータの回路構成を示す回路図である。図1に示すように、3相インバータ10は、3相(U相、V相、W相)のハーフブリッジ回路1〜3で構成されている。ハーフブリッジ回路1〜3の各出力点(中点)4には、モータなどの負荷5が接続されている。
次に、実施の形態2にかかる半導体集積回路装置の構造について説明する。図8〜11は、実施の形態2にかかる半導体集積回路装置の構造を示す断面図である。図8には、図3の切断線A−A’における断面構造を示す。図9には、図3の切断線B−B’における断面構造を示す。図10には、図3の切断線C−C’における断面構造を示す。図11には、図3の切断線D−D’における断面構造を示す。また、図8〜11には、図3の3相の各n型ウェル領域33のうち、W相におけるn型ウェル領域33を切断する断面構造を示すが、U相およびV相ともにW相と同様の断面構造を有する。
次に、実施の形態3にかかる半導体集積回路装置の構造について説明する。図12は、実施の形態3にかかる半導体集積回路装置の平面レイアウトを示す平面図である。実施の形態3にかかる半導体集積回路装置は、n型ウェル領域33内におけるHVNMOS14a,14bの平面レイアウトが実施の形態1にかかる半導体集積回路装置と異なる。具体的には、HVNMOS14a,14bは、n型ウェル領域33の、p型分離領域35よりも外側において、実施の形態1よりも第1VBピックアップ領域36から離れた位置に配置されている。
次に、実施の形態4にかかる半導体集積回路装置の構造について説明する。図13〜17は、実施の形態4にかかる半導体集積回路装置の平面レイアウトを示す平面図である。実施の形態4にかかる半導体集積回路装置は、ハイサイド回路領域21の配置(すなわちn型ウェル領域33の配置)、または、ハイサイド回路領域21およびローサイド回路領域22の配置が実施の形態1にかかる半導体集積回路装置と異なる。
次に、実施の形態5において、ローサイド回路領域22に配置されるHVIC20の入力信号処理回路11aの回路構成について説明する。図18は、HVICの入力信号処理回路の回路構成を示す回路図である。図18に示すHVIC20の入力信号処理回路11aの回路構成は、実施の形態1〜4の各HVIC20(図3,12〜17)に適用される。HVIC20の入力信号処理回路11aは、基準電圧回路101、低電圧誤動作防止回路102、3相分のコンパレータ(比較器)103a〜103c、第1〜5端子105〜109およびPG回路110を備える。PG回路110は、リセット(RESET)回路111、ローパスフィルタ112およびパルス発生回路113を備える。
次に、ノイズが印加されたときにハイサイド回路領域21のHVNMOS14a,14bに注入される電流量をシミュレーションにより検証した。図20Aは、実施例および比較例のシミュレーションに用いた構成を示す斜視図である。図20Bは、図20Aの実施例および比較例の第1VBピックアップ領域に印加したノイズの波形を示す波形図である。図20Cは、図20Aの実施例および比較例への注入電流比率を示す図表である。
4 ハーフブリッジ回路の出力点
5 負荷
6 ハーフブリッジ回路の上アームのIGBT
7 ハーフブリッジ回路の下アームのIGBT
8 3相インバータの高電位側ライン
9 3相インバータの低電位側ライン
10 3相インバータ
11a HVICの入力信号処理回路
11b LVICの入力信号処理回路
12 ハイサイド駆動回路
13 ローサイド駆動回路
14 レベルシフト回路
14a, 14b HVNMOS
15 ロジック回路、ローパスフィルタおよびRSラッチ等の回路部
16 ドライバ回路
17 ブートストラップダイオード
18 ブートストラップコンデンサ
20 HVIC
21 ハイサイド回路領域
22 ローサイド回路領域
23 HVJT
24,26 ハイサイド回路領域を構成するn型ウェル領域間の相間領域
25 ハイサイド回路領域を構成するn型ウェル領域とローサイド回路領域を構成するn型拡散領域との間の相間領域
30 半導体基板(半導体チップ)
30a 基板裏面側のp型領域
31 n型拡散領域
32 n-型拡散領域
33 n型ウェル領域
33a〜33d 基板おもて面から見たn型ウェル領域の辺
33e〜33h 基板おもて面から見たn型ウェル領域の頂点
34 p型拡散領域
35,35',91 p型分離領域
36,92 第1VBピックアップ領域
37, 37a,37b n型拡散領域
38 p型拡散領域
39 第2VBピックアップ領域
40 VBピックアップ電極
41 COM領域
42 COMコンタクト領域
43 COMコンタクト電極
44 VBピックアップ電極
50a,70a 横型NMOS
50b,70b 横型PMOS
51,62,71 n+型ソース領域
52,63,72 p+型コンタクト領域
53,64,73 n+型ドレイン領域
54,59,66,74,79 ゲート電極
55a,55b,67,75a,75b ソース電極
55c,68,75c ドレイン電極
56,76 p+型ソース領域
57,77 n+型コンタクト領域
58,78 p+型ドレイン領域
61 p型ベース領域
65 ゲートポリシリコン層
81 p-型支持基板
82 n型またはp型のエピタキシャル層
83 n+型埋め込み層
101 基準電圧回路
102 低電圧誤動作防止回路
103a〜103c コンパレータ
104a〜104c ツェナーダイオード
105〜109 入力信号処理回路の端子
110 PG回路
111 リセット回路
112 ローパスフィルタ
113 パルス発生回路
114a セット信号
114b リセット信号
115 HVICの入力信号処理回路の高電位側ライン
116 HVICの入力信号処理回路の低電位側ライン
120 LVIC
COM 共通電位
GND 接地電位
IN1,IN2 入力端子
IN_U,IN_V,IN_W 入力信号
VB ハイサイド駆動回路の最高電位
VS ハイサイド回路領域の基準電位(上アームのIGBTのエミッタ電位)
Vcc 3相インバータの電源電位
Vdd1 ハイサイド駆動回路の入力信号処理回路の電源電位(PG回路の電源電位)
Vdd2 LVICの電源電位
Claims (7)
- 半導体基板のおもて面の表面層に、互いに離して選択的に2つ以上設けられた第1導電型の第1半導体領域と、
前記第1半導体領域の内部に選択的に設けられ、前記半導体基板のおもて面から前記第1半導体領域を深さ方向に貫通する第2導電型の第2半導体領域と、
前記第1半導体領域の内部に、前記第2半導体領域と離して選択的に設けられ、前記第2半導体領域よりも高電位に固定された第1導電型の第3半導体領域と、
前記第3半導体領域よりも前記第1半導体領域の中央部側に配置された高電位側回路と、
を備え、
隣り合う前記第1半導体領域の、一方の前記第1半導体領域の前記高電位側回路と他方の前記第1半導体領域の前記高電位側回路との間であって、一方の前記第1半導体領域に配置された前記第3半導体領域は、他方の前記第1半導体領域に配置された前記第3半導体領域を挟んでかつ該第3半導体領域との間に前記第2半導体領域を介さずに、他方の前記第1半導体領域の前記高電位側回路と対向することを特徴とする半導体集積回路装置。 - 隣り合う前記第1半導体領域の、一方の前記第1半導体領域の前記高電位側回路と他方の前記第1半導体領域の前記高電位側回路との間であって、一方の前記第1半導体領域に配置された前記第2半導体領域は、他方の前記第1半導体領域に配置された前記第2半導体領域を挟んでかつ該第2半導体領域との間に前記第3半導体領域を介さずに、他方の前記第1半導体領域の前記高電位側回路と対向することを特徴とする請求項1に記載の半導体集積回路装置。
- 前記第1半導体領域は、矩形状の平面形状をなし、
少なくとも1組の隣り合う前記第1半導体領域の対向する辺の全体に沿って、前記第2半導体領域が配置されず前記第3半導体領域が配置されたことを特徴とする請求項1に記載の半導体集積回路装置。 - 他の隣り合う前記第1半導体領域の、対向する辺の全体に沿って前記第2半導体領域が配置され、対向する該第2半導体領域間に前記第3半導体領域が介在しないことを特徴とする請求項3に記載の半導体集積回路装置。
- 前記半導体基板のおもて面の表面層に選択的に設けられた第1導電型の第4半導体領域と、
前記第4半導体領域に配置された、前記高電位側回路よりも低い基準電圧で動作する低電位側回路と、
をさらに備え、
前記第4半導体領域は、前記第1半導体領域の、前記第3半導体領域が配置された部分以外の部分で前記第1半導体領域の外周に対向することを特徴とする請求項1〜4のいずれか一つに記載の半導体集積回路装置。 - 前記半導体基板のおもて面の表面層に選択的に設けられた第1導電型の第4半導体領域と、
前記第4半導体領域に配置された、前記高電位側回路よりも低い基準電圧で動作する低電位側回路と、
をさらに備え、
前記第4半導体領域は、前記第3半導体領域が配置された部分以外の部分で外周同士が対向する隣り合う前記第1半導体領域の間に配置されていることを特徴とする請求項2に記載の半導体集積回路装置。 - 前記第1半導体領域は、前記高電位側回路が形成される第1の第1半導体領域と、前記第1の第1半導体領域に接し、前記第1の第1半導体領域の周囲を囲む前記第1の第1半導体領域よりも不純物濃度の低い第2の第1半導体領域と、からなることを特徴とする請求項1〜6のいずれか一つに記載の半導体集積回路装置。
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