JP7143734B2 - 半導体集積回路 - Google Patents
半導体集積回路 Download PDFInfo
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- JP7143734B2 JP7143734B2 JP2018214854A JP2018214854A JP7143734B2 JP 7143734 B2 JP7143734 B2 JP 7143734B2 JP 2018214854 A JP2018214854 A JP 2018214854A JP 2018214854 A JP2018214854 A JP 2018214854A JP 7143734 B2 JP7143734 B2 JP 7143734B2
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
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- 229910052751 metal Inorganic materials 0.000 description 3
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- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
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Description
本発明の実施形態に係る半導体集積回路50は、図1に示すように、駆動対象として、例えば電力変換用ブリッジ回路の一相分である電力変換部60を駆動するHVICである。電力変換部60は、高圧側スイッチング素子S1と、低圧側スイッチング素子S2とを直列に接続して出力回路を構成している。
ここで、第1比較例に係る半導体集積回路を説明する。第1比較例に係る半導体集積回路は、図5に示すように、ハイサイド回路領域101のpウェル領域5及びpMOSトランジスタ92の下方にn+型の埋め込み層が無い点が、図4に示した本発明の実施形態に係る半導体集積回路50と異なる。
次に、第2比較例に係る半導体集積回路を説明する。第2比較例に係る半導体集積回路は、図5に示した第1比較例に係る半導体集積回路の寄生pnpバイポーラトランジスタ201の動作を抑制するために、図6及び図7に示すように、ハイサイド回路領域101においてn+型の埋め込み層70が一様に埋め込まれている点が、第1比較例に係る半導体集積回路と異なる。
次に、図8~図11等を参照しながら、本発明の実施形態に係る半導体集積回路の製造方法の一例を説明する。まず、p-型のSiからなる半導体基板1を用意する。半導体基板1上にフォトレジスト膜1aを塗布し、フォトリソグラフィ技術を用いて、図8に示すように、フォトレジスト膜1aをパターニングする。パターニングされたフォトレジスト膜1aをイオン注入用マスクとして用いて、Sb、P又はAs等のn型不純物をイオン注入で局所的に添加する。その後、フォトレジスト膜1aを除去する。
本発明の実施形態の第1変形例に係る半導体集積回路は、図12に示すように、ハイサイド回路領域101のpウェル領域5が浅く設けられている点が、図4に示した本発明の実施形態に係る半導体集積回路50の構成と異なる。pウェル領域5は、pウェル領域5の下方のn+型の埋め込み層71と離間して設けられている。本発明の実施形態の第1変形例に係る半導体集積回路の他の構成は、図4に示した本発明の実施形態に係る半導体集積回路50の構成と同様であるので、重複した説明を省略する。
本発明の実施形態の第2変形例に係る半導体集積回路は、図13に示すように、ハイサイド回路領域101のn+型の埋め込み層71の幅W11及びn+型の埋め込み層72の幅W12が狭い点が、図4に示した本発明の実施形態に係る半導体集積回路50の構成と異なる。埋め込み層71の幅W11は、pウェル領域5の幅W21と等しい。また、埋め込み層72の幅W12は、pMOSトランジスタ92の幅W22と等しい。本発明の実施形態の第2変形例に係る半導体集積回路の他の構成は、図4に示した本発明の実施形態に係る半導体集積回路50の構成と同様であるので、重複した説明を省略する。
本発明の実施形態の第3変形例に係る半導体集積回路は、図14に示すように、ハイサイド回路領域101のnウェル領域4と、p型の分離領域3との間に、n-型の耐圧領域4xが設けられている点が、図4に示した本発明の実施形態に係る半導体集積回路50の構成と異なる。耐圧領域4xは、nウェル領域4の周囲を取り囲むように環状の平面パターンを有する。耐圧領域4xは、nウェル領域4よりも浅く設けられている。耐圧領域4xの不純物濃度は、nウェル領域4の不純物濃度よりも低い。本発明の実施形態の第3変形例に係る半導体集積回路の他の構成は、図4に示した本発明の実施形態に係る半導体集積回路50の構成と同様であるので、重複した説明を省略する。
本発明の実施形態の第4変形例に係る半導体集積回路は、図15に示すように、ハイサイド回路領域101のnウェル領域4が、n型のエピタキシャル層の一部で構成されている点が、図4に示した本発明の実施形態に係る半導体集積回路50の構成と異なる。
本発明の実施形態の第5変形例に係る半導体集積回路は、図16に示すように、3相インバータを構成するU相、V相、W相のハイサイド回路部100a,100,100bを備える点が、図4に示した本発明の実施形態に係る半導体集積回路50の構成と異なる。
上記のように、本発明は実施形態によって記載したが、この開示の一部をなす論述及び図面は本発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施形態、実施例及び運用技術が明らかとなろう。
1a…フォトレジスト膜
2…エピタキシャル層
3…分離領域
4,4a,4b,8…ウェル領域(nウェル領域)
4x…耐圧領域
5,18,19…ウェル領域(pウェル領域)
6,7,9,17…コンタクト領域
10…半導体基体
11,13,15…ソース領域
12,14,16…ドレイン領域
21,22,23…ゲート電極
31,32,33,34,35,36,37…受動素子
41…ローサイド回路
42…レベルシフト回路
43…ハイサイド回路
45…pMOSトランジスタ
46…nMOSトランジスタ
50…半導体集積回路
60…電力変換部
61…接続点
65…ブートストラップダイオード
66…ブートストラップコンデンサ
67…負荷
70,71,72,73,74,75…埋め込み層
81,82,83…パッド
91…nMOSトランジスタ
92,93…pMOSトランジスタ
100,100a,100b…ハイサイド回路部
101,101a,101b…ハイサイド回路領域
102…HVJT
103…ローサイド回路領域
201,202…寄生pnpバイポーラトランジスタ
203,204,205…寄生npnバイポーラトランジスタ
Claims (9)
- 第1導電型の半導体基体と、
前記半導体基体の上部に設けられ、第1電位が印加される第2導電型の第1ウェル領域と、
前記第1ウェル領域の上部に設けられ、前記第1電位よりも低い第2電位が印加される第1導電型の第2ウェル領域と、
前記第1ウェル領域の上部に前記第2ウェル領域と離間して設けられ、前記第2電位が印加される主電極領域と、
前記第2ウェル領域の下に局所的に埋め込まれた第2導電型の第1埋め込み層と、
前記第1埋め込み層と離間して、前記主電極領域の下に局所的に埋め込まれた第2導電型の第2埋め込み層と、
を備えることを特徴とする半導体集積回路。 - 前記第2ウェル領域と、前記第1埋め込み層とが接することを特徴とする請求項1に記載の半導体集積回路。
- 前記第2ウェル領域と、前記第1埋め込み層とが離間することを特徴とする請求項1に記載の半導体集積回路。
- 前記第1埋め込み層の幅が、前記第2ウェル領域の幅以上であることを特徴とする請求項1~3のいずれか1項に記載の半導体集積回路。
- 前記半導体基体が、第1導電型の半導体基板と、前記半導体基板上に設けられた第1導電型のエピタキシャル層とで構成され、
前記第1ウェル領域が、前記エピタキシャル層に設けられた拡散層で構成されている
ことを特徴とする請求項1~4のいずれか1項に記載の半導体集積回路。 - 前記半導体基体が、第1導電型の半導体基板と、前記半導体基板上に設けられた第2導電型のエピタキシャル層とで構成され、
前記第1ウェル領域が、前記エピタキシャル層で構成されている
ことを特徴とする請求項1~4のいずれか1項に記載の半導体集積回路。 - 前記主電極領域が、前記第2ウェル領域よりも浅く設けられていることを特徴とする請求項1~6のいずれか1項に記載の半導体集積回路。
- 前記半導体基体の上部に前記第1ウェル領域に接して設けられ、前記第1及び第2電位よりも低い第3電位が印加される第1導電型の分離領域と、
前記半導体基体の上部に前記分離領域に接して設けられ、前記第1~第3電位とは異なる第4電位が印加される第2導電型の第3ウェル領域と、
を更に備えることを特徴とする請求項1~7のいずれか1項に記載の半導体集積回路。 - 前記半導体基体の上部に前記第1ウェル領域に接して設けられ、前記第1及び第2電位よりも低い第3電位が印加される第1導電型の分離領域と、
前記半導体基体の上部に前記分離領域に接して設けられ、前記第1電位が印加される第2導電型の第4ウェル領域と、
を更に備えることを特徴とする請求項1~7のいずれか1項に記載の半導体集積回路。
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KR102246570B1 (ko) * | 2014-09-05 | 2021-04-29 | 온세미컨덕터코리아 주식회사 | 전력 반도체 장치 |
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