JP6120586B2 - nチャネル二重拡散MOS型トランジスタおよび半導体複合素子 - Google Patents
nチャネル二重拡散MOS型トランジスタおよび半導体複合素子 Download PDFInfo
- Publication number
- JP6120586B2 JP6120586B2 JP2013012276A JP2013012276A JP6120586B2 JP 6120586 B2 JP6120586 B2 JP 6120586B2 JP 2013012276 A JP2013012276 A JP 2013012276A JP 2013012276 A JP2013012276 A JP 2013012276A JP 6120586 B2 JP6120586 B2 JP 6120586B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- layer
- channel
- region
- mos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 80
- 238000009792 diffusion process Methods 0.000 title claims description 31
- 239000002131 composite material Substances 0.000 title claims description 27
- 239000010410 layer Substances 0.000 claims description 471
- 239000002344 surface layer Substances 0.000 claims description 70
- 239000000758 substrate Substances 0.000 claims description 52
- 239000012535 impurity Substances 0.000 claims description 44
- 239000012212 insulator Substances 0.000 claims description 19
- 230000015556 catabolic process Effects 0.000 description 62
- 150000002500 ions Chemical class 0.000 description 32
- 238000002955 isolation Methods 0.000 description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 20
- 229920005591 polysilicon Polymers 0.000 description 20
- 230000001133 acceleration Effects 0.000 description 18
- -1 arsenic ions Chemical class 0.000 description 16
- 230000015572 biosynthetic process Effects 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 8
- 229910052698 phosphorus Inorganic materials 0.000 description 7
- 239000011574 phosphorus Substances 0.000 description 7
- 229910052785 arsenic Inorganic materials 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
- H01L29/0865—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
一方、p型ボディ層内に形成されるn型ソース層の電位は、n型埋め込み層の電位から独立に決定することができる。たとえば、n型埋め込み層をグランド電位とする一方で、n型ソース層およびn型ドレイン層を高電位とすることができる。したがって、この発明のnチャネル二重拡散MOS型トランジスタは、たとえば、インバータ回路やDC−DCコンバータにおいて用いられるブリッジ回路(フルブリッジ回路またはハーフブリッジ回路)を構成するハイサイドトランジスタおよびローサイドトランジスタのいずれとしても用いることができる。すなわち、ハイサイドトランジスタおよびローサイドトランジスタに共通の素子構造を適用できる。したがって、ブリッジ回路のための素子構造を簡単にすることができる。
請求項4記載の発明は、前記p型埋め込み層が、前記p型ボディ層の直下の領域を回避して形成されている、請求項1〜3のいずれか一項に記載のnチャネル二重拡散MOS型トランジスタである。これにより、p型埋め込み層を小さくできるので、n型ドリフト層とp型埋め込み層との間の容量を小さくして、スイッチング特性を一層向上できる。
請求項6記載の発明は、前記n型ドレイン層と前記チャネル領域との間に介在するように前記n型ドリフト層内に形成され、前記n型ドリフト層内の電流経路を延長する絶縁物埋め込み構造をさらに含む、請求項1〜5のいずれか一項に記載のnチャネル二重拡散MOS型トランジスタである。この構成により、ドリフト層内の絶縁物埋め込み構造によって、チャネル領域からn型ドレイン層に至る電流経路が長くなっている。それによって、ドレイン・エクステンデッド構造が形成されており、nチャネル二重拡散MOS型トランジスタを高耐圧素子とすることができる。
図1は、この発明の一実施形態に係る半導体複合素子の構成を説明するための断面図である。この半導体複合素子1は、BiCDMOS素子であり、共通の半導体基板2(たとえばシリコン基板)上に、CMOSエリア3と、DMOSエリア4と、バイポーラエリア5と、受動素子エリア6とを備えている。CMOSエリア3には、CMOS型トランジスタ30が形成されており、DMOSエリア4にはDMOS型トランジスタ40が形成されており、バイポーラエリア5にはバイポーラ素子50が形成されている。受動素子エリア6には、抵抗素子、キャパシタ等の受動素子60が形成されている。
具体的には、n型ウェル331内にp型ドリフト層335(PDRIFT)が形成されている。このp型ドリフト層335の表層部には、一対の浅いn型ウェル336(NW)が間隔を開けて形成されている。それらの一対の浅いn型ウェル336内には、一対のn型LDD層337(MVNLDD)がそれぞれ形成されている。そして、それらの一対のn型LDD層337内には、それぞれ、n+型ソース層338およびn+型ドレイン層339が形成されている。一対の浅いn型ウェル336の間の領域は、チャネル領域360である。このチャネル領域360には、ゲート絶縁膜361を挟んでゲート電極362が対向している。こうして、高耐圧nチャネルMOS型トランジスタ33nが構成されている。p型ドリフト層335とn型埋め込み層333との間には、p型埋め込み層363(LI)が介在されており、このp型埋め込み層363の上下面は、p型ドリフト層335およびn型埋め込み層333にそれぞれ接している。
図3A、図3Bおよび図3Cは、DMOSエリア4の構成例を説明するための断面図であり、各図の下段に示すように合体してDMOSエリア4を示す断面図を構成する。DMOSエリア4には、DMOS型トランジスタ40として、たとえば、7V程度の耐圧の低耐圧nチャネルDMOS型トランジスタ41、10V程度の耐圧の中耐圧nチャネルDMOS型トランジスタ42、15V〜28V程度の高耐圧nチャネルDMOS型トランジスタ43、10V〜28V程度の高耐圧pチャネルDMOS型トランジスタ44などが形成されている。高耐圧nチャネルDMOS型トランジスタ43は、この発明の一実施形態に係るnチャネル二重拡散MOS型トランジスタである。個々のDMOS型トランジスタ41〜44は、素子分離部7によって、他の素子から電気的に分離されている。DMOSエリア4内の素子分離部7は、この実施形態では、溝71内に絶縁物72(たとえば酸化シリコン)を埋め込んだSTI構造で構成されている。素子分離部7は、その底部にp型ドリフト層73(PDRIFT)およびp型ウェル74(PW)を伴っている。これにより、より確実な素子分離が図られている。また、DMOSエリア4内の素子分離部7の直下には、p型埋め込み層75(LI)が形成されている。このp型埋め込み層75は、p型半導体基板2とp型エピタキシャル層8との境界部に配置されている。
n型ドリフト層435とn型埋め込み層433との間には、p型埋め込み層434(LI)が配置されている。p型埋め込み層434は、n型埋め込み層433の上面に接している。p型埋め込み層434の上面はn型ドリフト層435から離れており、それらの間にはp型エピタキシャル層8が入り込んでいる。p型埋め込み層434の不純物濃度は、n型埋め込み層433の不純物濃度よりも低く、たとえばn型埋め込み層433の不純物濃度の10分の1以下とされている。
一方、p型ウェル436内に形成されるn+型ソース層439の電位は、n型埋め込み層433の電位から独立に決定することができる。たとえば、n型埋め込み層433をグランド電位とする一方で、n+型ソース層439およびn+型ドレイン層438を高電位とすることができる。したがって、高耐圧nチャネルDMOS型トランジスタ43は、たとえば、インバータ回路やDC−DCコンバータにおいて用いられるブリッジ回路(フルブリッジ回路またはハーフブリッジ回路)を構成するハイサイドトランジスタおよびローサイドトランジスタのいずれとしても用いることができる。すなわち、ハイサイドトランジスタおよびローサイドトランジスタに共通の素子構造を適用できる。したがって、ブリッジ回路のための素子構造を簡単にすることができる。
さらに、この実施形態では、p型埋め込み層434が、n型ドリフト層435およびn+型ドレイン層438の直下の領域を含む領域に形成されている。これにより、n型ドリフト層435からn型埋め込み層433に向かう空乏層の拡がりを確実に抑制できる。
n型ウェル511の表層部には、p型ドリフト層513(PDRIFT)が形成されており、このp型ドリフト層513を挟んで対向するように、一対の浅いn型ウェル514(NW)が形成されている。p型ドリフト層513の表層部には、p+型ベース層515が形成されている。また、一対の浅いn型ウェル514の表層部には、それぞれ、n+型コレクタ層516およびn+型エミッタ層517が形成されている。
n型ウェル521の表層部には、n型ドリフト層523(NDRIFT)が形成されており、このn型ドリフト層523を挟んで対向するように一対の浅いp型ウェル524(PW)が形成されている。これらの一対のp型ウェル524の表層部には、それぞれ、p+型コレクタ層525およびp+型エミッタ層526が形成されている。さらにn型ドリフト層523内には、浅いn型ウェル527(PW)が形成されており、このn型ウェル527の表層部にはp+型ベース層528が形成されている。また、コレクタ・エミッタのための一対のp型ウェル524の外側には、深いn型ウェル521の内縁に沿って、このn型ウェル521内に、浅いn型ウェル529(NW)が形成されている。この浅いn型ウェル529の表層部には、深いn型ウェル521の電位を制御するためのn+型層560が形成されている。
n型ウェル531の表層部には、n型ドリフト層533(NDRIFT)が形成されている。このn型ドリフト層533の表層部には、複数のp型LDD層534(MVPLDD)が間隔を開けて形成されており、それらの間に複数のn型LDD層535(MVNLDD)がそれぞれ配置されている。p型LDD層534とn型LDD層535との間には、STI構造部536が配置されている。p型LDD層534の表層部にはp+型アノード層537が形成されており、n型LDD層535の表層部にはn+型カソード層538が形成されている。
アクティブ抵抗素子63は、p型エピタキシャル層8に形成された深いn型ウェル631(HVNW/DNW)内に形成されている。n型ウェル631の表層部にはn型またはp型のLDD層632(MVNLDD/MVPLDD)が形成されており、その表層部にはn+型またはp+型のコンタクト層633が形成されている。主として、LDD層632が電気抵抗に寄与する。
次に、深いn型ウェルHVNWの形成領域にn型不純物イオンが注入される(S6)。たとえば、n型不純物イオンとしては燐イオンが用いられ、ドーズ量3.4E+12cm−2程度、加速エネルギー190KeV程度での注入、およびドーズ量1E+14cm−2程度、加速エネルギー190KeV程度での注入を行い、2重注入される。さらに、n型ドリフト層NDRIFT、nチャネルDMOSのドレイン、中耐圧pチャネルMOSのウェルの形成領域にn型不純物イオンが注入される(S7)。たとえば、n型不純物イオンとしては燐イオンが用いられ、ドーズ量は6E+12cm−2程度、加速エネルギーは200KeV程度とされる。さらに、p型ドリフト層PDRIFTの形成領域にp型不純物イオンが注入される(S8)。たとえば、p型不純物イオンとしてはボロンイオンが用いられ、ドーズ量は6.0E+12cm−2程度、加速エネルギーは180keV程度とされる。その後、熱処理として高温アニール(S9)が行われ、注入されたn型不純物イオンおよびp型不純物イオンが活性化される。
このような一連の工程を経ることにより、共通のp型半導体基板2上に、CMOS型トランジスタ31〜33、nチャネル二重拡散MOS型トランジスタ41〜43、pチャネル二重拡散MOS型トランジスタ44、バイポーラ型素子51〜55、受動素子61〜65等を形成した半導体複合素子1が作製される。
さらに、この発明のnチャネル二重拡散MOS型トランジスタは、半導体複合素子に含まれている必要はない。
その他、特許請求の範囲に記載された事項の範囲で種々の設計変更を施すことが可能である。
2 p型半導体基板
3 CMOSエリア
4 DMOSエリア
5 バイポーラエリア
6 受動素子エリア
7 素子分離部
8 p型エピタキシャル層
9 多層配線構造
BL n型埋め込み層
LI p型埋め込み層
DNW 深いn型ウェル
HVNW 深いn型ウェル
NDRIFT n型ドリフト層
PDRIFT p型ドリフト層
NW 浅いn型ウェル
PW 浅いp型ウェル
LVNLDD n型LDD層
MVNLDD n型LDD層
LVPLDD p型LDD層
MVPLDD p型LDD層
30 CMOS型トランジスタ
40 DMOS型トランジスタ
41 低耐圧nチャネルDMOS型トランジスタ
42 中耐圧nチャネルDMOS型トランジスタ
43 高耐圧nチャネルDMOS型トランジスタ
44 高耐圧pチャネルDMOS型トランジスタ
50 バイポーラ素子
60 受動素子
431 深いn型ウェル
432 活性領域
433 n型埋め込み層
434 p型埋め込み層
435 n型ドリフト層
436 p型ウェル(p型ボディ層)
437 n型LDD層
438 n+型ドレイン層
439 n+型ソース層
460 チャネル領域
461 ゲート絶縁膜
462 ゲート電極
463 STI構造部
464 溝
465 絶縁物
466 n+型層
Claims (8)
- p型半導体基板と、
前記p型半導体基板の上にエピタキシャル成長されたp型エピタキシャル層と、
前記p型半導体基板と前記p型エピタキシャル層との境界部に配置されたn型埋め込み層と、
前記p型エピタキシャル層の表層部に形成されたp型ボディ層と、
前記p型ボディ層内に形成され、前記p型ボディ層とともに二重拡散構造を構成するn型ソース層と、
前記n型ソース層との間にチャネル領域を確保するように、前記p型ボディ層から間隔を開けて前記p型エピタキシャル層の表層部に形成されたn型ドリフト層と、
前記チャネル領域から間隔を開けて、前記n型ドリフト層に接するように前記p型エピタキシャル層の表層部に形成されたn型ドレイン層と、
前記n型ドリフト層と前記n型埋め込み層との間において、前記n型埋め込み層の上面に接するように前記p型エピタキシャル層内に埋め込まれ、前記n型埋め込み層よりも不純物濃度の低いp型埋め込み層と、
前記チャネル領域において前記p型エピタキシャル層の表面に形成されたゲート絶縁膜と、
前記ゲート絶縁膜を介して前記チャネル領域に対向するように形成されたゲート電極とを含み、
前記p型埋め込み層の上面は前記n型ドリフト層から離れており、前記p型埋め込み層と前記n型ドリフト層との間に前記p型エピタキシャル層が入り込んでいる、nチャネル二重拡散MOS型トランジスタ。 - 前記n型埋め込み層が、少なくとも、前記p型ボディ層、前記チャネル領域、前記n型ドリフト層、前記n型ソース層、および前記n型ドレイン層の直下の領域を含む領域に渡って連続している、請求項1に記載のnチャネル二重拡散MOS型トランジスタ。
- 前記p型埋め込み層が、前記n型ドリフト層および前記n型ドレイン層の直下の領域を含む領域に形成されている、請求項1または2に記載のnチャネル二重拡散MOS型トランジスタ。
- 前記p型埋め込み層が、前記p型ボディ層の直下の領域を回避して形成されている、請求項1〜3のいずれか一項に記載のnチャネル二重拡散MOS型トランジスタ。
- 前記p型埋め込み層が、前記チャネル領域の直下の領域を回避して形成されている、請求項1〜4のいずれか一項に記載のnチャネル二重拡散MOS型トランジスタ。
- 前記n型ドレイン層と前記チャネル領域との間に介在するように前記n型ドリフト層内に形成され、前記n型ドリフト層内の電流経路を延長する絶縁物埋め込み構造をさらに含む、請求項1〜5のいずれか一項に記載のnチャネル二重拡散MOS型トランジスタ。
- 前記p型ボディ層、前記チャネル領域、前記n型ドリフト層、前記n型ソース層および前記n型ドレイン層を取り囲んで活性領域を区画し、前記n型埋め込み層に接するn型ウェルをさらに含む、請求項1〜6のいずれか一項に記載のnチャネル二重拡散MOS型トランジスタ。
- 請求項1〜7のいずれか一項に記載のnチャネル二重拡散MOS型トランジスタと、
前記p型半導体基板上に形成されたCMOS型素子と、
前記p型半導体基板上に形成されたバイポーラ型素子とを含む、半導体複合素子。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013012276A JP6120586B2 (ja) | 2013-01-25 | 2013-01-25 | nチャネル二重拡散MOS型トランジスタおよび半導体複合素子 |
US14/158,707 US9190513B2 (en) | 2013-01-25 | 2014-01-17 | N-channel double diffusion MOS transistor with P-type buried layer under N-type drift layer, and semiconductor composite device |
US14/882,411 US9812565B2 (en) | 2013-01-25 | 2015-10-13 | N-channel double diffusion MOS transistor with p-type buried layer underneath n-type drift and drain layers, and semiconductor composite device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013012276A JP6120586B2 (ja) | 2013-01-25 | 2013-01-25 | nチャネル二重拡散MOS型トランジスタおよび半導体複合素子 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014143363A JP2014143363A (ja) | 2014-08-07 |
JP6120586B2 true JP6120586B2 (ja) | 2017-04-26 |
Family
ID=51221994
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013012276A Active JP6120586B2 (ja) | 2013-01-25 | 2013-01-25 | nチャネル二重拡散MOS型トランジスタおよび半導体複合素子 |
Country Status (2)
Country | Link |
---|---|
US (2) | US9190513B2 (ja) |
JP (1) | JP6120586B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11171201B2 (en) | 2018-11-15 | 2021-11-09 | Fuji Electric Co., Ltd. | Semiconductor integrated circuit having a first buried layer and a second buried layer |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6255915B2 (ja) * | 2013-11-07 | 2018-01-10 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法及び半導体装置 |
CN104681621B (zh) * | 2015-02-15 | 2017-10-24 | 上海华虹宏力半导体制造有限公司 | 一种源极抬高电压使用的高压ldmos及其制造方法 |
JP6584977B2 (ja) * | 2016-02-24 | 2019-10-02 | 日立オートモティブシステムズ株式会社 | 半導体装置 |
CN107785349B (zh) | 2016-08-26 | 2019-12-17 | 台达电子企业管理(上海)有限公司 | 功率芯片 |
KR102140358B1 (ko) * | 2016-12-23 | 2020-08-03 | 매그나칩 반도체 유한회사 | 잡음 감소를 위한 분리 구조를 갖는 통합 반도체 소자 |
CN109148444B (zh) * | 2018-08-22 | 2020-10-27 | 电子科技大学 | Bcd半导体器件及其制造方法 |
US11562995B2 (en) | 2019-04-11 | 2023-01-24 | Fuji Electric Co., Ltd. | Semiconductor integrated circuit |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11289086A (ja) * | 1997-12-24 | 1999-10-19 | Seiko Instruments Inc | 半導体集積回路装置 |
US6236084B1 (en) * | 1998-06-01 | 2001-05-22 | Seiko Instruments Inc. | Semiconductor integrated circuit device having double diffusion insulated gate field effect transistor |
JP4526179B2 (ja) * | 2000-11-21 | 2010-08-18 | 三菱電機株式会社 | 半導体装置 |
US6882023B2 (en) * | 2002-10-31 | 2005-04-19 | Motorola, Inc. | Floating resurf LDMOSFET and method of manufacturing same |
US7095092B2 (en) * | 2004-04-30 | 2006-08-22 | Freescale Semiconductor, Inc. | Semiconductor device and method of forming the same |
US7262476B2 (en) * | 2004-11-30 | 2007-08-28 | Agere Systems Inc. | Semiconductor device having improved power density |
JP4927340B2 (ja) | 2005-02-24 | 2012-05-09 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置 |
US7244989B2 (en) * | 2005-06-02 | 2007-07-17 | Freescale Semiconductor, Inc. | Semiconductor device and method of manufacture |
US7791161B2 (en) * | 2005-08-25 | 2010-09-07 | Freescale Semiconductor, Inc. | Semiconductor devices employing poly-filled trenches |
US7276419B2 (en) * | 2005-10-31 | 2007-10-02 | Freescale Semiconductor, Inc. | Semiconductor device and method for forming the same |
US7776700B2 (en) * | 2007-01-04 | 2010-08-17 | Freescale Semiconductor, Inc. | LDMOS device and method |
KR101126933B1 (ko) * | 2008-09-02 | 2012-03-20 | 주식회사 동부하이텍 | 폴리에미터형 바이폴라 트랜지스터, bcd 소자, 폴리에미터형 바이폴라 트랜지스터의 제조 방법 및 bcd 소자의 제조 방법 |
US8159029B2 (en) * | 2008-10-22 | 2012-04-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage device having reduced on-state resistance |
JP5534298B2 (ja) * | 2009-06-16 | 2014-06-25 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8330220B2 (en) * | 2010-04-29 | 2012-12-11 | Freescale Semiconductor, Inc. | LDMOS with enhanced safe operating area (SOA) and method therefor |
US8623732B2 (en) * | 2010-06-17 | 2014-01-07 | Freescale Semiconductor, Inc. | Methods of making laterally double diffused metal oxide semiconductor transistors having a reduced surface field structure |
US8575692B2 (en) * | 2011-02-11 | 2013-11-05 | Freescale Semiconductor, Inc. | Near zero channel length field drift LDMOS |
KR101899556B1 (ko) * | 2012-02-03 | 2018-10-04 | 에스케이하이닉스 시스템아이씨 주식회사 | Bcdmos 소자 및 그 제조방법 |
KR101671651B1 (ko) * | 2012-10-16 | 2016-11-16 | 아사히 가세이 일렉트로닉스 가부시끼가이샤 | 전계 효과 트랜지스터 및 반도체 장치 |
US9269806B2 (en) * | 2013-10-03 | 2016-02-23 | Macronix International Co., Ltd. | Semiconductor device and method of fabricating same |
-
2013
- 2013-01-25 JP JP2013012276A patent/JP6120586B2/ja active Active
-
2014
- 2014-01-17 US US14/158,707 patent/US9190513B2/en active Active
-
2015
- 2015-10-13 US US14/882,411 patent/US9812565B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11171201B2 (en) | 2018-11-15 | 2021-11-09 | Fuji Electric Co., Ltd. | Semiconductor integrated circuit having a first buried layer and a second buried layer |
Also Published As
Publication number | Publication date |
---|---|
JP2014143363A (ja) | 2014-08-07 |
US20140210002A1 (en) | 2014-07-31 |
US9812565B2 (en) | 2017-11-07 |
US20160035885A1 (en) | 2016-02-04 |
US9190513B2 (en) | 2015-11-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11239312B2 (en) | Semiconductor chip integrating high and low voltage devices | |
JP6120586B2 (ja) | nチャネル二重拡散MOS型トランジスタおよび半導体複合素子 | |
US9362118B2 (en) | Semiconductor device and manufacturing method thereof | |
JP6591312B2 (ja) | 半導体装置 | |
KR20120081830A (ko) | 반도체 장치 및 그 제조 방법 | |
US20130069154A1 (en) | Semiconductor chip integrating high and low voltage devices | |
KR20070034585A (ko) | 비대칭 헤테로―도핑된 고―전압mosfet(ah2mos) | |
TW201712874A (zh) | 半導體裝置及半導體裝置的製造方法 | |
JPH09139438A (ja) | 半導体装置およびその製造方法 | |
US20100163990A1 (en) | Lateral Double Diffused Metal Oxide Semiconductor Device | |
JP2008004649A (ja) | 半導体装置及びその製造方法 | |
JP2010258355A (ja) | 半導体装置及びその製造方法 | |
US20050263843A1 (en) | Semiconductor device and fabrication method therefor | |
JP2010087133A (ja) | 半導体装置およびその製造方法 | |
TWI443830B (zh) | 用以在bicmos-dmos製程中提高崩潰電壓及特定導通電阻之ldpmos結構 | |
JP6381067B2 (ja) | 半導体装置および半導体装置の製造方法 | |
KR20140001087A (ko) | 수직 파워 mosfet 및 그 제조 방법 | |
KR20110078621A (ko) | 반도체 소자 및 그 제조 방법 | |
US9911814B2 (en) | Semiconductor device and manufacturing method thereof | |
JP6679908B2 (ja) | 半導体装置及びその製造方法 | |
JP6188205B2 (ja) | 高降伏電圧を有するバイポーラトランジスタ | |
KR100482950B1 (ko) | 반도체소자 및 그 제조방법 | |
JP2010028054A (ja) | 半導体装置およびその製造方法 | |
JP2009088449A (ja) | 半導体装置およびその製造方法 | |
JP2000252463A (ja) | 横型mos素子を含む半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20151204 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20161013 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20161013 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20161212 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20170302 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20170328 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6120586 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |