JP7444205B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7444205B2 JP7444205B2 JP2022126638A JP2022126638A JP7444205B2 JP 7444205 B2 JP7444205 B2 JP 7444205B2 JP 2022126638 A JP2022126638 A JP 2022126638A JP 2022126638 A JP2022126638 A JP 2022126638A JP 7444205 B2 JP7444205 B2 JP 7444205B2
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- 239000000758 substrate Substances 0.000 claims description 181
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
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- 238000002955 isolation Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
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- 229910002601 GaN Inorganic materials 0.000 description 1
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- 239000000370 acceptor Substances 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
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- 238000010894 electron beam technology Methods 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
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Description
特許文献1 特開2009-99690号公報
Claims (16)
- 第1の厚みを有する第1領域と、前記第1の厚みと異なる第2の厚みを有する第2領域と、を含む半導体基板と、
前記半導体基板の上面の上方に設けられた上面電極と、
を備え、
前記半導体基板の内部に設けられた第1導電型のドリフト領域と、
前記半導体基板の下面に露出する、前記ドリフト領域よりもドーピング濃度の高い第1導電型のカソード領域と、
前記第1領域において、前記ドリフト領域と前記半導体基板の上面との間に設けられた第2導電型のベース領域と、
前記第2領域において、前記ドリフト領域と前記半導体基板の上面との間に設けられた第2導電型のアノード領域と、
を含み、
前記ベース領域は、前記第1領域に形成される第1ダイオード部のアノードであり、
前記アノード領域は、前記第2領域に形成される第2ダイオード部のアノードである
半導体装置。 - 前記第1領域には、メイン素子部が設けられていて、
前記第2領域は、前記メイン素子部以外の領域に設けられている
請求項1に記載の半導体装置。 - 前記半導体基板の上面において前記メイン素子部を囲むガードリングを有する耐圧構造部を含み、
前記第2ダイオード部は、前記半導体基板の上面において前記ガードリングが囲む領域に配置されている
請求項2に記載の半導体装置。 - 前記半導体基板の上面から前記ドリフト領域に達するまで設けられ、上面視において第1方向に沿って直線形状に延伸する直線部分を有するトレンチ部を含み、
前記ベース領域は、それぞれの前記トレンチ部の前記直線部分に挟まれた領域に設けられている
請求項1から3のいずれか1項に記載の半導体装置。 - 前記第1ダイオード部および前記第2ダイオード部は、前記ドリフト領域の厚みが異なる
請求項1から4のいずれか1項に記載の半導体装置。 - 前記半導体基板の上面の上方に設けられたゲート配線部を含み、
前記第1領域の前記第1ダイオード部および前記第2領域の前記第2ダイオード部は、ゲート配線部を挟んで配置されている
請求項1から5のいずれか1項に記載の半導体装置。 - 前記第1ダイオード部の前記ベース領域と、前記第2ダイオード部の前記アノード領域とは、ドーピング濃度が異なる
請求項1から6のいずれか1項に記載の半導体装置。 - 前記上面電極は、前記第1ダイオード部の前記ベース領域および前記第2ダイオード部の前記アノード領域と接している
請求項1から7のいずれか1項に記載の半導体装置。 - 前記第1ダイオード部の前記ベース領域および前記第2ダイオード部の前記アノード領域の少なくとも一方の上方に、前記上面電極と接続されたポリシリコンを含む
請求項1から8のいずれか1項に記載の半導体装置。 - 前記第2ダイオード部は、前記半導体基板の上面から前記アノード領域よりも深い位置まで設けられ、前記アノード領域よりもドーピング濃度が高い第2導電型の分離ウェル領域を有し、
前記第1ダイオード部および前記第2ダイオード部は、前記分離ウェル領域により分離されている
請求項1から9のいずれか1項に記載の半導体装置。 - 第1の厚みを有する第1領域と、前記第1の厚みよりも小さい第2の厚みを有する第2領域と、を含む半導体基板と、
前記半導体基板の上面の上方に設けられた上面電極と、
を備え、
前記半導体基板の内部に設けられた第1導電型のドリフト領域と、
前記半導体基板の下面に露出する、前記ドリフト領域よりもドーピング濃度の高い第1導電型のカソード領域と、
前記第1領域において、前記ドリフト領域と前記半導体基板の上面との間に設けられた第2導電型のベース領域と、
前記第2領域において、前記ドリフト領域と前記半導体基板の上面との間に設けられた第2導電型のアノード領域と、
を含み、
前記第1領域には、前記半導体基板の上面から前記ベース領域よりも深い位置まで設けられ、前記ベース領域よりもドーピング濃度が高い第2導電型の第1ウェル領域に囲まれたメイン素子部が設けられており、
前記第2領域は、前記第1ウェル領域よりも外側に設けられている
半導体装置。 - 第1の厚みを有する第1領域と、前記第1の厚みと異なる第2の厚みを有する第2領域と、を含む半導体基板と、
前記半導体基板の上面の上方に設けられた上面電極と、
を備え、
前記半導体基板の内部に設けられた第1導電型のドリフト領域と、
前記第1領域から前記第2領域に渡って、前記半導体基板の下面に露出する、前記ドリフト領域よりもドーピング濃度の高い第1導電型のカソード領域と、
前記第1領域において、前記ドリフト領域と前記半導体基板の上面との間に設けられた第2導電型のベース領域と、
前記第2領域において、前記ドリフト領域と前記半導体基板の上面との間に設けられた第2導電型のアノード領域と、
を含む半導体装置。 - 前記第2領域の前記第2の厚みは、前記第1領域の前記第1の厚みよりも小さい
請求項1から10または12のいずれか1項に記載の半導体装置。 - 前記第2領域の前記第2の厚みは、前記第1領域の前記第1の厚みよりも大きい
請求項1から10または12のいずれか1項に記載の半導体装置。 - 前記半導体基板は、シリコン基板である
請求項1から14のいずれか1項に記載の半導体装置。 - 前記半導体基板は、炭化シリコン基板である
請求項1から14のいずれか1項に記載の半導体装置。
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