JP6790046B2 - バリア領域を含む半導体デバイス - Google Patents
バリア領域を含む半導体デバイス Download PDFInfo
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
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Description
10 半導体デバイス
15 要素
20 トランジスタ
201 トランジスタセル
100 半導体基板
110 第1の主表面
111 絶縁層
115 絶縁材料
120 第2の主表面
125 導電層
127 裏側金属層
130 トレンチ
131 活性トレンチ
132 ダミートレンチ
133 第1のソーストレンチ
134 第2のソーストレンチ
135 浮遊トレンチ
136 ゲートトレンチ
138 ドープ部分
160 メサ
161 第1のメサ
162 第2のメサ
163、164 ダミーメサ
180 ソース端子
181 ソース導電層
182 抵抗器要素
183 ソースコンタクト
185 ゲート端子
190 裏側端子
201 ソース領域
201a 第1のソース領域
201b 第2のソース領域
205 裏側領域
206 裏側電極
209 ドープ部分
210 ゲート電極
211 誘電体層
220 本体領域
221 片側チャネル
224 第1のドープ領域
225 第2のドープ領域
226 メサコンタクト
230 バリア領域
230a 底部側
231 第1のバリア領域
232 第2のバリア領域
235、236、237 部分
260 ドリフト領域
Claims (20)
- トランジスタを含む半導体デバイスであって、
第1の主表面を有する半導体基板内の第1の導電型のドリフト領域と、
前記ドリフト領域と前記第1の主表面との間の第2の導電型の本体領域と、
前記第1の主表面内の複数のトレンチであって、前記トレンチは、前記半導体基板を、第1のメサおよびダミーメサを含む複数のメサにパターニングし、
前記複数のトレンチは少なくとも1つの活性トレンチを含み、前記第1のメサは前記活性トレンチの第1の側に配置されており、前記ダミーメサは前記活性トレンチの第2の側に配置されている、複数のトレンチと、
前記活性トレンチ内に配置されたゲート電極と、
前記第1のメサ内の前記第1の導電型のソース領域と、
を含み、
前記トランジスタの片側チャネルが前記第1のメサ内に形成されるように構成される、
半導体デバイス。 - 前記第1のメサの幅が1μm未満である、請求項1に記載の半導体デバイス。
- 前記ソース領域がソースコンタクトを介してソース端子に電気接続されており、前記ダミーメサが、少なくとも第1の導電型のキャリアに対して前記ソースコンタクトよりも高い抵抗を有するコンタクトを介して前記ソース端子に接続されている、請求項1に記載の半導体デバイス。
- 前記ドリフト領域よりも高いドーピング濃度を有する導電型の第1のバリア領域をさらに含み、前記第1のバリア領域は前記本体領域と前記ドリフト領域との間に配置されており、前記第1のバリア領域は前記第1のメサおよび前記ダミーメサのうちの少なくとも一方の内部に配置されている、請求項1から3のいずれか一項に記載の半導体デバイス。
- 前記第1のバリア領域が前記第1のメサ内に配置されており、前記ダミーメサには存在しない、請求項4に記載の半導体デバイス。
- 前記第1のバリア領域が前記ダミーメサ内に配置されており、前記第1のメサには存在しない、請求項4に記載の半導体デバイス。
- 前記複数のトレンチが、第1のソーストレンチおよび第2のソーストレンチ、ならびに前記第1のソーストレンチと前記第2のソーストレンチとの間のさらなるトレンチをさらに含み、前記第1のソーストレンチおよび前記第2のソーストレンチ内に配置された導電材料がソース端子にそれぞれ電気接続されており、
ダミーメサが前記第1のソーストレンチおよび前記第2のソーストレンチの各々と前記さらなるトレンチとの間に配置されており、
前記第1のバリア領域が、前記第1のソーストレンチおよび前記第2のソーストレンチの各々と前記さらなるトレンチとの間の前記ダミーメサ内に配置されている、
請求項4または6に記載の半導体デバイス。 - 前記トレンチが浮遊トレンチをさらに含み、前記浮遊トレンチ内に配置された導電材料がゲート端子および前記ソース端子から電気的に遮断されている、請求項7に記載の半導体デバイス。
- 前記複数のトレンチがソーストレンチ及びダミーゲートトレンチを含み、前記ソーストレンチが前記第1のメサに隣接して配置されており、前記ダミーゲートトレンチがゲート電位に接続され、前記ダミーメサに隣接して配置されている、
請求項1から6のいずれか一項に記載の半導体デバイス。 - トランジスタを含む半導体デバイスであって、
第1の主表面を有する半導体基板内の第1の導電型のドリフト領域と、
前記ドリフト領域と前記第1の主表面との間の第2の導電型の本体領域と、
前記第1の主表面内の複数のトレンチであって、前記トレンチは、前記半導体基板を、ダミーメサを含む複数のメサにパターニングし、
前記複数のトレンチはダミートレンチを含み、前記ダミーメサは前記ダミートレンチの両側に配置されており、
前記複数のトレンチは活性トレンチをさらに含み、第1のメサが前記活性トレンチの第1の側に隣接して配置されており、前記ダミーメサのうちの一方が前記活性トレンチの第2の側に隣接して配置されている、複数のトレンチと、
前記活性トレンチ内に配置されたゲート電極と、
前記第1のメサ内の前記第1の導電型のソース領域と、
前記ドリフト領域のドーピング濃度よりも高いドーピング濃度における前記第1の導電型のバリア領域であって、前記バリア領域は前記本体領域と前記ドリフト領域との間に配置されており、前記バリア領域は、少なくとも、前記活性トレンチの前記第2の側に隣接する前記ダミーメサと異なる前記ダミーメサのうちの別のものの内部に配置されており、前記バリア領域は前記第1のメサには存在しない、バリア領域と、
を含む、半導体デバイス。 - トランジスタを含む半導体デバイスであって、
第1の主表面を有する半導体基板内の第1の導電型のドリフト領域と、
前記ドリフト領域と前記第1の主表面との間の第2の導電型の本体領域と、
前記第1の主表面内の複数のトレンチであって、前記トレンチは、前記半導体基板を、第1のメサを含む複数のメサにパターニングし、
前記複数のトレンチは活性トレンチならびに第1のソーストレンチおよび第2のソーストレンチを含み、前記第1のソーストレンチおよび前記第2のソーストレンチ内の導電材料はソース端子に接続されている、複数のトレンチと、
前記活性トレンチ内に配置されたゲート電極と、
前記第1のメサ内の前記第1の導電型のソース領域であって、前記第1のメサは前記活性トレンチに隣接して配置されている、ソース領域と、
前記第1のソーストレンチと前記第2のソーストレンチとの間の第2のメサであって、前記第2のメサは前記第1のソーストレンチおよび前記第2のソーストレンチのうちの少なくとも一方と接触している、第2のメサと、
前記ドリフト領域のドーピング濃度よりも高いドーピング濃度における前記第1の導電型のバリア領域であって、前記バリア領域は前記本体領域と前記ドリフト領域との間に配置されており、前記バリア領域は前記第2のメサ内に配置されており、前記バリア領域の鉛直方向サイズsは前記第2のメサの幅の少なくとも2倍である、バリア領域と、
を含む、半導体デバイス。 - 前記複数のトレンチが前記第1のソーストレンチと前記第2のソーストレンチとの間のダミートレンチをさらに含み、ダミーメサは前記ダミートレンチの両側に配置されている、請求項11に記載の半導体デバイス。
- 前記第1のメサの幅が1μm未満である、請求項11または12に記載の半導体デバイス。
- 前記第1のメサが前記活性トレンチと前記第1のソーストレンチとの間に配置されている、請求項11から13のいずれか一項に記載の半導体デバイス。
- 前記ダミートレンチ内の導電材料が前記ソース端子に電気接続されている、請求項12に記載の半導体デバイス。
- 前記複数のトレンチが、ダミートレンチ、ゲート電位に接続されている前記ダミートレンチ内の導通材料、前記ダミートレンチのどちらかの側に配置されたダミーメサを更に含んでいる、請求項11に記載の半導体デバイス。
- トランジスタを含む半導体デバイスであって、
第1の主表面を有する半導体基板内の第1の導電型のドリフト領域と、
前記ドリフト領域と前記第1の主表面との間の第2の導電型の本体領域と、
前記第1の主表面内の複数のトレンチであって、前記トレンチは、前記半導体基板を、第1のメサおよび第2のメサを含む複数のメサにパターニングし、
前記複数のトレンチは活性トレンチを含み、ゲート電極が前記活性トレンチ内に配置されている、複数のトレンチと、
前記第1のメサおよび前記第2のメサのうちの少なくとも一方の内部の前記第1の導電型のソース領域と、
前記ドリフト領域のドーピング濃度よりも高いドーピング濃度における前記第1の導電型の第1のバリア領域であって、前記第1のバリア領域は前記本体領域と前記ドリフト領域との間に配置されており、前記第1のバリア領域は前記第1のメサ内に配置されている、第1のバリア領域と、
前記第1のバリア領域よりも低いドーピング濃度を有し、前記ドリフト領域よりも高いドーピング濃度を有する前記第1の導電型の第2のバリア領域であって、前記第2のバリア領域は前記本体領域と前記ドリフト領域との間に配置されており、前記第2のバリア領域は前記第2のメサ内に配置されている、第2のバリア領域と、
を含み、前記第2のメサはダミーメサである、半導体デバイス。 - 前記ソース領域が前記第1のメサおよび前記第2のメサ内に配置されている、請求項17に記載の半導体デバイス。
- 請求項17または18に記載の半導体デバイスと、前記半導体デバイスに接続された要素と、を備える電気デバイス。
- 前記要素がモータおよび論理回路のうちの一方である、請求項19に記載の電気デバイス。
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