WO2009106680A1 - Extended utilization area for a memory device - Google Patents

Extended utilization area for a memory device Download PDF

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Publication number
WO2009106680A1
WO2009106680A1 PCT/FI2009/050083 FI2009050083W WO2009106680A1 WO 2009106680 A1 WO2009106680 A1 WO 2009106680A1 FI 2009050083 W FI2009050083 W FI 2009050083W WO 2009106680 A1 WO2009106680 A1 WO 2009106680A1
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WO
WIPO (PCT)
Prior art keywords
memory device
access
memory
profiles
accordance
Prior art date
Application number
PCT/FI2009/050083
Other languages
English (en)
French (fr)
Inventor
Jani Hyvönen
Kimmo Mylly
Jussi HÄKKINEN
Yevgen Gyl
Original Assignee
Nokia Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=41014077&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO2009106680(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Nokia Corporation filed Critical Nokia Corporation
Priority to JP2010548134A priority Critical patent/JP5663720B2/ja
Priority to EP18215330.4A priority patent/EP3493067B1/en
Priority to EP09715221.9A priority patent/EP2248023B1/en
Priority to KR1020107021534A priority patent/KR101281326B1/ko
Priority to KR1020137002338A priority patent/KR101468824B1/ko
Priority to CN200980106241.1A priority patent/CN101952808B/zh
Publication of WO2009106680A1 publication Critical patent/WO2009106680A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1433—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a module or a part of a module
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1441—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a range
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1052—Security improvement
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates generally to memory devices.
  • the present invention relates to providing systems, methods and devices for run-time configuration of mass memory devices.
  • memory devices are invoked for a variety of reasons, for example, to read, write, modify, delete, or change the attributes of the data that resides on a memory device.
  • These operations may be targeted to access varying chunks of data according the needs of an application program that invokes the specific memory access operation. For example, an application may require access to a small chunk of data from random addresses, the same address, or sequential addresses on the memory device. Similarly, the same or a different application may require access to large chunks of data from random addresses, the same address, or sequential addresses on the memory device. Examples of the different applications that may access a memory device include file systems, different databases, kernel reading code pages, and other applications that use the memory device.
  • a mass memory device is optimized for one kind of application, or a defined group of applications, with particular memory access characteristics.
  • This optimization may entail optimization of data throughput, life time and/or power consumption associated with the memory device.
  • Due to this fixed optimization strategy when a memory device is placed into a different environment with new access demands, it may fail to optimally perform under the requirements of the new environment.
  • the lack of flexibility in optimizing such memory devices may be partly due to inherent limitations that render these memory devices incapable of accommodating optimized functionalities for multiple kinds of access operations.
  • the reason for electing to optimize a memory device for a defined, and thus limited, group of applications is to simplify the design, and to effect cost savings.
  • a method, system and memory device are therefore provided to overcome the deficiencies of the prior art systems by allowing run-time configuration of a mass memory device.
  • a method for configuring access to a memory device comprises receiving one or more commands for activating one or more access profiles associated with said memory device, and configuring access to said memory device in accordance with at least one of said access profiles.
  • the access profiles may correspond to at least one of a random and a sequential mode of access.
  • the access profiles may further correspond to at least one of a read, a write, an erase, and a modify attribute operation.
  • one or more access profiles are adapted to accommodate repeated access requests to an identical address of said memory device.
  • one or more access profiles are adapted to produce an optimized performance associated with said memory device.
  • the performance may be optimized in accordance with at least one of: data throughput, lifetime, and power consumption associated with said memory device.
  • one or more received commands comprise a metadata portion for designating a preferred access profile corresponding to said command.
  • a specific memory location may be utilized in accordance with said access profile.
  • the specific memory location may comprise a section of said memory device with special characteristics. For example, it may include a more durable and performance-effective portion of the physical memory, or a portion of the memory that utilizes a specific memory technology.
  • the specific memory location may comprise a separate physical memory chip.
  • one or more access profiles are associated with one or more partitions of said memory device.
  • the configuring of the memory device is adapted in parallel for two or more parallel access profiles. In one embodiment, such configuring is carried out in accordance with JESD84 standard for eMMC. This configuring may further comprise designating access priority levels to resolve simultaneous access conflicts to memory resources.
  • the memory device is used to effect both mass memory and system memory implementations.
  • a default access profile may be used to configure said memory device upon power up.
  • Another aspect of the present invention relates to a memory device that comprises one or more registers for storing one or more predefined access profiles associated with said memory device.
  • the memory device also comprises receiving means for receiving one or more commands for activating one or more access profiles associated with said memory device, and configuring means for configuring access to said memory device in accordance with at least one of said predefined access profiles.
  • a currently active access profile may reside in a designated memory register.
  • one or more of said predefined access profiles may be updated with a new version of said access profile.
  • a computer program product embodied on a computer-readable medium.
  • the computer program product comprises a computer code for receiving one or more commands for activating one or more access profiles associated with said memory device, and a computer code for configuring access to said memory device in accordance with at least one of said access profiles.
  • a system for accessing a memory device is disclosed.
  • the system comprises an entity for receiving one or more commands for activating one or more access types associated with said memory device, and an entity for configuring access to said memory device in accordance with at least one of said access profiles.
  • a system for accessing a memory device is disclosed.
  • the system comprises a host for issuing one or more commands in accordance with access needs for said memory device, and an entity for receiving said commands and configuring access to said memory device in accordance with at least one or more access profiles.
  • FIG. 1 illustrates a perspective view of an exemplary electronic device within which various embodiments of the present invention may be implemented
  • FIG. 2 illustrates an exemplary schematic representation of the circuitry which may be included in the electronic device of Fig. 1.
  • FIG. 3 illustrates a flow diagram of an exemplary embodiment of the present invention.
  • FIG. 4 illustrates a flow diagram of another exemplary embodiment of the present invention.
  • FIG. 5 illustrates an exemplary device in accordance with an embodiment of the present invention.
  • a system may utilize a mass memory device separate from a system memory device to accommodate different memory access demands.
  • the various embodiments of the present invention disclose methods, systems and devices to enable run-time configuration of a memory device in accordance with certain memory access profiles.
  • the configuration may be effected for a portion of the memory device, a partition of the memory device, or even one single access location on the memory device. Since the system that accesses the memory device knows, or is capable of determining, the type of memory access needs (e.g., whether it is a read, write, erase, modify attribute, random, or a sequential operation), it can issue commands for configuring the memory device in accordance with an access profile that is most optimized/suitable for the particular access command.
  • Such access profiles for example, may be adapted for optimizing data throughput, lifetime and/or power consumption associated with particular uses of the memory device.
  • a default access profile may be defined to configure a memory device when, for example, the device or system initially boots up.
  • Such a default profile while providing a starting point for potential future modifications, may be pre-selected to accommodate the most likely access needs for that memory device. This profile may remain in effect until the memory device is powered down, or it may be replaced by another profile in accordance with the embodiments of the present invention.
  • the information regarding the nature and type of memory access allows the memory device to organize itself in a manner that is most suited for a particular access command, resulting in improved performance and higher reliability. These improvements are largely due to the elimination of background operations and unnecessary data merging that are normally associated with traditional memory access methods.
  • the techniques of the various embodiments of the present invention may be more effective in optimizing sequential memory access operations, where background processing and data merging are more abundant. These optimizations further extend the life of the storage device, and result in reduced energy consumption by the device.
  • the embodiments of the present invention further enable the utilization of the same memory device both as the mass storage memory and the system memory, thus eliminating the need for separate memory devices that are utilized in the systems of prior art.
  • all non- volatile memory needs of a system may be accommodated using a single eMMC memory, where the Operating System image, user data, and other parameters may be stored on the same device.
  • the very same memory device may be used to store the various types of user applications, the Operating System and other system data files. This consolidation is expected to further spur the adoption of a standardized memory device with higher production volumes, and to eventually lead to lower-cost memory devices.
  • a memory device 500 may comprise a physical memory 502 with one or more registers 504 for accommodating the predefined access profiles that are used to optimize the memory device.
  • the memory device 500 may further comprise a receiving means 510 that is adapted to receive one or more commands, through the communication interface 512, for activating a particular access profile.
  • the receiving means 510 is illustrated as comprising a separate section of the controller 508.
  • the controller 508 may configure the memory device 500 in accordance with one or more access profiles that reside in memory registers 504.
  • the communication between the controller 508 and the physical memory 502 may be conducted through the interface 506.
  • one predefined access profile may be a burst mode profile that facilitates high-speed transfer of large data chunks and provides a 'ready' indication to the host prior to, or after, such transfer.
  • the needed flash memory management operations may take place subsequent to the transfer at a convenient time, for example, while no other activities or memory access operations are taking place.
  • Another example of an access profile includes a random mode profile which enables quick access to short, random memory locations on the device.
  • the memory device in accordance with embodiments of the present invention may further comprise another register for accommodating the currently active access profile. This profile, which may be any one of the supported predefined profiles, governs the current access operations to the memory device.
  • such register may comprise a default profile that is activated during the boot up of the host system and/or the power up of the memory device.
  • This active profile may remain in effect until the memory device is powered down, or it may be replaced by another profile in accordance with the embodiments of the present invention.
  • Run-time configurability of the memory device in accordance with the present invention is effected by replacing the contents of the currently active profile register with one of the predefined profiles that resides on the first set of registers. Accordingly, when the need for a new type of memory access arises, a command may be issued to activate a suitable profile. The command may activate any one of the predefined access profiles, including but not limited to, the default profile.
  • the various access profiles may be updated or uploaded onto the memory device.
  • an existing access profile may be augmented (or completely replaced with a new version) to add or remove certain features and functionalities.
  • an entirely new access profile may be uploaded to the memory device, thus increasing the number of available access profiles that can be readily used to configure the memory device.
  • an access profile may be implemented as a binary file that further comprises the required logic to implement an access profile. This way, the access profile may be considered part of the memory device firmware responsible for handling specific accesses needs in an optimized fashion.
  • Figures 1 and 2 show one representative electronic device 12 within which embodiments of the present invention may be implemented. It should be understood, however, that the present invention is not intended to be limited to one particular type of device. In fact, the various embodiments of the present invention may be readily adapted for use in any stand-alone or embedded system that comprises or accesses a memory device.
  • the electronic device 12 of Figures 1 and 2 includes a housing 30, a display 32 in the form of a liquid crystal display, a keypad 34, a microphone 36, an ear-piece 38, a battery 40, an infrared port 42, an antenna 44, a smart card 46 in the form of a UICC according to one embodiment, a card reader 48, radio interface circuitry 52, codec circuitry 54, a controller 56 and a memory 58.
  • Individual circuits and elements are all of a type well known in the art, for example in the Nokia range of mobile telephones.
  • Fig. 3 is an example flow diagram illustrating run-time configurability of a memory device in accordance to an embodiment of the present invention. As illustrated in Fig.
  • the memory device upon boot up of the system in step 100, organizes itself according to the default profile in step 102.
  • the exemplary default profile used in Fig. 3 configures the memory device to accommodate the reading of large sequential data from the memory device.
  • the system reads a large amount of sequential data, which for example, may comprise the operating system of the host device.
  • the system Upon completion of the large read operation, the system enters an idle state in step 106. Since the majority of memory access operations during an idle state is likely to involve short random read/write operations, the memory device, in step 108, is commanded to activate an access profile for reading/writing short random data.
  • Step 110 the system requires large sequential reads/writes.
  • this need may arise when the system is connected to an external mass storage device.
  • a mass storage device may, for example, include a stand-alone memory device such as a USB memory, or a PC or other electronic device that comprises one or more mass storage components.
  • the memory device in accordance with embodiments of the present invention, in step 112, receives a command to activate the access profile that is optimized for reading/writing large sequential data.
  • the system conducts at least a portion of the large sequential read/write transfer.
  • the system of the present invention may need to access the memory device in short, random I/O access cycles, as illustrated in step 116.
  • the memory device may receive a command to suspend its current access profile, which is directed towards reading/writing long sequential data, and activate an alternate access profile that is optimized for reading/writing short random data.
  • the memory device in step 122, may receive a subsequent command to revert back to the access profile for reading/writing large sequential data. The system may then resume reading/writing large sequential data in step 124.
  • Fig. 4 illustrates an alternate embodiment of the present invention according to which two or more memory access operations (and their corresponding access profiles) may be implemented in parallel.
  • steps 200 to 216 represent similar operations as their counterparts in Fig. 3.
  • the memory device upon boot up in step 200, the memory device in accordance with embodiments of the present invention organizes itself according to the default profile in step 202.
  • the exemplary default profile used in Fig. 4 configures the memory device to accommodate the reading of large sequential data from the memory device.
  • step 204 the system reads a large amount of sequential data, which for example, may comprise the operating system of the host device.
  • the system Upon completion of the large read operation, the system enters an idle state in step 206. Since the majority of memory access operations during an idle state is likely to involve short random read/write operations, the memory device, in step 208, is commanded to activate an access profile for reading/writing short random data. The system may then require access to large sequential reads/writes in step 210. This need may arise, for example, in preparation for large data transfers to/from an external memory device.
  • the memory device in accordance with embodiments of the present invention, in step 212, receives a command to activate the access profile that is optimized for reading/writing large sequential data.
  • step 214 the system conducts at least a portion of the large sequential read/write transfers before the system need for short read/write access cycles to the memory device arises in step 216.
  • the present embodiment in accordance with Fig. 4 accommodates both memory access modes by commanding the memory device in accordance with embodiments of the present invention to activate a parallel access profile for reading/writing short random data in step 220. Accordingly, while the system continues to read/write large sequential data in step 218, it may simultaneously (or in an interleaved fashion) conduct short memory access operations in step 222.
  • JEDEC eMMC is a standardized mass storage device comprising a memory and a controller device.
  • the controller handles block-management functions associated with the memory such as logical block allocation and wear leveling.
  • the communication between the memory and the host device is also handled by the controller according to a standard protocol.
  • This protocol defines, among other signals, a bidirectional command signal, CMD, that is used for device initialization, and transfer of commands between the host and memory device. More specifically, CMD23 (SET BLOCK COUNT) defines the number of blocks (read/write) and the reliable writer parameter (write) for a block read/write command. CMD23 includes a 32 bit argument field, of which bits 15 to 0 are allocated for setting the number of blocks for the corresponding read/write command, and bits 30 to 16 are designated as stuff bits. In accordance to one embodiment of the present invention, these stuff bits may be utilized to designate different access profiles for the memory device. By the way of example, and not by limitation, one profile may be defined as a burst profile mode, corresponding to a fast, contiguous data access mode.
  • the memory device When in burst profile mode, the memory device, immediately after receiving all the data, may indicate "exit busy" and set the transfer mode to "transfer state," thus facilitating faster execution of subsequent accesses by the host.
  • the memory device may also enable the host to send additional commands corresponding to a different access profile. This way, a degree of parallelism in the I/O operations is established.
  • access priority levels may be defined to resolve access conflicts, where two or more profiles run in parallel and require access to the same memory resource at the same time. Examples of such a memory resources include a RAM buffer, a Flash bus, and other memory resources.
  • the access profile associated with a media device may be adapted to comprise different control and/or setting profiles that are associated with different partitions of the memory device.
  • partitions may comprise logical or physical partitions of the memory device. For example, one partition may be configured for random read/write operations while another partition may be configured to provide sequential access.
  • a memory access (e.g., an I/O read/write) command may be configured to comprise a metadata portion for designating a preferred access profile corresponding to that access command.
  • the system in accordance with the present invention may recognize that one address is being continuously and frequently updated, and accordingly, it may set an appropriate access profile for that memory command.
  • the memory device - depending on its internal implementations and capabilities - may map such sustained and specific access operations to certain sections of the physical memory with special characteristics. For example, the mapping may be directed to a more a more durable and performance- effective portion of the physical memory, a portion of the memory that utilizes a specific memory technology, or to a separate physical chip that is more suitably designed for such repeated access operations.
  • the memory device firmware may take an action in accordance with the access profile request of an embodiment of the present invention and handle the I/O operation in a different way.
  • a computer-readable medium may include removable and non-removable storage devices including, but not limited to, Read Only Memory (ROM), Random Access Memory (RAM), compact discs (CDs), digital versatile discs (DVD), etc.
  • program modules may include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types.
  • Computer- executable instructions, associated data structures, and program modules represent examples of program code for executing steps of the methods disclosed herein. The particular sequence of such executable instructions or associated data structures represents examples of corresponding acts for implementing the functions described in such steps or processes.
PCT/FI2009/050083 2008-02-28 2009-01-30 Extended utilization area for a memory device WO2009106680A1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2010548134A JP5663720B2 (ja) 2008-02-28 2009-01-30 メモリ機器のための拡張利用範囲
EP18215330.4A EP3493067B1 (en) 2008-02-28 2009-01-30 Extended utilization area for a memory device
EP09715221.9A EP2248023B1 (en) 2008-02-28 2009-01-30 Extended utilization area for a memory device
KR1020107021534A KR101281326B1 (ko) 2008-02-28 2009-01-30 메모리 장치의 활용 영역 확장
KR1020137002338A KR101468824B1 (ko) 2008-02-28 2009-01-30 메모리 장치의 활용 영역 확장
CN200980106241.1A CN101952808B (zh) 2008-02-28 2009-01-30 存储设备的扩展利用区域

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/039,672 US8307180B2 (en) 2008-02-28 2008-02-28 Extended utilization area for a memory device
US12/039,672 2008-02-28

Publications (1)

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WO2009106680A1 true WO2009106680A1 (en) 2009-09-03

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PCT/FI2009/050083 WO2009106680A1 (en) 2008-02-28 2009-01-30 Extended utilization area for a memory device

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US (10) US8307180B2 (ko)
EP (2) EP3493067B1 (ko)
JP (7) JP5663720B2 (ko)
KR (2) KR101468824B1 (ko)
CN (2) CN104657284B (ko)
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