US20100332922A1 - Method for managing device and solid state disk drive utilizing the same - Google Patents

Method for managing device and solid state disk drive utilizing the same Download PDF

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US20100332922A1
US20100332922A1 US12/721,692 US72169210A US2010332922A1 US 20100332922 A1 US20100332922 A1 US 20100332922A1 US 72169210 A US72169210 A US 72169210A US 2010332922 A1 US2010332922 A1 US 2010332922A1
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memory
memory block
page
slc
desired data
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US12/721,692
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Po-Wei Chang
Kun-Hung Hsieh
Li-Chun Tu
Ting-Chun Chang
Kuo-Hung Wang
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MediaTek Inc
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MediaTek Inc
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Priority to US12/721,692 priority patent/US20100332922A1/en
Assigned to MEDIATEK INC. reassignment MEDIATEK INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WANG, KUO-HUNG, CHANG, TING-CHUN, HSIEH, KUN-HUNG, TU, LI-CHUN, CHANG, PO-WEI
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by G11C11/00
    • G11C5/14Power supply arrangements, e.g. Power down/chip (de)selection, layout of wiring/power grids, multiple supply levels
    • G11C5/143Detection of memory cassette insertion/removal; Continuity checks of supply and ground lines ; Detection of supply variations/interruptions/levels ; Switching between alternative supplies
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023Free address space management
    • G06F12/0238Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/30Power supply circuits
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72Details relating to flash memory management
    • G06F2212/7201Logical to physical mapping or translation of blocks or pages

Abstract

A solid state disk drive is provided. The solid state disk drive includes a multiple level cell (MLC) memory device and a controller. The MLC memory device includes memory blocks each comprising memory cells capable of storing more than a single bit of data per cell. The controller transforms at least one memory block into a single level cell (SLC)-like memory block, and accesses the memory block in an SLC manner.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application claims the benefit of U.S. Provisional Application No. 61/221,569 filed Jun. 30, 2009, and entitled “Apparatus and Operation Method of Flash Memory System”. The entire contents of which are hereby incorporated by reference.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The invention relates to a method for managing a memory device, and more particularly to a method for managing a memory device that extends the operating lifespan of the memory device.
  • 2. Description of the Related Art
  • Flash memory is widely used in electronic products today, especially for portable applications, as a result of its non-volatility and in system re-programmability. The basic structure of a flash memory cell includes a control gate, a drain diffusion region and a source diffusion region disposed on a substrate to form a transistor with a floating gate under the control gate serving as an electron storage device. The channel region lies under the floating gate with a tunnel oxide insulation layer therebetween. The energy barrier of the tunnel oxide insulation layer can be overcome by applying a sufficiently high electric field thereacross. This allows electrons to pass through the tunnel oxide insulation layer, which is used to change the amount of electrons stored in the floating gate. The amount of electrons stored in the floating gate determines the threshold voltage (Vt) of the cell. More electrons stored in the floating gate causes the cell to have a higher Vt. The Vt of a cell is used to represent the stored data of the cell.
  • Generally, a flash memory, which can store one bit of data in a cell, is called a Single Level Cell (SLC). Meanwhile, a flash memory, which can store more than one bit of data in a cell, is called a Multiple Level Cell (MLC). Multiple Level Cell (MLC) technology has attracted a lot of attention due to its area efficiency. By storing 2N discrete levels of Vt, the MLC can store N bits of data per cell, thus reducing the equivalent cell size to 1/N. Because of the advantage of multiple bits of data per cell, the MLC has become one of the best candidates for mass storage applications that typically require higher and higher densities.
  • Although the MLC is more area efficient than the SLC, one drawback of using the MLC is its relatively short operating lifespan. Generally, the maximum amount of erasing of an MLC memory block is about 10K times, versus about 100K times for an SLC memory block. Thus, a method for managing a multiple level cell flash memory device that extends the operating lifespan thereof is highly desired.
  • BRIEF SUMMARY OF THE INVENTION
  • Solid state disk drives and methods for managing a memory device are provided. An embodiment of a solid state disk drive comprises a multiple level cell (MLC) memory device and a controller. The MLC memory device comprises a plurality of memory blocks each comprising a plurality of memory cells capable of storing more than a single bit of data per cell. The controller transforms at least one memory block into a single level cell (SLC)-like memory block, and accesses the memory block in an SLC manner.
  • An embodiment of a method for managing a memory device, comprising a plurality of memory blocks each with a plurality of memory cells capable of storing more than a single bit of data per cell therein, comprises: receiving desired data in accordance with a write operation of the memory device; estimating a failure probability of at least one memory block to be written corresponding to the write operation; and writing the desired data to the memory cells of the memory block in a single level cell (SLC) manner when the estimated failure probability thereof exceeds a predetermined threshold.
  • Another embodiment of a solid state disk drive comprises a multi-channel multiple level cell (MLC) memory device and a controller. The multi-channel MLC memory device comprises a plurality of memory modules each comprising a plurality of memory cells capable of storing more than a single bit of data per cell therein, wherein each memory cell is associated with a plurality of pages. Each page is grouped into one of a plurality of page groups in accordance with different page properties. The controller receives at least one program command from a host to write desired data to the multi-channel MLC memory device, allocates a predetermined number of empty pages each belonging to different memory modules in accordance with the program command, and writes the desired data in the empty pages, wherein the empty pages allocated by the controller for an access operation belongs to the same page group.
  • Another embodiment of a method for managing a multi-channel memory device comprising a plurality of memory modules each with a plurality of memory cells capable of storing more than a single bit of data per cell therein, wherein each memory cell is associated with a plurality of pages, comprises: grouping each page into one of a plurality of page groups in accordance with different page properties; receiving at least one program command to write desired data to the multi-channel MLC memory device; allocating a predetermined number of empty pages each belonging to different memory modules in accordance with the program command; and writing the desired data in the empty pages, wherein the empty pages allocated by the controller for an access operation belongs to the same page group.
  • A detailed description is given in the following embodiments with reference to the accompanying drawings.
  • BRIEF DESCRIPTION OF DRAWINGS
  • The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
  • FIG. 1 shows a solid state disk drive configured according to an embodiment of the invention;
  • FIG. 2 shows a solid state disk drive configured according to another embodiment of the invention;
  • FIG. 3 shows a flow chart of the memory management method for a write operation according to an embodiment of the invention;
  • FIG. 4 shows a flow chart of the memory management method for a read operation according to an embodiment of the invention;
  • FIG. 5 shows a flow chart of a memory management method according to another embodiment of the invention;
  • FIG. 6 shows a flow chart of a memory management method according to another embodiment of the invention;
  • FIG. 7 shows a timing diagram for writing desired data in a memory cell of each memory channel in accordance with an embodiment of the invention;
  • FIG. 8 shows a timing diagram for writing desired data in a memory cell of a portion of memory channels in accordance with another embodiment of the invention; and
  • FIG. 9 shows a timing diagram for accessing the memory channels in accordance with another embodiment of the invention.
  • DETAILED DESCRIPTION OF THE INVENTION
  • The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
  • FIG. 1 shows a solid state disk (SSD) drive configured according to an embodiment of the invention. A solid state disk drive 100 comprises a host interface 101, a controller 102, a buffer 103 and a memory device 104. The host interface 101, serves as an interface between the solid state disk drive 100 and a host (not shown). In general, a host is defined as a system or subsystem that stores information in the solid state disk drive 100. The host interface 101 receives access requests from the host (e.g. read and write operations). The controller 102 is coupled to the host interface 101, receives commands from the host interface 101 and controls the access operations of the memory device 104. The controller 102 may comprise an error checking and correcting (ECC) engine 105 to provide error checking and correcting for the data stored in the memory device 104.
  • The buffer 103 stores data, including the data transferred from the host interface 101 via the controller 102 during a write operation, prior to transferring the data to the memory device 104. Also, during a read operation, the buffer 103 temporarily stores data from the memory device 104 via the controller 102 prior to transferring the data to the host interface 101. According to an embodiment of the invention, the buffer 103 is a random access memory (RAM), such as a dynamic random access memory (DRAM). The memory device 104 may comprise a plurality of memory blocks each with a plurality of memory cells, wherein each memory cell is capable of storing one or more bits. In a preferred embodiment, the memory device may also be configured in an array having a plurality of rows and/or columns of memory modules.
  • FIG. 2 shows a solid state disk drive configured according to another embodiment of the invention. As shown in FIG. 2, the memory device 204 may comprise a plurality of memory modules, wherein each memory module may be regarded as a memory channel and comprises a plurality of memory blocks. Each memory block may also comprise a plurality of memory cells capable of storing one or more bits of data per cell. However, it should be noted that no specific arrangement of memory cells, memory blocks and memory modules are required to practice the present invention.
  • The memory devices 104 and 204 may be multi level cell (MLC) flash memories capable of storing more than a single bit of data per cell. According to an embodiment of the invention, in order to maximize the limited operating lifespan of the MLC memory devices (such as 104 or 204), the memory cells of the MLC memory device may further be transformed into a single level cell (SLC)-like memory cell. As an example, the controller 102 may transform a memory block into an SLC-like memory block when the controller 102 determines that the operating lifespan of the memory block, when being operated in an MLC manner, is about to expire or a failure probability thereof exceeds a predetermined threshold.
  • FIG. 3 shows a flow chart of the memory management method for a write operation according to an embodiment of the invention. After a write operation of at least one memory block of the MLC flash memory device 104 (Step S201), the processor 102 may obtain an erase count of the corresponding memory block and determine whether the erase count of the memory block has reached a predetermined erase count threshold THEC (Step S202). The erase count may be maintained by the processor 102, wherein the processor 102 records the amount of times of the erase operation of the corresponding memory block. When the erase count does not reach the predetermined threshold THEC, the processor 102 may further determine whether the write operation of the corresponding memory block has failed (Step S203). According to an embodiment of the invention, the write operation may be determined as a failed operation when, for example, the data read from the corresponding memory block is different from the original data desired to be stored.
  • According to the embodiment of the invention, when the processor 102 detects that the erase count of the memory block has reached a predetermined erase count threshold THEC or the write operation of the corresponding memory block has failed, the processor 102 may determine that a failure probability of the corresponding memory block is higher than the predetermined threshold. In other words, the memory block may soon become a defective block. The processor 102 next checks whether the corresponding memory block can be transformed into an SLC-like memory block (Step S204). The information may be stored in the header or redundant section of the memory block. If the memory block can be transformed into and/or accessed as an SLC-like memory block, in order to maximize the operating lifespan of the MLC memory block, the memory block is transformed into an SLC-like memory block so as to be accessed in an SLC manner (Step S205). As an example, the memory block may be marked as an SLC-like memory block in the header or redundant section of the memory block as previously described. Meanwhile, if the memory block can not be transformed into an SLC-like memory block (for example, the memory block is already an SLC-like memory block, or is designed not to be transformed into an SLC-like memory block, or others), the processor 102 may mark the memory block as a defective block (Step S206) so that the memory block may not be further programmed or accessed anymore to avoid undesired errors. It should be noted that for clear illustration of the invention concept, only the steps involved by the proposed method are illustrated in FIG. 3. Also, the invention is not limited to only the steps involved by the proposed method. For persons with ordinary skill in the art, knowledge of how to derive steps, not presented, for accessing a memory device is reasonably assumed. Thus, various alterations and modifications, without departing from the scope and spirit of the invention, may be applied. The scope of the present invention shall be defined and protected by the following claims and their equivalents.
  • FIG. 4 shows a flow chart of the memory management method for a read operation according to an embodiment of the invention. After a read operation of at least one memory block of the MLC flash memory device 104 (Step S301), the processor 102 may determine whether the read operation of the corresponding memory block has failed (Step S302). According to an embodiment of the invention, the read operation may be determined as a failed operation when, for example, the ECC engine 105 is unable to decode the data stored in the memory block. When the read operation is not a failed operation, the processor 102 may further determine whether a bit error rate (BER) of the memory block has exceeded a predetermined BER threshold THBER (Step S303). According to an embodiment of the invention, the BER of the memory block may be obtained, for example, according to the amount of error bits that are detected by the ECC engine 105.
  • According to the embodiment of the invention, when the processor 102 detects that the read operation of the corresponding memory block has failed or the BER of the memory block has exceeded a predetermined BER threshold THBER, the processor 102 may determine that a failure probability of the corresponding memory block is higher than the predetermined threshold. In other words, the memory block may soon become a defective block. The processor 102 next checks whether the corresponding memory block can be transformed into an SLC-like memory block (Step S304). The information may be, as previously described, stored in the header or redundant section of the memory block. If the memory block can be transformed into and/or accessed as an SLC-like memory block, in order to maximize the operating lifespan of the MLC memory block, the memory block is transformed into an SLC-like memory block so as to be accessed in an SLC manner (Step S305). As an example, the memory block may be marked as an SLC-like memory block in the header or redundant section of the memory block as previously described. Meanwhile, if the memory block can not be transformed into an SLC-like memory block (for example, the memory block is already an SLC-like memory block, or is designed not to be transformed into an SLC-like memory block, or others), the processor 102 may mark the memory block as a defective block (Step S306) so that the memory block may not be further programmed or accessed to avoid undesired errors. It should be noted that for clear illustration of the invention concept, only the steps involved by the proposed method are illustrated in FIG. 4. Also, the invention is not limited to only the steps involved by the proposed method. For persons with ordinary skill in the art, knowledge of how to derive steps, not presented, for accessing a memory device is reasonably assumed. Thus, various alterations and modifications, without departing from the scope and spirit of the invention, may be applied. The scope of the present invention shall be defined and protected by the following claims and their equivalents.
  • FIG. 5 shows a flow chart of a memory management method according to another embodiment of the invention. After receiving desired data in accordance with a write operation of the memory device 104 (Step S401), the controller 102 estimates a failure probability of at least one memory block to be written corresponding to the write operation (Step S402). According to an embodiment of the invention, the failure probability may be estimated according to the amount of erase operations performed, a read failure rate, a write failure rate and/or a bit error rate of the corresponding memory block. It is noted that the step may also be implemented by checking whether the memory block to be written can be transformed into an SLC-like memory block during a previous access operation, such as in the Steps S204 and S304 shown in FIG. 3 and FIG. 4, and the invention should not be limited thereto. When the estimated failure probability of the memory block has exceeded a predetermined threshold, the controller 102 writes the desired data to the memory cells of the memory block in a single level cell (SLC) manner (Step S403). According to an embodiment of the invention, the corresponding memory block is written in an SLC manner by storing one bit per memory cell.
  • For an MLC flash memory device, each memory cell may be associated with a plurality of pages. As an example, each memory cell may be associated with a pair of pages, including a first page belonging to a page group A and a second page belonging to a page group B. According to a predetermined rule, a program speed of pages belonging to the page group A is faster than a program speed of pages belonging to the page group B. In the embodiment of the invention, when the controller 102 determines to access the corresponding memory block in an SLC manner, only one page corresponding to each memory cell is written. As an example, the data may be written to the first page belonging to the page group A with a faster program speed. According to another predetermined rule, the pages belonging to different page groups may have some other different page properties. As an example, an error correcting and checking (ECC) capability of the pages belonging to the page group A may be better than an ECC capability of pages belonging to the page group B. In the embodiment of the invention, when the controller 102 determines to access the corresponding memory block in an SLC manner, only one page corresponding to each memory cell is written. As an example, the data may be written to the first page belonging to the page group A with a better ECC capability. According to yet another embodiment of the invention, the data may be only written to the least significant page, which is used to store the least significant bit (LSB) of the memory cell. However, it is noted that in alternate embodiments, the controller 102 may also program the page belonging to the page group B, the most significant page or the most significant bit (MSB) of the memory cell in the SLC manner, and the invention should not be limited thereto.
  • According to the embodiments of the invention, by estimating the failure probability of the memory device in advance, the memory block may be transformed into and performs like an SLC memory block before being marked as a defective MLC block. By accessing the memory block in an SLC manner, both the access/program speed and operating lifespan of the memory block become similar to that of an SLC memory block. Thus, the operating lifespan of the memory device is greatly extended.
  • According to another embodiment of the invention, the SSD drive 100 as shown in FIG. 1 and the SSD drive 200 as shown in FIG. 2 may also be designed as a hybrid memory device, transforming some MLC memory blocks into SLC-like memory blocks as previously described. Conventionally, a predetermined number of SLC memory modules are integrated with the MLC memory modules to accomplish a hybrid memory device. However, the price of the SLC memory module is usually much more expensive than the MLC memory module. In addition, the ECC requirements and access speed of the SLC memory module are also different from that of the MLC memory module, increasing cost and design complexity. Therefore, a novel method for a hybrid memory device based on the concept of, transforming some MLC memory blocks into SLC-like memory blocks as previously described is proposed.
  • According to the embodiments of invention, a predetermined SLC/MLC ratio may be determined in advance and the controller 102 may transform a predetermined number of MLC memory blocks into SLC-like memory blocks in accordance with the predetermined SLC/MLC ratio. Note that different from the conventional hybrid memory device having an unchangeable fixed SLC/MLC ratio that cannot be changed after leaving the factory, the predetermined SLC/MLC ratio in the embodiments of invention may be dynamically adjusted by the controller 102 according to system requirements, user behavior, software environment, the amount of overall memory blocks, and the amount of defective memory blocks, or others. Therefore, the predetermined number (of SLC-like memory blocks) may be flexibly and dynamically adjusted by the controller 102 in accordance with a predetermined rule.
  • According to the embodiments of the invention, the predetermined number may be X, where X is a positive integer. Each memory cell of the MLC memory device may be associated with a plurality of pages. Each page may be grouped into one of N page groups in accordance with different page properties, where N is also a positive integer and the page properties may be the program speed, ECC capability, storage bits (MSB or LSB) as previously described, or others. When the memory block can be transformed into the SLC-like memory block, the processor may write desired data in accordance with a write operation corresponding to the memory block in an SLC manner by only writing data to M page group(s), wherein M is also a positive integer and M N. In other words, according to an embodiment of the invention, the controller 102 may transform X MLC memory blocks into SLC-like memory blocks, wherein the X SLC-like memory blocks may be accessed in the SLC manner. Thus, for each memory cell in the SLC-like memory block, only the pages belonging to the M page group(s) will be programmed and accessed, and the pages belonging to the (N−M) page group(s) are left to be un-programmable and/or un-accessible.
  • As an example, each memory cell of the MLC memory device may be associated with a pair of pages. Therefore, in this example, N=2. The pair of pages may include a first page belonging to a page group A with a program speed faster and/or an ECC capability better than a second page belonging to a page group B. When the MLC memory blocks are transformed into SLC-like memory blocks, only one page per cell may be programmed and accessed. Therefore, in this example, M=1 and either the first page belonging to the page group A or the second page belonging to the page group B may be programmed and accessed after the transformation.
  • According to yet another embodiment of the invention, the multi-channel MLC memory device 204 as shown in FIG. 2 may further be managed to achieve better performance. For an MLC memory device with each memory cell being associated with a plurality of pages, an access speed of the plurality of pages may be different. As an example, each memory cell may be associated with a pair of pages, including a first page belonging to a page group A and a second page belonging to a page group B. According to different page properties, a program speed of pages belonging to the page group A may be faster than a program speed of pages belonging to the page group B. In order to achieve better performance when accessing a multi-channel MLC memory device, the group of pages is preferably controlled for each access operation.
  • FIG. 6 shows a flow chart of a memory management method according to another embodiment of the invention. First, the controller 102 may group each page into one of a plurality of page groups in accordance with different page properties. According to the embodiments of the invention, the page properties may comprise a program speed, an ECC capability, or others. Next, upon receiving at least one program command to write desired data to the multi-channel MLC memory device (Step S602), the controller 102 may allocate a predetermined number of empty pages each belonging to different memory modules in accordance with the program command (Step S603). According to the embodiment of invention, the controller 102 may maintain an empty page list comprising information (for example, the physical address) about the pages that have not been written with data, and the controller may allocate the empty pages for this program operation according to the empty page list. Note that according to the embodiment of the invention, the controller 102 may collect the empty pages belonging to a same page group from the empty page list, and allocate those empty pages for the program operation. The reason to collect the empty pages belonging to a same page group is to achieve same access times for each channel during each access operation (which will be described in more detail in the following paragraphs). Finally, the controller may write the desired data into the empty pages for the program operation (Step S604).
  • FIG. 7 shows a timing diagram for writing desired data in a memory cell of each memory channel in accordance with an embodiment of the invention. For example, in the embodiment of invention, the 8-channel MLC memory device comprises a plurality of memory cells each associated with a pair of pages (e.g. a page A and a page B respectively belongs to a page group A and page group B, where the program speed of page group A is faster than that of page group B) to store data. As the example shown in FIG. 7, the controller 102 may collect the empty pages belonging to a same page group from the empty page list, and allocated those empty pages for one program operation. The desired data are written to page A of all of the 8-channels during the first write operation. Therefore, the first write operation may be quickly finished within the time period T1. From time period T2 to T4, the controller 102 further writes another desired data to page B, which has a slower program speed than page A, and therefore the time required for the second write operation is longer than the first write operation.
  • Note that in the conventional method of random collection of the empty pages, the collected empty pages for one write operation may belong to different page groups (for example, some empty pages may belong to page group A some empty pages may belong to page group B) and have different page properties (for example, different program speeds). Therefore, the overall operation time for each write operation can not be less than the time required for writing the page belonging to page B because even if the write operation in the channels for writing the empty pages belong to page group A have finished, the overall write operation cannot be finished until the write operation in the channels for writing the empty pages belong to page group B have finished. Therefore, comparing with the conventional method of random collection of the empty pages, the proposed method can prevent the write operation (for example, the first write operation shown in FIG. 7) from being delayed by the waiting time for finish the access process of page B. Thus the overall operation time is greatly reduced.
  • FIG. 8 shows a timing diagram for writing desired data in a memory cell of a portion of memory channels in accordance with another embodiment of the invention. In this embodiment, not all of the channels are active. Therefore, only a portion of memory channels are programmed. Similar to the embodiment shown in FIG. 7, since the controller 102 has collected the empty pages of the active channels belonging to a same page group from the empty page list, and allocated those empty pages for the active channels, the pages belonging to the same group of the active channels may be programmed in one program operation (such as a single write operation). Therefore, overall operation time is greatly reduced.
  • FIG. 9 shows a timing diagram for accessing the memory channels in accordance with another embodiment of the invention. Generally, the time required by a write operation is about several times that of a read operation. However, in some embodiments, when the host requests a write operation and then immediately requests a read operation, the controller 102 may merge these two operations together in a same access operation. According to the embodiments of the invention, the controller 102 is capable of collecting the empty pages belonging to a same page group from the empty page list for the channels to be written, and allocating those empty pages for the channels. Therefore, for an access operation, the pages belonging to the same group may be simultaneously written, and the overall operation time may be greatly reduced. For a example shown in the FIG. 9, the pages being written in the first write operation (within the time period T1) and the second write operation (during the time period from T2 to T4) are respectively belong to individual page group (e.g. page group A and page group B, respectively), thus the proposed method can prevent the first write operation from being delayed by the waiting time for finish the access process of page B. In other words, in either a write operation or a merged access operation for reading data and writing data to the empty page in different channels at the same time, when the collected empty pages belong to the same page group, better performance is achieved because in that write operation or merged access operation, the time required for writing data in different channels are substantially the same. Therefore, overall operation time is greatly reduced.
  • While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. Those who are skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of this invention. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents.

Claims (28)

1. A solid state disk drive, comprising:
a multiple level cell (MLC) memory device, comprising a plurality of memory blocks each comprising a plurality of memory cells capable of storing more than a single bit of data per cell; and
a controller, transforming at least one memory block into a single level cell (SLC)-like memory block, and accessing the memory block in an SLC manner.
2. The solid state disk drive as claimed in claim 1, wherein the controller further accesses the memory block, estimates a failure probability of the memory block according to the access operation, and transforms the memory block into an SLC-like memory block when the failure probability thereof exceeds a predetermined threshold.
3. The solid state disk drive as claimed in claim 2, wherein the processor estimates the failure probability of the memory block according to an amount of erase operations performed, a read failure rate, a write failure rate and/or a bit error rate of the memory block.
4. The solid state disk drive as claimed in claim 3, wherein the processor further obtains an erase count representing an amount of erase operations performed of the memory block, determines whether the erase count of the memory block has reached a predetermined erase count threshold, and transforms the memory block into the SLC-like memory block when the erase count of the memory block has reached
5. The solid state disk drive as claimed in claim 3, wherein the processor further determines whether the access operation of the memory block has failed, and transforms the memory block into the SLC-like memory block when the access operation of the memory block has failed.
6. The solid state disk drive as claimed in claim 3, wherein the processor further determines whether a bit error rate (BER) of the memory block corresponding to the access operation exceeds a predetermined BER threshold, and transforms the memory block into the SLC-like memory block when the BER of the memory block exceeds the predetermined BER threshold.
7. The solid state disk drive as claimed in claim 1, wherein when the memory block has been transformed into the SLC-like memory block, the processor further writes desired data in accordance with a write operation corresponding to the memory block in the SLC manner so that each memory cell of the memory block stores a single bit.
8. The solid state disk drive as claimed in claim 1, wherein when the memory block has been transformed into the SLC-like memory block, the processor further writes desired data in accordance with a write operation corresponding to the memory block in the SLC manner by only writing the desired data to least significant bits of the memory cells of the memory block.
9. The solid state disk drive as claimed in claim 1, wherein each memory cell of the MLC memory device is associated with at least a first page and a second page, a program speed of the first page is faster than a program speed of the second page, the processor further writes desired data in accordance with a write operation corresponding to the memory block in the SLC manner by only writing the desired data to the first pages of the memory cells of the memory block.
10. The solid state disk drive as claimed in claim 1, wherein each memory cell of the MLC memory device is associated with at least a first page and a second page, an error correcting and checking (ECC) capability of the first page is more efficient than an ECC capability of the second page, and when the memory block has been transformed into the SLC-like memory block, the processor further writes desired data in accordance with a write operation corresponding to the memory block in the SLC manner by only writing the desired data to the first pages of the memory cells of the memory block.
11. The solid state disk drive as claimed in claim 1, wherein when the memory block has been transformed into the SLC-like memory block, the processor further writes desired data in accordance with a write operation corresponding to the memory block in the SLC manner by only writing the desired data to least significant pages of the memory cells of the memory block.
12. The solid state disk drive as claimed in claim 1, wherein each memory cell of the MLC memory device is associated with a first number of pages, each page is grouped into one of a second number of page groups in accordance with different page properties, and when the memory block has been transformed into the SLC-like memory block, the processor further writes desired data in accordance with a write operation corresponding to the memory block in the SLC manner by only writing a than the second number, and wherein the second number is a positive integer not less than the third number.
13. The solid state disk drive as claimed in claim 1, wherein the controller further transforms a predetermined number of memory blocks into SLC-like memory blocks, and wherein the predetermined number is dynamically adjusted by the controller in accordance with a predetermined rule.
14. A method for managing a memory device comprising a plurality of memory blocks each with a plurality of memory cells capable of storing more than a single bit of data per cell comprising:
receiving desired data in accordance with a write operation of the memory device;
estimating a failure probability of at least one memory block to be written corresponding to the write operation; and
writing the desired data to the memory cells of the memory block in a single level cell (SLC) manner when the estimated failure probability thereof exceeds a predetermined threshold.
15. The method as claimed in claim 14, further comprising:
transforming a predetermined number of memory blocks into SLC-like memory blocks; and
accessing the predetermined number of memory blocks in the SLC manner,
wherein the predetermined number is adjusted in accordance with a predetermined rule.
16. The method as claimed in claim 14, wherein each of the written memory cells stores a single bit.
17. The method as claimed in claim 14, wherein the desired data is only written to least significant bits of the memory cells.
18. The method as claimed in claim 14, wherein each memory cell is associated with a plurality of pages, including at least a first page and a second page, a program speed of the first page is faster than a program speed of the second page, and the desired data is only written to the first pages of the memory cells.
19. The method as claimed in claim 14, wherein each memory cell is associated with a plurality of pages, including at least a first page and a second page, an error correcting and checking (ECC) capability of the first page is more efficient than an ECC capability of the second page, and the desired data is only written to the first pages of the memory cells.
20. The method as claimed in claim 14, wherein the desired data is only written to least significant pages of the memory cells.
21. The method as claimed in claim 14, wherein the failure probability is estimated according to an amount of erase operations performed, a read failure rate, a
22. The method as claimed in claim 14, further comprising:
determining whether an erase count of the memory block has reached a predetermined erase count threshold; and
writing the desired data to the memory cells of the memory block in the SLC manner when the erase count of the memory block has reached the predetermined erase count threshold.
23. The method as claimed in claim 14, further comprising:
determining whether a previous write operation or a previous read operation of the memory block has failed; and
writing the desired data to the memory cells of the memory block in the SLC manner when the previous write operation or the previous read operation has failed.
24. The method as claimed in claim 14, further comprising:
determining whether a bit error rate (BER) of the memory block has exceeded a predetermined BER threshold; and
writing the desired data to the memory cells of the memory block in the SLC manner when the BER exceeds the predetermined BER threshold.
25. A solid state disk drive, comprising:
a multi-channel multiple level cell (MLC) memory device, comprising a plurality of memory modules each comprising a plurality of memory cells capable of storing more than a single bit of data per cell therein, wherein each memory cell is associated with a plurality of pages, and each page is grouped into one of a plurality of page groups in accordance with different page properties; and
a controller, receiving at least one program command from a host to write desired data to the multi-channel MLC memory device, allocating a predetermined number of empty pages each belonging to different memory modules in accordance with the program command, and writing the desired data in the empty pages, wherein the empty pages allocated by the controller for an access operation belongs to the same page group.
26. The solid state disk drive as claimed in claim 25, wherein the page property is a program speed.
27. The solid state disk drive as claimed in claim 25, wherein the page property is an error correcting and checking (ECC) capability.
28. A method for managing a multi-channel memory device comprising a plurality of memory modules each with a plurality of memory cells capable of storing more than a single bit of data per cell therein, wherein each memory cell is associated with a plurality of pages, comprising:
grouping each page into one of a plurality of page groups in accordance with different page properties;
receiving at least one program command to write desired data to the multi-channel MLC memory device;
allocating a predetermined number of empty pages each belonging to different memory modules in accordance with the program command; and
writing the desired data in the empty pages,
wherein the empty pages allocated by the controller for an access operation belongs to the same page group.
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