TWI769100B - Method for managing flash memory module and associated flash memory controller and electronic device - Google Patents

Abstract

The present invention provides a flash memory controller, wherein the flash memory controller is arranged to access a flash memory module, and the flash memory controller includes a ROM, a microprocessor and a timer. The ROM stores a program code, the microprocessor is configured to execute the program code to control the access of the flash memory module, and the timer is used to generate time information. In the operations of the flash memory controller, the microprocessor refers to the time information to perform dummy read operations upon at least a portion of the blocks, wherein the dummy read operations are not triggered by read commands from a host device.

Description

Method for managing a flash memory module and associated flash memory controller and power supply sub device

The present invention relates to a flash memory controller.

With the evolution of flash memory technology, the memory cells in the flash memory chip are changed from a planar arrangement to a multi-layer stacking mode, so that a single chip can contain more memory cells, so as to improve the flash memory chip. capacity. However, the above-mentioned 3D flash memory will encounter some problems in reading quality. For example, if the data in a block has not been read for a long time, the quality of the data in the block will be fast. Deterioration, which makes it difficult to decode the data of the subsequent block, or even cannot be read correctly. Therefore, how to propose an efficient management method to avoid the problem of data preservation is an important technical direction.

Therefore, one of the objectives of the present invention is to provide a method for managing a flash memory, which can effectively avoid the deterioration of the data in the above-mentioned blocks due to the long-term non-reading, so as to solve the problems in the prior art.

In one embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller includes a unique Read memory, a microprocessor and a timer. The ROM system is used to store a code, the microprocessor is used to execute the code to control access to the flash memory module, and the timer is used to generate time information. In the operation of the flash memory controller, the microprocessor performs a redundant read operation on at least a part of the plurality of blocks according to the time information generated by the timer, wherein the Redundant read operations are not triggered by a read command from a master.

In another embodiment of the present invention, a method for managing a flash memory module is disclosed, wherein the flash memory module includes a plurality of flash memory chips, and each flash memory chip includes A plurality of blocks are formed, each block includes a plurality of data pages, and the method includes: using a timer to generate a time information; and according to the time information generated by the timer, to the plurality of areas At least a portion of the blocks perform a redundant read operation, wherein the redundant read operation is not triggered by a read command from a master device.

In another embodiment of the present invention, an electronic device is disclosed, which includes a flash memory module and a flash memory controller, wherein the flash memory module includes a plurality of flash memories Chip, each flash memory chip includes a plurality of blocks, and each block includes a plurality of data pages. In the operation of the flash memory controller, the flash memory controller performs a redundant read operation on at least a part of the plurality of blocks according to time information generated by a timer, wherein The redundant read operation is not triggered by a read command from a master.

100: Memory Device

110: Flash memory controller

112: Microprocessor

112C: Code

112M: read-only memory

114: Control logic

116: Buffer memory

118: Interface logic

119: Timer

120: Flash memory module

130: Main unit

132: Encoder

134: decoder

N1~NK: pin

200, B1~BN: block

202: floating gate transistor

BL1, BL2, BL3: bit lines

WL0~WL2,WL4~WL6: word lines

L1~L8: Voltage level

Vt1~Vt7: Threshold voltage

400: Block record table

500,600: Block read time record table

800~804: Steps

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a block in a flash memory according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a plurality of write voltage levels and a plurality of threshold voltages in each memory cell of the three-layer memory block.

FIG. 4 is a schematic diagram of a block record table according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a block read time record table according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of a block read time record table according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of an update block read time record table according to an embodiment of the present invention.

FIG. 8 is a flowchart of a method for managing a flash memory module according to an embodiment of the present invention.

FIG. 1 is a schematic diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 110 , and the flash memory controller 110 is used for accessing the flash memory module 120 . According to this embodiment, the flash memory controller 110 includes a microprocessor 112, a read only memory (ROM) 112M, a control logic 114, a buffer memory 116, an interface logic 118, and a Timer 119. The ROM 112M is used to store a code 112C, and the microprocessor 112 is used to execute the code 112C to control access to the flash memory module 120 . The control logic 114 includes an encoder 132 and a decoder 134, wherein the encoder 132 is used to encode the data written into the flash memory module 120 to generate a corresponding check code (or error correction code). code (Error Correction Code, ECC), and the decoder 134 is used for decoding the data read from the flash memory module 120 .

In addition, both the flash memory controller 110 and the flash memory module 120 include a plurality of interconnected pins N1 ˜NK for transmitting data and commands between each other. Since the functions of pins N1~NK can refer to the relevant specifications of the flash memory, the details will not be described here.

In a typical situation, the flash memory module 120 includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks, and the flash memory controller 110 controls the flash memory. The operation of erasing data by the memory module 120 is performed in units of blocks. In addition, a block can record a specific number of data pages, wherein the operation of the flash memory controller 110 to write data to the flash memory module 120 is performed in units of data pages. In this embodiment, the flash memory module 120 is a three-dimensional NAND-type flash memory (3D NAND-type flash) module.

In practice, the flash memory controller 110 that executes the code 112C through the microprocessor 112 can use its own internal components to perform various control operations. For example, the control logic 114 is used to control the flash memory module 120. Access operations (especially access operations to at least one block or at least one data page), use the buffer memory 116 to perform required buffering, and use the interface logic 118 to communicate with a Host Device 130 . The buffer memory 116 is implemented by random access memory (Random Access Memory, RAM). For example, the buffer memory 116 may be a static random access memory (Static RAM, SRAM), but the invention is not limited thereto.

In one embodiment, the memory device 100 may be a portable memory device (eg, a memory card conforming to SD/MMC, CF, MS, XD standards), and the host device 130 is an electronic device that can be connected to the memory device, Such as mobile phones, laptops, desktops...etc. In another embodiment, the memory device 100 may be a solid state drive or conform to the Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications The embedded storage device is arranged in an electronic device, such as a mobile phone, a notebook computer, a desktop computer, and the main device 130 can be a processor of the electronic device.

FIG. 2 is a schematic diagram of a block 200 in the flash memory module 120 according to an embodiment of the present invention, wherein the flash memory module 120 is a three-dimensional NAND type flash memory. As shown in FIG. 2, the block 200 includes a plurality of memory cells (such as the floating thyristor 202 shown in the figure or other charge trap devices), which pass through a plurality of bit lines (the figure only BL1-BL3) and a plurality of word lines (eg, WL0-WL2, WL4-WL6 are shown) are shown to form a three-dimensional NAND-type flash memory structure. In Figure 2, taking the uppermost plane as an example, all the floating thyristors on the word line WL0 constitute at least one data page, and all the floating thyristors on the word line WL1 constitute at least another data page page, and all the floating thyristors of word line WL2 constitute at least one other data page...and so on. In addition, the definition between the word line WL0 and the data page (logical data page) is also different according to the different writing methods of the flash memory. , SLC), all floating gate transistors on the word line WL0 only correspond to a single logical data page; when using the Multi-Level Cell (MLC) method, the word line All floating gate transistors on WL0 correspond to two logical data pages; when using triple-level storage (Triple-Level Cell, TLC) to write, all floating gate transistors on word line WL0 correspond to three and when writing in a quad-level cell (QLC) manner, all the floating gate transistors on the word line WL0 correspond to four logical data pages. Since those skilled in the art should be able to understand the structure of the 3D NAND flash memory and the relationship between word lines and data pages, the relevant details are omitted here.

During the operation of the memory device 100, since a block in the flash memory module 120 is in the state of data being written, if the block has not been read for a long time, the data quality of the block will be reduced. is greatly reduced, thereby causing decoding difficulties for the decoder 134. Therefore, in this embodiment, the micro The processor 112 performs a dummy read operation on at least a part of the blocks in the flash memory module 120 storing data according to the time information generated by the timer 119, so as to avoid the block The data is degraded because it has not been read for a long time. In detail, the above redundant read operation refers to the fact that the microprocessor 112 does not actually obtain the content of the block from the flash memory module 120, and the redundant read operation is not performed by Triggered by a read command from the master device 130 (ie, the microprocessor 112 does not perform a redundant read operation on the block because of a request from the master device 130).

In this embodiment, when the microprocessor 112 performs a redundant read operation on the block, the microprocessor 112 sends a read request to the flash memory module 120, but at this time, the microprocessor 112 will A read enable pin (eg, pin N2 shown in FIG. 1 ) of the flash memory controller 110 is turned off, that is, the flash memory controller 110 cannot The module 120 obtains the requested data. After receiving the read request from the flash memory controller 110, the flash memory module 120 reads one or more data pages of the block, and only temporarily stores the read content. Stored in its own temporary storage area without transferring the read data to the flash memory controller 110 . As described above, by performing redundant read operations on the block, the quality of the data in the block can be prevented from being degraded due to no reading for a long time.

In one embodiment, since the purpose of the redundant read operation is only to prevent the quality of the data in the block from being degraded due to no reading for a long time, the flash memory controller 110 may only request the block to be read One data page is enough to speed up redundant read operations.

In another embodiment, the microprocessor 112 can control/instruct the flash memory module 120 to use a single-level cell (SLC) read mode to perform the redundant read of the block operation, regardless of whether the block is a single-level storage block, a multi-level storage (MLC) block, Either a triple-level cell (TLC) block or a quad-level cell (QLC) block. As an illustration, the block is a three-layer storage block, please refer to the multiple write voltage levels L1-L8 and multiple thresholds of each memory cell in the three-layer storage block shown in FIG. 3. A schematic diagram of the voltages (or read voltages) Vt1 to Vt7. As shown in FIG. 3, each floating gate transistor 202 may be programmed (to have a voltage level L1 (ie (MSB,CSB,LSB)=(1,1,1)), a voltage level L2 (ie (MSB, CSB, LSB) = (1, 1, 0), voltage level L3 (ie (MSB, CSB, LSB) = (1, 0, 0)), voltage level L4 (also That is (MSB,CSB,LSB)=(0,0,0)), the voltage level L5 (ie (MSB,CSB,LSB)=(0,1,0)), the voltage level L6 (ie ( MSB,CSB,LSB)=(0,1,1)), voltage level L7 (ie (MSB,CSB,LSB)=(0,0,1)) or voltage level L8 (ie (MSB) ,CSB,LSB)=(1,0,1)). When the flash memory controller 110 needs to read the least significant bit (LSB) in the floating gate transistor 202, the flash memory controller 110 will Use the threshold voltages Vt1, Vt5 to read the floating thyristor 202, and generate "1" or "0" according to the conduction state of the floating thyristor 202 (whether current is generated), similarly, when the flash memory When the controller 110 needs to read the middle significant bit (CSB) in the floating thyristor 202, the flash memory controller 110 uses the threshold voltages Vt2, Vt4 and Vt6 to read the floating thyristor 202, and according to the floating thyristor 202 The conduction state of the thyristor 202 (whether current is generated) generates a "1" or a "0" for decoding by the decoder 134. Similarly, when the flash memory controller 110 needs to read the floating thyristor When the most significant bit (MSB) in 202 is the most significant bit (MSB), the flash memory controller 110 will use the threshold voltages Vt3 and Vt7 to read the floating thyristor 202, and according to the conduction state of the floating thyristor 202 (whether a current is generated or not) ) to determine whether the most significant bit is "1" or "0" for the decoder 134 to decode.

As shown in FIG. 3, when reading a three-layer storage block, a plurality of threshold voltages Vt1-Vt7 are generally required to read data content. However, when the microprocessor 112 reads the block (three-layer storage block) block) during redundant read operation, only a single threshold voltage is used to read each memory cell, for example, the flash memory module 120 only uses the threshold voltage Vt4 to read each memory cell, and The remaining threshold voltages Vt1-Vt3, Vt5-Vt7 are not used in the redundant read operation.

The timing of the redundant read operation and various embodiments of how the microprocessor 112 selects the blocks that need to perform the redundant read operation are described below.

In the first embodiment, the microprocessor 112 can create a block record table to record which blocks in the flash memory module 120 have stored data. Referring to the schematic diagram of the block record table 400 shown in FIG. 4, if the flash memory module 120 includes a plurality of blocks B1-BN, the microprocessor 112 can write data to the flash memory module when During the process of group 120, the contents of the block record table 400 are updated together, that is, when data is written to a block in the flash memory module 120, the block serial number is written into the block record table 400 (for example, , B1, B2, B12, B13, B14 in the figure), and when a block in the flash memory module 120 is erased or marked as invalid, the corresponding block serial number is recorded from the block record table 400 removed. Therefore, the microprocessor 112 can periodically, for example, every 30 minutes, perform redundant read operations on the blocks recorded in the block record table 400 according to the time information generated by the timer 119 to maintain these The data quality of the block where the data is stored.

In this embodiment, the block record table 400 can be temporarily stored in the buffer memory 116 or an external dynamic random access memory, and the block record table 400 can be stored when the memory device 100 is shut down or needs to release memory space. Write to the flash memory module 120 .

In the second embodiment, the microprocessor 112 can create a block reading time record table to record the blocks that have been read in the flash memory module 120 and the corresponding time information. Referring to the schematic diagram of the block read time record table 500 shown in FIG. 5, assuming that the flash memory module 120 includes a plurality of blocks B1-BN, the microprocessor 112 can 120 when each block is read Time information for the block is recorded (eg, a time stamp obtained by the host device 130 or the timer 119). In one embodiment, the content of the block read time record table 500 is continuously updated, that is, the block read time record table 500 records the last read time point of each block. Therefore, the microprocessor 112 can select the unread data according to the content of the block read time record table 500 periodically, for example, every 30 minutes, when it is idle, or according to the time information generated by the timer 119. Take longer blocks for redundant read operations. For example, assuming that the block read time record table 500 records that blocks B_4 and B_5 are more than 20 minutes away from the last read time point, the microprocessor 112 can prioritize the block B_4 and block B_5 B_5 performs redundant read operations.

In this embodiment, the block read time record table 500 can be temporarily stored in the buffer memory 116 or an external dynamic random access memory, and when the memory device 100 is shut down or the memory space needs to be released, the block The read time record table 500 is written into the flash memory module 120 .

In the third embodiment, the microprocessor 112 can establish a block reading time record table to record the block serial number and corresponding time information in real time when a block is read, and the block reading time The record table can be further updated/organized for subsequent redundant read operations. Referring to the schematic diagram of the block reading time record table 600 shown in FIG. 6, it is assumed that the microprocessor 112 sequentially reads blocks B_123, B_75, B_67, B_123, B_4, B_5, B_67, B_123, the microprocessor 112 simultaneously records the read blocks and the corresponding time information (for example, the time stamp shown in the figure) in sequence in the block read time record table 600. The read operation is performed according to the read request of the host device 130 . Then, the microprocessor 112 may periodically, for example, every 5 minutes, sort out the block read time record table 600 according to the time information generated by the timer 119 to delete duplicate block numbers. For example, referring to FIG. 7, since block B_123 has three read records, the microprocessor 112 can directly delete the first two read records; and block B_67 has two read records, then the microprocessor 112 can directly delete the first two read records. The controller 112 can directly delete the previous read record to generate a sorted block read time record table 600 .

Next, the microprocessor 112 may periodically, for example, every 10 minutes, generate a not to do list according to the block read time record table 600 according to the time information generated by the timer 119 , to list blocks with shorter read times that do not require redundant read operations. For example, assuming that the current time point is 14:40, and the microprocessor 112 sets that blocks that have been read within 15 minutes do not need to perform redundant read operations, then the do not list can include Blocks B5, B67, B123. Next, if the microprocessor 112 needs to operate, the microprocessor 112 can record the blocks in the flash memory module 120 with data storage according to the block record table 400 shown in FIG. 4 and the do not make list. , but does not include the blocks B5, B67, and B123 included in the do-not-do list for redundant read operations.

Finally, after the redundant read operation is completed, the microprocessor 112 directly removes the block for which the redundant read operation is performed from the block read time record table 600 . The block read time record table 600 can directly delete the records of blocks B_75 and B4, that is, it is not necessary to record the block serial numbers and corresponding time information for redundant read operations.

It should be noted that the above-mentioned time points of the redundant read operation and the three embodiments of how the microprocessor 112 selects the blocks that need to perform the redundant read operation are only for illustrative purposes, as long as the microprocessor 112 can establish the correlation. The table is used to determine which blocks need to perform redundant read operations. The content of the table can be expressed in different ways according to the design of the engineer, and the changes in the relevant design should belong to the scope of the present invention.

FIG. 8 is a method of managing a flash memory module according to an embodiment of the present invention flow chart. With reference to the content described in the above embodiments, the flow is as follows.

Step 800: The process starts.

Step 802: Use a timer to generate time information.

Step 804: Perform a redundant read operation on at least a part of the blocks according to the time information generated by the timer, wherein the redundant read operation is not read by a master device triggered by the command.

Briefly summarizing the present invention, in the flash memory controller of the present invention, by actively detecting the read status of the block, and actively performing redundant read operations on the blocks that have not been read for a period of time, it is possible to It can effectively avoid the deterioration of the data in the block due to the long-term non-reading, so as to improve the storage quality and the reading efficiency.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: Memory Device

110: Flash memory controller

112: Microprocessor

112C: Code

112M: read-only memory

114: Control logic

116: Buffer memory

118: Interface logic

119: Timer

120: Flash memory module

130: Main unit

132: Encoder

134: decoder

N1~NK: pin

Claims (6)

A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module includes a plurality of flash memory chips, each flash memory The memory chip includes a plurality of blocks, each block includes a plurality of data pages, and the flash memory controller includes: a read-only memory for storing a program code; a microprocessor for to execute the code to control access to the flash memory module; and a timer to generate time information; wherein the microprocessor generates the time information according to the timer to A redundant read operation is performed on at least a part of the plurality of blocks, wherein the redundant read operation is not triggered by a read command of a master device; wherein the flash memory controller includes a buffer memory the buffer memory stores a block record table, wherein the block record table only records the block serial number of the block in which the data is stored in the plurality of blocks; and the microprocessor refers to the block record table The at least a part of the block is selected as the block with the stored data. The flash memory controller as described in claim 1, wherein the microprocessor periodically performs the redundant read operation on the at least a part of the blocks according to the time information generated by the timer . A method for managing a flash memory module, wherein the flash memory module includes a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, and each block includes a plurality of a data page, and the method includes: using a timer to generate a time information; Referring to a block record table, which only records the block serial numbers of the blocks in which the data is stored in the plurality of blocks, so as to select the blocks in which the data is stored from the plurality of blocks; and according to the timer The generated time information is used to perform a redundant read operation on the selected block storing data, wherein the redundant read operation is not triggered by a read command of a master device. The method of claim 3, wherein the step of performing the redundant read operation on the selected block storing data according to the time information generated by the timer comprises: according to the timing The time information generated by the processor is used to periodically perform the redundant read operation on the selected block with stored data. An electronic device, comprising: a flash memory module, wherein the flash memory module includes a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each area The block includes a plurality of data pages; and a flash memory controller for accessing the flash memory module; wherein the flash memory controller according to time information generated by a timer at least a part of the blocks perform a redundant read operation, wherein the redundant read operation is not triggered by a read command of a master device; wherein the flash memory controller includes a buffer memory, The buffer memory stores a block record table, wherein the block record table only records the block serial number of the block in which the data is stored in the plurality of blocks; and the flash memory controller refers to the block record form to select The block storing the data is used as the at least part of the block. The electronic device of claim 5, wherein the flash memory controller periodically performs the redundant read operation on the at least a part of the blocks according to the time information generated by the timer.

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