TW202234253A - Method for managing flash memory module and associated flash memory controller and electronic device - Google Patents

Abstract

The present invention provides a flash memory controller, wherein the flash memory controller is arranged to access a flash memory module, and the flash memory controller includes a ROM, a microprocessor and a time management circuit. The ROM stores a program code, the microprocessor is configured to execute the program code to control the access of the flash memory module, and the time management circuit is configured to generate current time information. In the operations of the flash memory controller, when the microprocessor writes data into last pages of a specific block of the flash memory module, the microprocessor writes the time information generated by the time management circuit into one of the last pages of the specific block.

Description

Method for managing flash memory module and related flash memory controller and electronic device

The present invention relates to a flash memory controller.

With the evolution of flash memory technology, the memory cells in the flash memory chip are changed from a planar arrangement to a multi-layer stacking mode, so that a single chip can contain more memory cells, so as to improve the flash memory chip. capacity. However, the above-mentioned 3D flash memory will encounter the problem of data retention, that is, when the data is written into the flash memory chip, the data quality will be greatly degraded, and may prevent the data from being read correctly. Therefore, how to propose an efficient management method to avoid the problem of data preservation is an important technical direction.

Therefore, the present invention proposes a method for managing a flash memory, which can efficiently and quickly find out the block where the data saving problem is about to occur and perform appropriate processing, so as to solve the problem in the prior art.

In one embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory module includes a plurality of a flash memory chip, each flash memory chip includes a plurality of blocks, each block includes a plurality of data pages, and the flash memory controller includes a ROM, a microprocessor and a time management circuit. The read-only memory system is used to store a code, the microprocessor is used to execute the code to control access to the flash memory module, and the time management circuit is used to generate current time information. In the operation of the flash memory controller, when the microprocessor writes data to the last data pages of a particular block, the microprocessor writes the time information generated by the time management circuit to one of the last data pages.

In another embodiment of the present invention, a method for managing a flash memory module is disclosed, wherein the flash memory module includes a plurality of flash memory chips, and each flash memory chip includes A plurality of blocks are formed, each block includes a plurality of data pages, and the method includes the following steps: generating a current time information; and when the data is written to a specific block of the flash memory module When the last plurality of data pages are generated, the time information generated by the time management circuit is written into one of the last plurality of data pages.

In another embodiment of the present invention, an electronic device is disclosed, which includes a flash memory module and a flash memory controller. The flash memory module includes a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, and each block includes a plurality of data pages; and the flash memory controller system for accessing the flash memory module, wherein the flash memory controller generates current time information; and when the flash memory controller writes data to a flash memory module In the last data pages of a specific block, the flash memory controller writes the time information generated by the time management circuit into one of the last data pages.

FIG. 1 is a schematic diagram of a memory device 100 according to a first embodiment of the present invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 110 , and the flash memory controller 110 is used for accessing the flash memory module 120 . In this embodiment, the flash memory controller 110 includes a microprocessor 112, a read only memory (ROM) 112M, a control logic 114, a buffer memory 116, an interface logic 118, and A time management circuit 119 . The ROM 112M is used to store a code 112C, and the microprocessor 112 is used to execute the code 112C to control access to the flash memory module 120 . The control logic 114 includes an encoder 132 and a decoder 134, wherein the encoder 132 is used to encode the data written into the flash memory module 120 to generate a corresponding check code (or error correction code). code (Error Correction Code, ECC), and the decoder 134 is used for decoding the data read from the flash memory module 120 .

Typically, the flash memory module 120 includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks, and the flash memory controller 110 controls the flash memory. The operation of erasing data by the memory module 120 is performed in units of blocks. In addition, a block can record a specific number of data pages, wherein the operation of the flash memory controller 110 to write data to the flash memory module 120 is performed in units of data pages. In this embodiment, the flash memory module 120 is a three-dimensional NAND-type flash memory (3D NAND-type flash) module.

In practice, the flash memory controller 110 that executes the code 112C through the microprocessor 112 can use its own internal components to perform various control operations. For example, the control logic 114 is used to control the flash memory module 120. Access operations (especially access operations to at least one block or at least one data page), use the buffer memory 116 to perform required buffering, and use the interface logic 118 to communicate with a Host Device 130 . In addition, the time management circuit 119 is connected to a specific pin N2 of the host device through a specific pin N1 of the flash memory controller. The buffer memory 116 is implemented by a random access memory (Random Access Memory, RAM). For example, the buffer memory 116 may be a static random access memory (Static RAM, SRAM), but the invention is not limited thereto.

In one embodiment, the memory device 100 may be a portable memory device (eg, a memory card conforming to SD/MMC, CF, MS, XD standards), and the host device 130 is an electronic device that can be connected to the memory device, Such as mobile phones, laptops, desktops...etc. In another embodiment, the memory device 100 may be a solid state drive or an embedded storage conforming to Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications The device is installed in an electronic device, such as a mobile phone, a notebook computer, a desktop computer, and the main device 130 may be a processor of the electronic device.

FIG. 2 is a schematic diagram of a block 200 in the flash memory module 120 according to an embodiment of the present invention, wherein the flash memory module 120 is a three-dimensional NAND type flash memory. As shown in FIG. 2, the block 200 includes a plurality of memory cells (such as the floating thyristor 202 shown in the figure or other charge trap devices), which pass through a plurality of bit lines (the figure only BL1-BL3) and a plurality of word lines (eg, WL0-WL2, WL4-WL6 are shown) are shown to form a three-dimensional NAND-type flash memory structure. In Figure 2, taking the uppermost plane as an example, all the floating thyristors on the word line WL0 constitute at least one data page, and all the floating thyristors on the word line WL1 constitute at least another data page page, and all the floating thyristors of word line WL2 constitute at least one other data page . . . and so on. In addition, the definition between the word line WL0 and the data page (logical data page) is also different according to the different writing methods of the flash memory. , SLC), all floating thyristors on the word line WL0 only correspond to a single logical data page; when using the Multi-Level Cell (MLC) method, the word All floating gate transistors on line WL0 correspond to two logical data pages; when using triple-level storage (Triple-Level Cell, TLC) to write, all floating gate transistors on word line WL0 correspond to three logical data pages; and when writing in a Quad-Level Cell (QLC) manner, all floating gate transistors on word line WL0 correspond to four logical data pages. Since those skilled in the art should be able to understand the structure of the 3D NAND flash memory and the relationship between word lines and data pages, the relevant details are omitted here.

The structure shown in FIG. 2 is only a simple description of the basic structure of the 3D flash memory, and in actual manufacturing, more layers are stacked to achieve higher density storage capacity. Since the three-dimensional flash memory adopts the stacking structure shown in Figure 2, the data will encounter a serious problem of data retention in storage, that is, after the data is written to the block 200, a period Over time, the memory cells in it will encounter data writing level changes, threshold voltage shifts, etc. data quality problems, so that the data in the block 200 may encounter decoding difficulties during subsequent reading, or Even the decoding could not be successfully completed, resulting in data loss. Therefore, the present embodiment provides a management method for the flash memory module 120, which can set a time management circuit 119 in the flash memory controller 110 to efficiently record the time information of each block, For quality judgment to perform subsequent appropriate processing, the specific operation content is described in detail as follows.

FIG. 3 is a schematic diagram illustrating that the block 200 includes a plurality of data pages P0 to PN. When the flash memory controller 110 needs data from the host device 130, or data from other blocks in the flash memory module 120, and/or data temporarily stored by the flash memory controller 110 itself When writing to the block 200, the flash memory controller 110 sequentially writes the data from the first data page P0 to the last data page PN. In this embodiment, when the flash memory controller 110 prepares to write data to the last data page PN, or prepares to write data to the last multiple data pages, the time management circuit 119 uses a specific pin N1 sends a request command to the main device 130 to request the main device 130 to provide the current time information, and since the main device 130 itself is connected to the operating system, it can provide the current time information (for example, month, day, minute, information such as seconds) 302 to the time management circuit 119. After the time management circuit 119 receives the time information 302, it will provide the time information 302 to the microprocessor 112 for the microprocessor 112 to process it through the encoder 132 and write it into the data page PN together with other data .

Since the last data page PN of the block 200 records an absolute time (eg, a time stamp), when the subsequent flash memory controller 110 and the flash memory module 120 are in an idle state, the flash memory The bank controller 110 can scan each block, and obtain the time point when the write operation of the block is completed by directly reading the last data page PN of each block. Afterwards, the flash memory controller 110 uses the time management circuit 119 to obtain the current time from the host device 130 in real time to determine how long the data in each block has been stored (that is, each block is completed The time gap between the write operation and the current block scan). In this embodiment, if the storage time of the data in a block is higher than a threshold (eg, one month or several weeks after the block is written), the flash memory controller 110 can determine that the block may encounter data storage problems, therefore, the block is put into the program of garbage collection (garbage collection) operation, and the valid data in the block is at a later appropriate time point. Move to another block and erase the contents of that block.

As described above, through the management method of this embodiment, the flash memory controller 110 can simply and efficiently know how long the data in each block has been stored, so as to determine whether each block is about to be Encountered data preservation problems and made appropriate follow-up actions.

In another embodiment of the present invention, in addition to writing time information in the last data page PN of each block, the microprocessor 112 establishes a time information comparison table 400 as shown in FIG. Records the time information written in each block (for example, block 1, block 2, block 3, block 4 in FIG. 4) (for example, time information 1, time information 2, time in FIG. 4) Information 3, time information 4). In this embodiment, the time information comparison table 400 can be temporarily stored in an external dynamic random access memory or in the buffer memory 116 inside the flash memory controller 110 for the flash memory controller 110 to Without reading each block of the flash memory module 120 , it is possible to quickly determine how long the data in each block has been stored, and perform appropriate follow-up processing.

In addition, when the flash memory controller 110 is about to be shut down or the memory needs to free up space, the time information comparison table 400 can be written to an appropriate address in the flash memory module 120 to avoid data loss.

In another embodiment, in order to use the memory space more efficiently, the content of the time information comparison table 400 can be integrated into other comparison tables/mapping tables, such as a logical address to physical address mapping table (logical address). to physical address mapping table) or physical address to logical address mapping table (physical address to logical address mapping table).

FIG. 5 is a schematic diagram of a memory device 500 according to a second embodiment of the present invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 510 , and the flash memory controller 510 is used for accessing the flash memory module 120 . In this embodiment, the flash memory controller 510 includes a microprocessor 112, a ROM 112M, a control logic 114, a buffer memory 116, an interface logic 118, a timer 517, and a time Management circuit 519. The ROM 112M stores a code 112C, and the control logic 114 includes an encoder 132 and a decoder 134 . Elements with the same numbers in FIG. 5 as in FIG. 1 have similar operations, so the details thereof will not be repeated, so the following description is only for the timer 517 and the part of the time management circuit 519 .

In the present embodiment, the time management circuit 519 may be integrated into the microprocessor 112, and when the flash memory controller 510 is powered on (ie, the memory device 500 is powered on and the flash memory controller 510 begins to communicate with When the main device 130 is connected), the time management circuit 519 will receive the initial time from the main device 130 (that is, the time point when the flash memory controller 510 is powered on), and since the main device 130 itself is connected to the operating system, it can provide The initial time (eg, month, day, minute, second, etc. information) is sent to the time management circuit 519 . After that, the timer 517 starts to continuously count the elapsed time after the flash memory controller 510 is powered on.

Also referring to the block 200 shown in FIG. 3, when the flash memory controller 510 needs data from the host device 130, or data from other blocks in the flash memory module 120, and/or When the data temporarily stored by the flash memory controller 510 is written to the block 200, the flash memory controller 510 will sequentially write the data from the first data page P0 to the last one. Information page PN. In this embodiment, when the flash memory controller 510 prepares to write data to the last data page PN, or prepares to write data to the last multiple data pages, the time management circuit 519 adds the initial time to the The time elapsed after the flash memory controller 510 is powered on is currently calculated by the timer 517 to generate time information. After the time management circuit 119 calculates the time information, it will provide the information to the microprocessor 112 for the microprocessor 112 to write into the data page PN together with other data after being processed by the encoder 132 .

In the embodiment shown in FIG. 5, the time management circuit 519 obtains absolute time information (ie, the above-mentioned initial time) from the host device 130 only when the flash memory controller 510 is powered on, and thereafter It calculates the current absolute time through its own timer 517 .

Since the last data page PN of the block 200 records the absolute time (the absolute time calculated through the content of the initial time timer 517 ), when the subsequent flash memory controller 510 and the flash memory model When the group 120 is in an idle state, the flash memory controller 510 can scan each block and obtain the block by directly reading the last data page PN of each block when the write operation is completed. time point. After that, the time management circuit 519 calculates the current time by adding the initial time and the content of the timer 517 to determine how long the data in each block has been stored (that is, when each block is finished writing The time gap between the input operation and the current block scan). In this embodiment, if the storage time of the data in a block is higher than a threshold (eg, one month or several weeks after the block is written), the flash memory controller 510 can determine that the block may encounter data storage problems, therefore, the block is put into the garbage collection operation program, and the valid data in the block is moved to another at an appropriate subsequent time point. block and erase the block.

As described above, through the management method of this embodiment, the flash memory controller 510 can simply and efficiently know how long the data in each block has been stored, so as to determine whether each block is about to be Encountered data preservation problems and made appropriate follow-up actions.

In the embodiment shown in FIG. 5, the microprocessor 112 can also create a time information comparison table 400 as shown in FIG. 4, or integrate the content of the time information comparison table 400 into other comparison tables/maps In a table, for example, a logical address to physical address mapping table or a physical address to logical address mapping table.

FIG. 6 is a schematic diagram of a memory device 600 according to a third embodiment of the present invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 610 , and the flash memory controller 610 is used for accessing the flash memory module 120 . In this embodiment, the flash memory controller 610 includes a microprocessor 112, a ROM 112M, a control logic 114, a buffer memory 116, an interface logic 118, a timer 617, and a time Management circuit 619. The ROM 112M stores a code 112C, and the control logic 114 includes an encoder 132 and a decoder 134 . Elements with the same numbers in FIG. 6 as in FIG. 1 have similar operations, so the details thereof will not be repeated, so the following description is only for the timer 617 and the part of the time management circuit 619 .

In the present embodiment, the time management circuit 619 may be integrated into the microprocessor 112, and when the flash memory controller 610 is powered on (ie, the memory device 600 is powered on and the flash memory controller 610 begins to communicate with When the host device 130 is connected), the time management circuit 619 obtains a reference time at a suitable time point, and the timer 617 starts to continuously count the elapsed time after the flash memory controller 610 is powered on.

In this embodiment, the time management circuit 619 does not obtain any absolute time information from the host device 130 , but estimates the current time from the content stored in the flash memory module 120 . For example, referring to FIG. 7, if the flash memory controller 610 is powered off at time t0 and the flash memory controller 610 is powered on at time t1, the microprocessor 112 can read Taking the time information 712 stored in the block 710 that completed the last write operation before the time point t0, and then estimating a predicted time for representing the duration of the power-off time (ie, (t1-t0)), Finally, the time information 712 is added to the predicted time to obtain the reference time. In one embodiment, since the flash memory controller 610 itself cannot accurately know the length of the power-off time (ie, (t1-t0)), the flash memory controller 610 can read the block by reading the block. The data content of 710 is obtained, and the prediction time is estimated according to the data quality of block 710, wherein the worse the data quality is, the longer the data storage time is, that is, the longer the power-off time is. For example, the microprocessor 112 can read the data of the block 710 and generate the prediction time according to the bit error rate of the data, wherein the higher the bit error rate is, the longer the prediction time is; The processor 112 can also read the data of the block 710 and determine the voltage distribution of the memory cells in the block 710 to generate the predicted time, wherein the more dispersed the voltage distribution, the longer the estimated predicted time; or the microprocessor 112 can also read the data of the block 710 and determine the threshold voltage shift degree of the memory cells in the block 710 to generate the prediction time, wherein the higher the threshold voltage offset, the longer the estimated prediction time.

Also referring to the block 200 shown in FIG. 3, when the flash memory controller 610 needs data from the host device 130, or data from other blocks in the flash memory module 120, and/or When the data temporarily stored by the flash memory controller 610 itself is written to the block 200, the flash memory controller 610 will sequentially write the data from the first data page P0 to the last one. Information page PN. In this embodiment, when the flash memory controller 610 prepares to write data to the last data page PN, or prepares to write data to the last multiple data pages, the time management circuit 619 adds the reference time to the The time elapsed after the flash memory controller 610 is powered on is calculated by the timer 617 to generate time information. After the time management circuit 619 calculates the time information, it will provide the information to the microprocessor 612 for the microprocessor 112 to write into the data page PN together with other data after being processed by the encoder 132 .

When the subsequent flash memory controller 610 and the flash memory module 120 are in an idle state, the flash memory controller 610 can scan each block and directly read the last block of each block The data page PN is used to obtain the time point of the block when the write operation is completed. After that, the time management circuit 619 calculates the current time by adding the reference time and the content of the timer 617 to determine how long the data in each block has been stored (that is, when each block is finished writing The time gap between the input operation and the current block scan). In this embodiment, if the storage time of the data in a block is higher than a threshold (eg, one month or several weeks after the block is written), the flash memory controller 610 can determine that the block may encounter data storage problems, therefore, the block is put into the garbage collection operation program, and the valid data in the block is moved to another block and erase the block.

As described above, through the management method of this embodiment, the flash memory controller 610 can simply and efficiently know how long the data in each block has been stored, so as to determine whether each block is about to be Encountered data preservation problems and made appropriate follow-up actions.

FIG. 8 is a flowchart of a method for managing a flash memory module according to an embodiment of the present invention. With reference to the content described in the above embodiments, the flow is as follows.

Step 800: The process starts.

Step 802: Generate current time information.

Step 804: When data is written to the last data pages of a specific block of the flash memory module, write the time information to one of the last data pages.

Step 806: Create/update a lookup table/mapping table to store each block and the corresponding time information.

Step 808: Determine the data quality of each block according to the time information of the block, and determine whether to move the data of the block to other blocks accordingly.

To briefly summarize the present invention, in the flash memory controller of the present invention, by recording the time information of each block, it is possible to quickly and efficiently determine whether the data storage time is too long, which may cause data quality problems, and Accordingly, appropriate follow-up operations are performed in advance to avoid the problem of data loss. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100,500,600: Memory Device 110, 510, 610: Flash memory controllers 112: Microprocessor 112C: Code 112M: read-only memory 114: Control logic 116: Buffer memory 118: Interface logic 119,519,619: Time Management Circuits 120: Flash memory module 130: Main unit 132: Encoder 134: decoder N1, N2: specific pins 200,710: Blocks 202: floating gate transistor BL1, BL2, BL3: bit lines WL0~WL2,WL4~WL6: word lines P0, P1, P2, P3, P(N-1), PN: Information page 400: Time information comparison table 517,617: Timer 302,712: Time information 800~808: Steps

FIG. 1 is a schematic diagram of a memory device according to a first embodiment of the present invention. FIG. 2 is a schematic diagram of a block in a flash memory module according to an embodiment of the present invention. Figure 3 is a schematic diagram of blocks and data pages. FIG. 4 is a schematic diagram of a time information comparison table according to an embodiment of the present invention. FIG. 5 is a schematic diagram of a memory device according to a second embodiment of the present invention. FIG. 6 is a schematic diagram of a memory device according to a third embodiment of the present invention. FIG. 7 is a timing diagram of power-off and power-on of the flash memory controller. FIG. 8 is a flowchart of a method for managing a flash memory module according to an embodiment of the present invention.

100: Memory Device

110: Flash memory controller

112: Microprocessor

112C: Code

112M: read-only memory

114: Control logic

116: Buffer memory

118: Interface logic

119: Time Management Circuits

120: Flash memory module

130: Main unit

132: Encoder

134: decoder

N1, N2: specific pins

Claims (6)

A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module includes a plurality of flash memory chips, each flash memory The memory chip includes a plurality of blocks, each block includes a plurality of data pages, and the flash memory controller includes: a ROM, used to store a code; a microprocessor for executing the code to control access to the flash memory module; When the flash memory controller and the flash memory module are in an idle state, the microprocessor scans at least a part of the plurality of blocks, and directly reads the at least one block. The last data page of each block in the partial block is used to obtain the time information of the block when the write operation is completed, so as to judge whether there is a block in the at least part of the block that may encounter data preservation. on the problem. The flash memory controller as described in claim 1, wherein the time information of the block when the writing operation is completed is an absolute time. The flash memory controller as described in item 1 of the claimed scope further includes: a time management circuit, coupled to the microprocessor, for generating a current time information; Wherein the microprocessor calculates a time difference between the time information of each block in the at least a part of blocks and the current time according to a current time generated by the time management circuit, and according to the time difference Determine whether the block may encounter data preservation problems. An electronic device, comprising: a flash memory module, wherein the flash memory module includes a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, and each block includes a plurality of data pages; as well as a flash memory controller for accessing the flash memory module; When the flash memory controller and the flash memory module are in an idle state, the flash memory controller scans at least a part of the plurality of blocks, and directly reads The last data page of each block in the at least a portion of the blocks is used to obtain the time information of the block when the write operation is completed, so as to determine whether any blocks in the at least a portion of the blocks may encounter to the problem of data preservation. The electronic device as described in claim 4, wherein the time information of the block when the writing operation is completed is an absolute time. The electronic device as described in claim 4, wherein the flash memory controller calculates the time of each of the at least a portion of the blocks according to a current time generated by a time management circuit A time gap between the information and the current time, and according to the time gap to determine whether the block may encounter data storage problems.

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