US6995999B2 - Nonvolatile semiconductor memory device and control method thereof - Google Patents

Nonvolatile semiconductor memory device and control method thereof Download PDF

Info

Publication number
US6995999B2
US6995999B2 US10/867,950 US86795004A US6995999B2 US 6995999 B2 US6995999 B2 US 6995999B2 US 86795004 A US86795004 A US 86795004A US 6995999 B2 US6995999 B2 US 6995999B2
Authority
US
United States
Prior art keywords
voltage
pulse
memory cell
programming
variable resistive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US10/867,950
Other languages
English (en)
Other versions
US20040264244A1 (en
Inventor
Hidenori Morimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Assigned to SHARP KABUSHIKI KAISHA reassignment SHARP KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MORIMOTO, HIDENORI
Publication of US20040264244A1 publication Critical patent/US20040264244A1/en
Application granted granted Critical
Publication of US6995999B2 publication Critical patent/US6995999B2/en
Assigned to INTELLECTUAL PROPERTIES I KFT. reassignment INTELLECTUAL PROPERTIES I KFT. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SHARP KABUSHIKI KAISHA
Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTELLECTUAL PROPERTIES I KFT.
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5685—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using storage elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0064—Verifying circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0071—Write using write potential applied to access device gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/009—Write using potential difference applied between cell electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/31—Material having complex metal oxide, e.g. perovskite structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Definitions

  • the present invention relates to a nonvolatile semiconductor memory device having a memory array in which a plurality of memory cells each formed by connecting one end of a variable resistive element for storing information according to a change in electric resistance caused by application of a voltage and a drain of a selection transistor to each other on a semiconductor substrate are arranged in the row direction and the column direction, and a control method thereof. More particularly, the present invention relates to a method of applying a voltage to a memory cell at the time of programming or erasing.
  • a nonvolatile semiconductor memory is becoming more and more important.
  • power consumption of a logic circuit for executing a logic function is dominant but, in a standby state, power consumption of a memory device is dominant.
  • the power consumption in the standby state is becoming more important as the drive time by a battery of a mobile apparatus increases.
  • the nonvolatile semiconductor memory it becomes unnecessary to supply power to the nonvolatile semiconductor memory in the standby state, so that the power consumption can be reduced to the limit.
  • Nonvolatile semiconductor memories include a flash memory, an FeRAM (Ferroelectric Random Access Memory) and the like, and many of them are already practically used. Those nonvolatile semiconductor memories have tradeoffs among high speed, rewrite resistance, power consumption and the like. Research and development for an ideal nonvolatile semiconductor memory satisfying all of required specifications are being conducted. Some nonvolatile semiconductor memories using new materials have been already proposed and an RRAM (Resistance Random Access Memory) is one of promising nonvolatile semiconductor memories. Since the RRAM has high potentials of high speed, large capacity, low power consumption and the like, expectations are placed on the future potential of the RRAM.
  • RRAM Resistance Random Access Memory
  • RRAM Novel Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory
  • IEDM Paper No. 7.5, December, 2002 specifically describes an RRAM in which by applying a voltage pulse to an oxide material containing manganese having a perovskite type crystal structure showing CMR (colossal magnetoresistance) and HTSC (high temperature super conductivity) such as Pr 1-x Ca X MnO 3 (0 ⁇ x ⁇ 1, hereinafter, abbreviated as “PCMO”), the resistance value changes.
  • CMR colossal magnetoresistance
  • HTSC high temperature super conductivity
  • FIG. 13 shows a change in the resistance value when a pulse of 100 nanoseconds of ⁇ 5 V is applied to the PCMO having a thickness of 100 nm.
  • the resistance value changes between 1 k ⁇ and 1 M ⁇ and a large change of three digits in the resistance value occurs reversibly 100 times or more.
  • FIG. 14 in which the vertical axis indicates the resistance value and the horizontal axis indicates the number of application times of a pulse of 4 V and 5 nanoseconds, shows that the resistance value of the variable resistive element changes in an analog manner in accordance with the number of pulse application times.
  • the relation between the current value I and the voltage V is expressed by I ⁇ Exp ( ⁇ V). It indicates that the current-voltage characteristic has very high nonlinearity and a small voltage change causes a large change in the current amount. Consequently, if there are variations in a program threshold voltage which changes from the low resistance state (hereinafter, described as RL) of a variable resistive element to the high resistance state (hereinafter, described as RH) or an erase threshold voltage which changes from the RH to the RL, when the same voltage is applied to the variable resistive element to program or erase data, a very large variation occurs in the amount of current flowing in the variable resistive element, and current consumed in programming or erasing increases.
  • RL program threshold voltage which changes from the low resistance state
  • RH high resistance state
  • an erase threshold voltage which changes from the RH to the RL
  • the present invention has been made in consideration of the problems and its object is to provide a nonvolatile semiconductor memory device and a control method thereof which can realize reliable programming and erasing of data to/from a memory cell while suppressing increase in current consumption at the time of programming or erasing and in which a memory cell includes a variable resistive element for storing information according to a change in electric resistance caused by application of a voltage.
  • the present invention provides a nonvolatile semiconductor memory device comprising at least: a memory array in which a plurality of memory cells are arranged in a row direction and a column direction, each of the memory cells being formed by connecting one end of a variable resistive element for storing information according to a change in electric resistance caused by an electric stress and a drain of a selection transistor to each other on a semiconductor substrate; a word line connected to gates of the selection transistors of the plurality of memory cells in the same row; a source line connected to sources of the selection transistors of the plurality of memory cells in the same row or the same column; a bit line connected to the other ends of the variable resistive elements of the plurality of memory cells in the same column; a control circuit for executing controls of programming, erasing and reading of information to/from the memory cell; a voltage switch circuit for switching among a program voltage, an erase voltage and a read voltage to be applied to the source line and the bit line; and a read circuit for reading information from the memory
  • the present invention also provides a control method of a nonvolatile semiconductor memory device, wherein the nonvolatile semiconductor memory device comprises at least: a memory array in which a plurality of memory cells are arranged in a row direction and a column direction, each of the memory cells being formed by connecting one end of a variable resistive element for storing information according to a change in electric resistance caused by an electric stress and a drain of a selection transistor to each other on a semiconductor substrate; a word line connected to gates of the selection transistors of the plurality of memory cells in the same row; a source line connected to sources of the selection transistors of the plurality of memory cells in the same row or the same column; a bit line connected to the other ends of the variable resistive elements of the plurality of memory cells in the same column; a control circuit for executing controls of programming, erasing and reading of information to/from the memory cell; a voltage switch circuit for switching among a program voltage, an erase voltage and a read voltage to be applied to the source line
  • a voltage pulse of a voltage value adjusted for programming is generated at the time of programming, and a voltage pulse of a voltage value adjusted for erasing is generated at the time of erasing.
  • a voltage value obtained by subtracting a drain-source voltage of the selection transistor from an absolute value of a voltage difference between the program voltage or the erase voltage applied to the bit line and the source line is set to be larger than either a program threshold voltage necessary for programming data to the variable resistive element or an erase threshold voltage necessary for erasing data in the variable resistive element.
  • the voltage value of the voltage pulse is set so that the selection transistor operates in a saturation region at least in a period in the application period of the voltage pulse when the voltage pulse is applied to the gate of the selection transistor of the memory cell to be programmed or erased.
  • the program voltage or the erase voltage to be applied to the bit line and the source line is applied to the bit line or the source line and the word line
  • the voltage pulse to be applied to the word line is applied to the source line or the bit line to which the program voltage or the erase voltage is not applied.
  • FIG. 1 is a block diagram showing a general configuration in an embodiment of a nonvolatile semiconductor memory device according to the present invention
  • FIG. 2 is a cross-sectional view schematically showing the structure of a memory cell used in the nonvolatile semiconductor memory device according to the present invention
  • FIG. 3 is a circuit diagram showing an example of the configuration of a memory array used in the nonvolatile semiconductor memory device according to the present invention
  • FIG. 4 is a circuit diagram showing another example of the configuration of the memory array used in the nonvolatile semiconductor memory device according to the present invention.
  • FIG. 5 is a schematic diagram showing the layout of a main portion of the memory array shown in FIG. 3 ;
  • FIG. 6 is a schematic diagram showing the layout of a main portion of the memory array shown in FIG. 4 ;
  • FIG. 7 is an equivalent circuit diagram for explaining a programming/erasing operation of a memory cell used in the nonvolatile semiconductor memory device according to the present invention.
  • FIG. 8 is an equivalent circuit diagram for explaining a programming/erasing operation of a memory cell used in the nonvolatile semiconductor memory device according to the present invention.
  • FIG. 9 is an equivalent circuit diagram for concretely explaining the programming operation of the memory cell used in the nonvolatile semiconductor memory device according to the present invention.
  • FIG. 10 is a diagram showing dependency on a gate voltage in the programming operation of a memory cell used in the nonvolatile semiconductor memory device according to the present invention.
  • FIG. 11 is an equivalent circuit diagram for concretely explaining the erasing operation of the memory cell used in the nonvolatile semiconductor memory device according to the present invention.
  • FIG. 12 is a diagram showing dependency on the gate voltage in the erasing operation of a memory cell used in the nonvolatile semiconductor memory device according to the present invention.
  • FIG. 13 is a characteristic diagram showing a switching characteristic of a variable resistive element
  • FIG. 14 is a characteristic diagram showing a switching characteristic of the variable resistive element
  • FIG. 15 is a characteristic diagram showing a nonlinear current-voltage characteristic in the low resistance state of the variable resistive element
  • FIG. 16 is a characteristic diagram showing the nonlinear current-voltage characteristic in the high resistance state of the variable resistive element
  • FIG. 17 is a diagram showing the range of multivalue levels in the case of applying the variable resistive element to a multivalue memory cell
  • FIG. 18 is a flowchart showing the programming procedure of a memory cell in an embodiment of a control method of the nonvolatile semiconductor memory device according to the present invention.
  • FIG. 19 is a flowchart showing the erasing procedure of a memory cell in an embodiment of the control method of the nonvolatile semiconductor memory device according to the present invention.
  • FIG. 20 is a block diagram showing a general configuration in another embodiment of the nonvolatile semiconductor memory device according to the present invention.
  • FIG. 21 is a flowchart showing the programming procedure of a memory cell in another embodiment of the control method of the nonvolatile semiconductor memory device according to the present invention.
  • FIG. 22 is a flowchart showing the erasing procedure of a memory cell in another embodiment of the control method of the nonvolatile semiconductor memory device according to the present invention.
  • FIG. 1 is a block diagram of an inventive device 100 .
  • the inventive device 100 has a configuration in that information is stored in a memory array 101 and the memory array 101 is constructed by arranging a plurality of memory cells. Information can be stored/read to/from a memory cell in the memory array 101 .
  • a word line decoder 104 selects a word line in the memory array 101 corresponding to a signal input to the address line 102
  • a bit line decoder 105 selects a bit line in the memory array 101 corresponding to an address signal input to the address line 102
  • a source line decoder 106 selects a source line of the memory array 101 corresponding to the address signal input to the address line 102 .
  • a control circuit 109 controls programming, erasing and reading of the memory array 101 .
  • the control circuit 109 controls the word line decoder 104 , the bit line decoder 105 , the source line decoder 106 , a voltage switch circuit 110 and a pulse voltage applying circuit 108 on the basis of an address signal input from the address line 102 , data input (at the time of programming) input from the data line 103 and a control input signal input from a control signal line 111 , and controls reading, programming and erasing operations of the memory array 101 .
  • the control circuit 109 has, although not shown, functions of an address buffer circuit, a data input/output buffer circuit and a control input buffer circuit as general circuits.
  • the voltage switch circuit 110 applies a bit line voltage and a source line voltage which are necessary at the time of reading, programming and erasing of the memory array 101 .
  • Vcc denotes a voltage supplied to the device
  • Vss denotes a ground voltage
  • Vpp denotes a voltage for programming or erasing.
  • the pulse voltage applying circuit 108 applies a pulse voltage to a word line selected by the word line decoder 104 .
  • the pulse voltage applying circuit 108 further has the function capable of simultaneously applying the same pulse voltage to one or more word lines and has the function capable of simultaneously applying a pulse voltage at different voltage levels to two or more word lines.
  • Data is read from the memory array 101 via the bit line decoder 105 and a read circuit 107 .
  • the read circuit 107 determines the state of data, sends the result to the control circuit 109 , and outputs it to the data line 103 .
  • FIG. 2 is a schematic cross-sectional view of a memory cell 11 as a component of the memory array 101 .
  • the memory cell 11 is formed by connecting a selection transistor 6 and a variable resistive element 10 in series while electrically connecting a drain region 3 and a lower electrode 7 .
  • the selection transistor 6 is constructed by a source region 2 and the drain region 3 made in a semiconductor substrate 1 and a gate electrode 5 formed on a gate oxide film 4 .
  • the variable resistive element 10 is constructed by sandwiching a variable resistive material 8 of which resistance value changes when a voltage is applied between the lower electrode 7 and an upper electrode 9 .
  • the upper electrode 9 is connected to a metal wire 12 serving as a bit line
  • the gate electrode 5 is connected to a word line
  • the source region 2 is connected to a diffusion layer or a metal wire 13 serving as a source line.
  • the variable resistive element 10 is a nonvolatile memory element of which electric resistance changes by application of a voltage and, even after the application of the voltage is finished, whose changed electric resistance is held, and which can store data according to the resistance change, and is a CMR (Colossal Magnetoresistance) memory element made of an oxide having a perovskite type crystal structure containing manganese.
  • the variable resistive material 8 for example, a film formed by using any of materials expressed as Pr 1-x Ca x MnO 3 , La 1-x Ca x MnO 3 (PCMO), or La 1-x-y Ca x Pb y MnO 3 (where x ⁇ 1, y ⁇ 1, x+y ⁇ 1) is used.
  • a manganese oxide film made of Pr 0.7 Ca 0.3 MnO 3 , La 0.65 Ca 0.35 MnO 3 , La 0.65 Ca 0.175 Pb 0.175 MnO 3 or the like is formed by MOCVD, spin coating, laser ablation, sputtering or the like.
  • variable resistive element 10 Since the resistance change of the variable resistive element 10 is as large as three digits or more, even when a resistance value is divided into a plurality of regions and different information is defined for the regions, each of the information can be sufficiently determined. Consequently, the variable resistive element 10 can store multivalue information of one bit (binary data) or more.
  • the above-listed variable resistive materials have a non-linear current-voltage characteristic. Concretely, they have the Poole-Frenkele type nonlinear electric conductivity characteristic described above.
  • FIGS. 3 and 4 schematically show the configurations of the memory array 101 .
  • the memory array 101 has a configuration in that m ⁇ n memory cells 11 are disposed at intersecting points of m bit lines (BL 1 to BLm) and n word lines (WL 1 to WLn).
  • FIG. 3 shows a configuration in that n source lines (SL 1 to SLn) are disposed in parallel with the word lines.
  • FIG. 4 shows a configuration in that m source lines (SL 1 to SLm) are disposed in parallel with bit lines.
  • FIG. 5 is a schematic view showing the layout of a part (four cells) of the memory array 101 in which the source lines are parallel with the word lines as shown in FIG. 3 .
  • FIG. 6 is a schematic view showing the layout of a part (two cells) of the memory array in which the source lines are parallel with the bit lines as shown in FIG. 4 .
  • the memory arrays 101 in FIGS. 5 and 6 have different numbers of cells, but have almost the same area.
  • the sectional structure of the memory cell shown in FIG. 2 does not directly correspond to any of the layouts of FIGS. 5 and 6 , but can be adapted to the layout of each of the memory cells of FIGS. 5 and 6 by changing arrangement of the bit lines or source lines on the basis of the sectional structure of the memory cell shown in FIG. 2 .
  • the source line SL can be formed by a diffusion layer.
  • the source line SL cannot be formed by the diffusion layer. It is necessary to provide a contact in a source diffusion region and connect the contact to the source line SL of a metal layer every two cells. Since the source line SL has to be formed between the bit lines BL, the cell area enlarges.
  • the selection transistors 6 in not-selected cells in the same row and using a common word line are turned on and Vpp is applied to the source regions 2 . Consequently, it becomes necessary to apply Vpp to all of bit lines of not-selected cells to prevent a voltage from being applied to the variable resistive elements 10 , and the control becomes complicated.
  • Any of the configurations of the memory array may be used, but it is preferable to use the array of FIG. 3 having a small cell area from the viewpoint of manufacturing cost.
  • the present invention is not limited to the extending direction of the source lines, and the configurations of the memory array are not limited to the configurations shown in FIGS. 3 and 4 , but a configuration obtained by modifying the two configurations may be also used.
  • Table 1 shows voltage conditions at terminals at the time of programming and erasing of the memory cell 11 .
  • Vpp is applied to the upper electrode
  • Vss is applied to the source region
  • a voltage pulse having a voltage amplitude Vwp which will be described later is applied to the gate electrode and the selection transistor 6 is turned on
  • a positive voltage which is equal to or more than a program threshold voltage switching voltage which changes from the low resistance state to the high resistance state is applied to the variable resistive element 10
  • the low resistance state changes to the high resistance state (the voltage polarity in the case where the upper electrode has a voltage higher than that of the lower electrode is set to be positive).
  • Vss is applied to the upper electrode
  • Vpp is applied to the source region
  • a voltage pulse having voltage amplitude Vwe is applied to the gate electrode
  • the selection transistor 6 is turned on, a negative voltage whose absolute value is equal to or more than the erase threshold voltage is applied to the variable resistive element 10 and the variable resistive element 10 changes from the high resistance state to the low resistance state.
  • the control method of the inventive device 100 will be described by also using an equivalent circuit of the memory cell 11 shown in FIG. 7 .
  • the selection transistor 6 and the variable resistive element 10 are connected in series, and the source region 2 in the selection transistor 6 and the upper electrode 9 of the variable resistive element 10 are connected to the voltage switch circuit 110 in FIG. 2 , respectively.
  • Vpp program or erase voltage
  • Vss ground voltage
  • the pulse voltage applying circuit 108 is connected to the gate electrode 5 of the selection transistor 6 , and a pulse voltage having a pulse width of “t” seconds and a voltage amplitude of Vwp or Vwe can be applied to the gate electrode 5 .
  • the selection transistor 6 can be equivalently used as a resistive element 17 having an ON-state resistance value Ron and can be expressed as an equivalent circuit shown in FIG. 8 .
  • the resistance value of the variable resistive element 10 is expressed as Rr, and voltages to the resistive element 17 as the selection transistor 6 are described as Vds and Vr.
  • the drain current does not show a large change in response to a change in the source-drain voltage Vds and the resistive element 17 can be dealt approximately as a constant current element.
  • the selection transistor 6 operates in a linear region (non-saturation region)
  • the drain current changes so as to follow a change in the source-drain voltage.
  • the program voltage Vpp is applied to the upper electrode 9 , and the ground voltage Vss is applied to the source region 2 .
  • the voltage Vr applied to the resistive element 17 is expressed by Mathematical Expression (1)
  • the voltage Vds applied across the drain and source of the selection transistor 6 is expressed by Mathematical Expression (2)
  • the voltage different (Vpp ⁇ Vss) between the upper electrode 9 and the source region 2 is divided into Vr and Vds.
  • Vr Vpp ⁇ Rr /( Rr+Ron ) (1)
  • Vds Vpp ⁇ Ron /( Rr+Ron ) (2)
  • the voltage Vr applied to the variable resistive element 10 can be controlled as shown by Mathematical Expression (1). Consequently, the voltage pulse having the voltage amplitude Vwp adjusted so that a voltage which is equal to or more than the program threshold voltage and is close to the program threshold voltage as much as possible is applied to the variable resistive element 10 is applied to the gate electrode 5 .
  • Vr denotes a voltage applied across the upper electrode 9 and the lower electrode 7 when the same current as the drain current flowing in the selection transistor 6 flows in the variable resistive element 10 .
  • variable resistive element 10 If the voltage amplitude Vwp is increased unnecessarily and the on-state resistance Ron decreases excessively, a voltage exceeding the program threshold voltage is applied to the variable resistive element 10 . Moreover, the drain current at the time of programming increases and, as a result, the current consumption at the time of programming increases.
  • the erasing operation of the memory cell 11 is the same as the programming operation.
  • the resistance value of the variable resistive element 10 in the memory cell 11 in the erasing operation is in the high resistance state, so that the erase threshold voltage can be applied to the variable resistive element 10 with a drain current smaller than that in the programming operation. Consequently, the on-state resistance Ron of the selection transistor 6 can be set to be higher than that in the programming operation, and the voltage amplitude Vwe of the pulse voltage applied to the gate electrode 5 has to be set to be smaller than the voltage amplitude Vwp in the programming operation.
  • FIG. 9 shows the voltages Vpp, Vss and Vwp applied to the terminals of the memory cell 11 in FIG. 7 in the programming operation, the drain-source voltage Vds, drain current and on-state resistance Ron of the selection transistor 6 , and resistance Rr 0 and a voltage Vr 0 across terminals in the low resistance state of the variable resistive element 10 .
  • the voltages Vpp, Vss and Vwp are 5 V, 0 V and 5.5 V, respectively.
  • Vds, the drain current and on-state resistance Ron of the selection transistor 6 are 3.6 V, 1.95 mA and 1.8 k ⁇ , respectively.
  • the resistance Rr 0 and the voltage Vr 0 across the terminals of the variable resistive element 10 are 720 ⁇ and 1.4 V, respectively.
  • the voltage amplitude Vwp of the pulse voltage is 5.5 V
  • the voltage of 1.4 V exceeding the program threshold voltage is applied to the variable resistive element 10 and the resistance value changes from 720 ⁇ to the high resistance state.
  • FIG. 10 shows dependency of the voltage amplitude Vwp in the programming operation.
  • the figure shows changes in a combined resistance value (Rr+Ron) of the memory cell 11 in the case where the programming/erasing operation is repeated from the left end to the right.
  • a predetermined read voltage of 1 V or less is applied to a bit line, unnecessary programming and erasing operations are eliminated, and the combined resistance value is measured.
  • P 1 to P 8 denote the programming operations
  • E 1 to E 3 denote the erasing operations.
  • Vpp and Vss in the programming and erasing operations are 5 V and 0 V, respectively, and the pulse width of the pulse voltage is 100 nanoseconds.
  • the voltage values of the voltage amplitudes Vwp and Vwe of pulse voltages in the operations are shown in parentheses below P 1 to P 8 and E 1 to E 3 .
  • P 1 , E 1 , P 2 and E 2 show an operation check to see whether programming/erasing can be normally performed on the sample used for the program/erase test.
  • the pulse voltage is applied while increasing the voltage amplitude Vwp step by step in increments of 0.5 V from 3.0 V to 5.5 V.
  • programming with the voltage amplitude Vwp of 5.5 V could be checked.
  • E 3 and P 8 denote an operation check made after the dependency of the voltage amplitude Vwp was examined.
  • the voltage of 1.4 V exceeding the program threshold voltage is not applied to the variable resistive element 10 when the voltage amplitude Vwp is 5 V or less and the variable resistive element 10 does not change from the low resistance state (720 ⁇ ) to the high resistance state. Since intermediate programming is recognized when the voltage amplitude Vwp is 5 V, by controlling the voltage amplitude Vwp with high precision, multi-value storage can be realized.
  • FIG. 11 shows the voltages Vpp, Vss and Vwe applied to the terminals of the memory cell 11 in FIG. 7 in the erasing operation, the drain-source voltage Vds, drain current and on-state resistance Ron of the selection transistor 6 , and resistance Rr 1 and a voltage Vr 1 across terminals in the high resistance state of the variable resistive element 10 .
  • the voltages Vpp, Vss and Vwe are 5 V, 0 V and 3.5 V, respectively.
  • Vds, the drain current and on-state resistance Ron of the selection transistor 6 are 3.7 V, 645 ⁇ A, and 5.7 k ⁇ , respectively.
  • the resistance Rr 1 and the voltage Vr 1 across the terminals (absolute value) of the variable resistive element 10 are 1.95 k ⁇ and 1.3 V, respectively.
  • the voltage amplitude Vwe of the pulse voltage is 3.5 V
  • the voltage of 1.4 V (absolute value) exceeding the erase threshold voltage is applied to the variable resistive element 10 and the resistance value changes from 1.95 k ⁇ to the low resistance state.
  • FIG. 12 shows dependency of the voltage amplitude Vwe in the erasing operation.
  • the figure shows changes in a combined resistance value (Rr+Ron) of the memory cell 11 in the case where the programming/erasing operation is repeated from the left end to the right.
  • a predetermined read voltage of 1 V or less is applied to a bit line, unnecessary programming and erasing operations are eliminated, and the combined resistance value is measured.
  • P 1 to P 3 denote the programming operations
  • E 1 to E 7 denote the erasing operations.
  • Vpp and Vss in the programming and erasing operations are 5 V and 0 V, respectively, and the pulse width of the pulse voltage is 100 nanoseconds.
  • the voltage values of the voltage amplitudes Vwp and Vwe of pulse voltages in the operations are shown in parentheses below P 1 to P 3 and E 1 to E 7 .
  • P 1 , E 1 and P 2 show an operation check to see whether programming/erasing can be normally performed on the sample used for the program/erase test.
  • the pulse voltage is applied while increasing the voltage amplitude Vwe step by step in increments of 0.5 V from 1.0 V to 3.5 V.
  • P 3 denotes a program operation check made after the dependency of the voltage amplitude Vwe was examined.
  • the gate voltage becomes dominant. Even when the drain-source voltage Vds changes, an almost constant drain current flows, so that constant current programming is performed.
  • the drain current is adjusted with the voltage amplitude Vwp or Vwe of the pulse voltage, and the voltage value of Vr applied to the variable resistive element 6 can be changed.
  • the selection transistor 6 operates in the non-saturation region, the drain-source voltage Vds becomes dominant, so that constant current programming is not performed.
  • the drain-source voltage Vds becomes large to a certain extent, the linearity deteriorates, and the drain current changes due to a change in the gate voltage. Consequently, by adjusting the drain current by the voltage amplitude Vwp or Vwe of the pulse voltage, the voltage value of Vr applied to the variable resistive element 10 can be changed.
  • the saturation region is desirable as the operation region when the pulse voltage is applied to the gate voltage 5 of the selection transistor 6 .
  • the resistance value of the variable resistive element 10 decreases and the drain current becomes higher as compared with that in the initial state. It is therefore preferable that increase in the current consumption can be suppressed by the constant current operation.
  • the pulse width of the pulse voltage in the sample examples of FIGS. 10 and 12 , 100 nanoseconds is set.
  • an optimum value has to be employed according to the characteristics of the variable resistive element 10 .
  • 100 nanoseconds is preferable and a value in the range from 10 nanoseconds to 100 ⁇ s may be appropriately selected. If the programming/erasing operation is completed with the pulse width of 100 ⁇ s or less, the time is sufficiently shorter than the program time of the flash memory under the present circumferences.
  • the programming and erasing operations can be performed at the time of programming and erasing.
  • another control method of using the same voltage amplitude of the pulse voltage at-the time of programming and erasing and adjusting the program or erase voltage Vpp to be applied to the bit line or source line so as to apply a proper voltage to the variable resistive element 10 in each of the programming and erasing operations can be also considered.
  • the selection transistor 6 operates in the saturation region, even when Vpp is changed, the amount of current flowing in the variable resistive element 10 does not change largely, so that the voltage applied to the variable resistive element 10 does not change so much.
  • the programming or erasing method by controlling Vpp there is the possibility in that programming or erasing is not performed due to variations in the program or erase threshold voltage in the variable resistive element 10 .
  • the drain current in the selection transistor 6 is changed by controlling the gate voltage of the selection transistor 6 , a necessary voltage to be applied to the variable resistive element 10 can be properly controlled. Consequently, excessive current does not flow in the memory cell 11 and the voltage amplitudes Vwp and Vwe of the pulse voltage can be controlled so that the voltage which is equal to or more than the program/erase threshold voltage and is close to the program/erase threshold voltage as much as possible can be applied to the variable resistive element 10 with high precision.
  • the inventive method is particularly effective to a variable resistive element having a nonlinear current-voltage characteristic since the necessary voltage to be applied to the variable resistive element 10 can be controlled with high precision. Moreover, according to the inventive method, by changing the magnitude of the voltage amplitude Vwp of the pulse voltage at the time of programming, the voltage to be applied to the variable resistive element 10 can be adjusted with high precision. Consequently, the present invention provides the programming method particularly effective to a multivalue memory cell as a memory cell sensitive to variations in the resistance value and to which multivalue information of one or more bits is programmed.
  • the program voltage Vpp and the ground voltage Vss are applied to a selected bit line and a not-selected bit line, respectively, via the bit line decoder 105 and the voltage switch circuit 110 , and the ground voltage Vss is applied to all of the source lines via the source line decoder 106 and the voltage switch circuit 110 .
  • the pulse voltage having the voltage amplitude Vwp is applied to a selected word line from the pulse voltage applying circuit 108 via the word line decoder 104 .
  • the ground voltage Vss and the erase voltage Vpp are applied to a selected bit line and a not-selected bit line, respectively, via the bit line decoder 105 and the voltage switch circuit 110 .
  • the erase voltage Vpp and the ground voltage Vss are applied to a selected source line and a not-selected source line, respectively, by using the source line decoder 106 and the voltage switch circuit 110 .
  • the pulse voltage having the voltage amplitude Vwe is applied from the pulse voltage applying circuit 108 to a selected word line via the word line decoder 104 .
  • the program voltage Vpp and the ground voltage Vss are applied to a selected bit line and a not-selected bit line, respectively, via the bit line decoder 105 and the voltage switch circuit 110 , and the ground voltage Vss is applied to all of the source lines via the source line decoder 106 and the voltage switch 110 .
  • the pulse voltage having the voltage amplitude Vwp is applied to a selected word line from the pulse voltage applying circuit 108 via the word line decoder 104 .
  • the ground voltage Vss is applied to all of bit lines via the bit line decoder 105 and the voltage switch circuit 110 , and the erase voltage Vpp and the ground voltage Vss are applied to a selected source line and a not-selected source line, respectively, via the source line decoder 106 and the voltage switch circuit 110 .
  • the pulse voltage having the voltage amplitude Vwe is applied from the pulse voltage applying circuit 108 to a selected word line via the word line decoder 104 .
  • the number of word lines to which the pulse voltage is applied may be one.
  • the pulse voltage may be also applied simultaneously to two or more word lines in order to increase the program speed (program throughput) of the inventive device.
  • the number of word lines to which the pulse voltage is to be applied is two or more, by applying the pulse voltage while changing the voltage amplitude Vwp of the pulse voltage, information of different levels can be simultaneously programmed into the multivalue memory cell.
  • step W 1 Vpp and Vss are applied to a bit line and a source line, respectively, connected to the memory cell 11 .
  • step W 2 the pulse voltage of Vwp is applied to the word line connected to the memory cell 11 .
  • a current value or a resistance value (combined resistance of a variable resistive element and a transistor) of the memory cell 11 is read, and whether the read value is equal to or less than a predetermined current value (Iw) or equal to or more than a predetermined resistance value (Rw) is verified (step W 3 ), thereby indirectly determining whether the electric resistance of the variable resistive element 10 reaches a predetermined range (program state) or not. If the electric resistance has reached the range, the programming is finished (step W 5 ).
  • step W 4 the word line voltage Vwp is increased only by ⁇ V (step W 4 ), the pulse voltage is applied again (step W 2 ) and, after that, similar verification is performed (step W 3 ). The operation is repeated and application of the voltage pulse (step W 2 ) and the verification (step W 3 ) are performed until the electric resistance has reached the range, and the programming operation is finished.
  • FIG. 10 shows the relation between the voltage amplitude Vwp at the time of programming of a pulse voltage to be applied to the gate voltage 5 of the selection transistor 6 and a read resistance value after application of the pulse voltage.
  • the erasing operation can be also performed by a procedure similar to that of the programming operation.
  • Vss and Vpp are applied to a bit line and a source line, respectively, connected to the memory cell 11 .
  • the pulse voltage of Vwe is applied to the word line connected to the memory cell 11 .
  • a current value or a resistance value (combined resistance of a variable resistive element and a selection transistor) of the memory cell 11 is read, and whether the read value is equal to or more than a predetermined current value (Ie) or equal to or less than a resistance value (Re) is verified (step E 3 ), thereby indirectly determining whether the electric resistance of the variable resistive element 10 reaches a predetermined range (erase state) or not. If the electric resistance has reached the range, the erasing operation is finished (step E 5 ). If the electric resistance has not reached the range yet, the word line voltage Vwe is increased only by ⁇ V (step E 4 ), the pulse voltage is applied again (step E 2 ) and, after that, similar verification is performed (step E 3 ). The operation is repeated, application of the voltage pulse (step E 2 ) and the verification (step E 3 ) are performed until the electric resistance has reached the range, and the erasing operation is finished.
  • FIG. 12 shows the relation between the voltage amplitude Vwe at the time of erasing with a pulse voltage to be applied to the gate voltage 5 of the selection transistor 6 and a read resistance value after application of the pulse voltage.
  • the programming and erasing operations can be performed at the time of programming and erasing.
  • the pulse width of the pulse voltage applied to the gate voltage 5 a period in which the memory cell is in the program or erase state is specified.
  • the pulse voltage or erase voltage in pulses to be applied across a bit line and a source line in the first embodiment is applied.
  • a predetermined word line voltage is applied to a word line connected to the memory cell to be programmed or erased, and the period in which the memory cell 11 enters the program or erase state is specified by the pulse width of a pulse voltage applied to either the bit line or the source line.
  • a pulse voltage is applied to the upper electrode 9 of the variable resistive element 10 or the source region 2 of the selection transistor 6 .
  • voltage conditions of the components word line, bit line and source line
  • the second embodiment of applying the pulse voltage to a bit line of a small load capacity is more desirable than the first embodiment of applying the pulse voltage to a word line.
  • FIG. 20 is a block diagram showing an inventive device 200 according to the second embodiment.
  • a pulse voltage applying circuit 208 applies a pulse voltage to a bit line selected by the bit line decoder 105 or a source line selected by the source line decoder 106 .
  • the pulse voltage applying circuit 208 further has the function capable of applying the same pulse voltage to one or more bit lines or source lines and has the function capable of simultaneously applying pulse voltages of different voltage levels to two or more bit lines or source lines.
  • a program voltage or erase voltage of the voltage switch circuit 110 is applied via the pulse voltage applying circuit 208 .
  • a predetermined word line voltage (Vwp in the programming operation and Vwe in the erasing operation) is applied by the word line decoder 104 via the voltage switch circuit 110 , but is not applied as a pulse voltage specifying the program or erase period.
  • the other circuit configuration is the same as that of the first embodiment and the same reference numeral is given to a circuit having the same function.
  • the voltage switch circuit for word line voltage may be constructed by a circuit different from the voltage switch circuit for switching between the program voltage and the erase voltage of a bit line and a source line. In FIG. 20 , both of the circuits are shown as one circuit.
  • the program voltage Vwp and the ground voltage Vss are applied to a selected word line and a not-selected word line, respectively, via the word line decoder 104 and the voltage switch circuit 110 .
  • the ground voltage Vss is applied to all of source lines via the source line decoder 106 and the voltage switch circuit 110 .
  • the pulse voltage having the voltage amplitude Vpp is applied to a selected bit line via the bit line decoder 105 from the pulse voltage applying circuit 208 .
  • the ground voltage Vss and the erase voltage Vpp are applied to a selected bit line and a not-selected bit line, respectively, via the bit line decoder 105 and the voltage switch circuit 110 .
  • the erase voltage Vwe and the ground voltage Vss are applied to a selected word line and a not-selected source line, respectively, via the word line decoder 104 and the voltage switch circuit 110 .
  • the pulse voltage having the voltage amplitude Vpp is applied from the pulse voltage applying circuit 208 to a selected source line via the source line decoder 106 .
  • the program voltage Vwp and the ground voltage Vss are applied to a selected word line and a not-selected word line, respectively, via the word line decoder 104 and the voltage switch circuit 110 , and the ground voltage Vss is applied to all of the source lines via the source line decoder 106 and the voltage switch circuit 110 .
  • the pulse voltage having the voltage amplitude Vpp is applied to a selected bit line from the pulse voltage applying circuit 208 via the bit line decoder 105 .
  • the ground voltage Vss is applied to all of bit lines via the bit line decoder 105 and the voltage switch circuit 110 , the erase voltage Vwe and the ground voltage Vss are applied to a selected word line and a not-selected word line, respectively, via the word line decoder 104 and the voltage switch circuit 110 , and the ground voltage Vss is applied to a not-selected source line via the source line decoder 106 and the voltage switch circuit 110 .
  • the pulse voltage having the voltage amplitude Vpp is applied from the pulse voltage applying circuit 208 to a selected source line via the source line decoder 106 .
  • the number of bit lines or source lines to which the pulse voltage is applied may be one.
  • the pulse voltage may be also applied simultaneously to two or more bit lines or source lines in order to increase the program speed (program throughput) of the inventive device.
  • the number of word lines to which the word line voltage is to be applied is two or more at the time of programming, by applying the word line voltage while changing the voltage amplitude Vwp of the word line voltage, information of different levels can be simultaneously programmed into the multivalue memory cell.
  • step W 1 Vwp and Vss are applied to a word line and a source line, respectively, connected to the memory cell 11 .
  • step W 2 the pulse voltage of Vpp is applied to the bit line connected to the memory cell 11 .
  • a current value or a resistance value (combined resistance of a variable resistive element and a transistor) of the memory cell 11 is read, and whether the read value is equal to or less than a predetermined current value (Iw) or equal to or more than a predetermined resistance value (Rw) is verified (step W 3 ), thereby indirectly determining whether the electric resistance of the variable resistive element 10 reaches a predetermined range (program state) or not. If the electric-resistance reaches the range, the programming operation is finished (step W 5 ). However, if the electric resistance does not satisfy the conditions, a voltage obtained by increasing the word line voltage Vwp only by ⁇ V in step W 4 is applied to the word line in step W 1 .
  • step W 2 The pulse voltage is applied again to the bit line (step W 2 ) and verification is performed similarly (step W 3 ).
  • step W 3 The operation is repeated and application of the word line voltage (step W 1 ), application of the voltage pulse (step W 2 ) and verification (step W 3 ) are performed until the electric resistance reaches the range, and the programming operation is finished.
  • the erasing operation can be also performed by a procedure similar to that of the programming operation.
  • Vwe and Vss are applied to a word line and a bit line, respectively, connected to the memory cell 11 .
  • the pulse voltage of Vpp is applied to the source line connected to the memory cell 11 .
  • a current value or a resistance value (combined resistance of a variable resistive element and a selection transistor) of the memory cell 11 is read, and whether the read value is equal to or less than a predetermined current value (Ie) or equal to or more than a resistance value (Re) is verified (step E 3 ), thereby indirectly determining whether the electric resistance of the variable resistive element 10 reaches a predetermined range (erase state) or not. If the electric resistance has reached the range, the erasing is finished (step E 5 ).
  • step E 4 a voltage obtained by increasing the word line voltage Vwe only by ⁇ V in step E 4 is applied to the word line in step E 1 , the pulse voltage is applied again to the source line (step E 2 ) and, after that, similar verification is performed (step E 3 ). The operation is repeated and application of the word line voltage (step E 1 ), application of the voltage pulse (step E 2 ) and the verification (step E 3 ) are performed until the electric resistance reaches the predetermined range, and the erasing operation is finished.
  • the memory cell 11 is constructed as shown in FIGS. 2 and 7 .
  • the memory cell 11 may be also constructed in such a manner that the source region 2 of the selection transistor 6 and the lower electrode 7 of the variable resistive element 10 are electrically connected to each other, the upper electrode 9 is connected to a source line, the drain region 3 is connected to a bit line, and the position of the selection transistor 6 and that of the variable resistive element 10 are interchanged.
  • the voltage difference (Vpp ⁇ Vss) between the upper electrode 9 and the drain region 3 is divided into the voltage Vr applied across both ends of the variable resistive element 10 and the source-drain voltage Vds in a normal state in a manner similar to the memory cell configurations shown in FIGS. 2 and 7 .
  • the inventive device and the inventive method are not limited to an RRAM using an oxide having a perovskite-type crystal structure containing manganese such as PCMO as the variable resistive material, but can be also easily applied to a nonvolatile semiconductor memory device in which a memory cell is constructed by using an element whose resistance value changes according to application of a voltage as a memory carrier.
  • the nonvolatile semiconductor memory device and the control method thereof by applying voltages to a bit line and a source line and, after that, adjusting the voltage amplitude of a pulse voltage to be applied to a word line, the voltage applied to the variable resistive element can be adjusted with high precision. As a result, an excessive voltage is not applied to the variable resistive element at the time of programming/erasing, so that the programming and erasing operations can be performed with a small current amount. Since the voltage applied to the variable resistive element can be adjusted with high precision, the resistance value of the variable resistive element can be also controlled with high precision.
  • the present invention can provide the nonvolatile semiconductor memory device and the control method thereof optimum to be used for a multivalue memory cell which is sensitive to variations in the resistance value and stores multivalue information of two or more bits.
  • the amplitude of the word line voltage to be applied at the time of programming and erasing can be easily adjusted.
  • the voltage applied to the variable resistive element can be adjusted with high precision.
  • an excessive voltage is not applied to the variable resistive element, and programming and erasing can be performed with a small current amount.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
US10/867,950 2003-06-12 2004-06-14 Nonvolatile semiconductor memory device and control method thereof Expired - Lifetime US6995999B2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2003168223 2003-06-12
JP2003-168223 2003-06-12
JP2003433815A JP4113493B2 (ja) 2003-06-12 2003-12-26 不揮発性半導体記憶装置及びその制御方法
JP2003-433815 2003-12-26

Publications (2)

Publication Number Publication Date
US20040264244A1 US20040264244A1 (en) 2004-12-30
US6995999B2 true US6995999B2 (en) 2006-02-07

Family

ID=33302293

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/867,950 Expired - Lifetime US6995999B2 (en) 2003-06-12 2004-06-14 Nonvolatile semiconductor memory device and control method thereof

Country Status (7)

Country Link
US (1) US6995999B2 (ja)
EP (1) EP1486985B1 (ja)
JP (1) JP4113493B2 (ja)
KR (1) KR100547969B1 (ja)
CN (1) CN100479057C (ja)
DE (1) DE602004008833T2 (ja)
TW (1) TWI237271B (ja)

Cited By (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050258027A1 (en) * 2003-09-15 2005-11-24 Makoto Nagashima Back-biased face target sputtering based programmable logic device
US20060081466A1 (en) * 2004-10-15 2006-04-20 Makoto Nagashima High uniformity 1-D multiple magnet magnetron source
US20060081467A1 (en) * 2004-10-15 2006-04-20 Makoto Nagashima Systems and methods for magnetron deposition
US20060276036A1 (en) * 2004-10-15 2006-12-07 Makoto Nagashima Systems and methods for plasma etching
US20070008773A1 (en) * 2005-07-11 2007-01-11 Matrix Semiconductor, Inc. Nonvolatile memory cell comprising switchable resistor and transistor
US20070008770A1 (en) * 2005-07-08 2007-01-11 Hajime Nagao Storage devices and semiconductor devices
US20070070710A1 (en) * 2005-09-27 2007-03-29 Oki Electric Industry Co., Ltd. Nonvolatile semiconductor memory device and data writing method
US20070084717A1 (en) * 2005-10-16 2007-04-19 Makoto Nagashima Back-biased face target sputtering based high density non-volatile caching data storage
US20070097730A1 (en) * 2005-10-27 2007-05-03 Chen Eugene Y Current driven switched magnetic storage cells having improved read and write margins and magnetic memories using such cells
US20070224770A1 (en) * 2006-03-25 2007-09-27 Makoto Nagashima Systems and methods for fabricating self-aligned memory cell
US20080007993A1 (en) * 2006-07-04 2008-01-10 Sharp Kabushiki Kaisha Semiconductor memory device
US20080011600A1 (en) * 2006-07-14 2008-01-17 Makoto Nagashima Dual hexagonal shaped plasma source
US20080014750A1 (en) * 2006-07-14 2008-01-17 Makoto Nagashima Systems and methods for fabricating self-aligned memory cell
US20080011603A1 (en) * 2006-07-14 2008-01-17 Makoto Nagashima Ultra high vacuum deposition of PCMO material
US20080025070A1 (en) * 2006-07-31 2008-01-31 Sharp Kabushiki Kaisha Semiconductor memory device
US20080049487A1 (en) * 2006-08-22 2008-02-28 Sharp Kabushiki Kaisha Semiconductor memory device
US20080062740A1 (en) * 2006-08-28 2008-03-13 In-Gyu Baek Methods of programming a resistive memory device
US20080062752A1 (en) * 2006-09-05 2008-03-13 Stmicroelectronics Sa Phase change memory erasable and programmable by a row decoder
US20080101110A1 (en) * 2006-10-25 2008-05-01 Thomas Happ Combined read/write circuit for memory
US20080316821A1 (en) * 2007-04-27 2008-12-25 Atsushi Yokoi Nonvolatile storage device and bias control method thereof
US20090046495A1 (en) * 2005-05-11 2009-02-19 Atsushi Shimaoka Nonvolatile semiconductor memory device
US20090046496A1 (en) * 2006-06-16 2009-02-19 Yoshikazu Katoh Nonvolatile memory device
US7660148B2 (en) 2007-04-24 2010-02-09 Spansion Llc Nonvolatile memory device and method to control the same
US20100054045A1 (en) * 2008-09-04 2010-03-04 Macronix International Co., Ltd. Memory and Reading Method Thereof
US20100182820A1 (en) * 2009-01-22 2010-07-22 Sony Corporation Variable resistance memory device
US20100214862A1 (en) * 2009-02-26 2010-08-26 Ho Jung Kim Semiconductor Devices and Methods for Changing Operating Characteristics and Semiconductor Systems Including the Same
US20100259967A1 (en) * 2007-11-29 2010-10-14 Sony Corporation Memory cell
US20100271860A1 (en) * 2008-09-30 2010-10-28 Shunsaku Muraoka Driving method of variable resistance element, initialization method of variable resistance element, and nonvolatile storage device
US20110044088A1 (en) * 2008-08-20 2011-02-24 Shunsaku Muraoka Variable resistance nonvolatile storage device and method of forming memory cell
US20110149635A1 (en) * 2007-12-12 2011-06-23 Sony Corporation Storage device and information rerecording method
US8154909B2 (en) * 2007-06-01 2012-04-10 Panasonic Corporation Resistance variable memory apparatus
US20120250401A1 (en) * 2011-03-29 2012-10-04 Nxp B.V. Phase change memory (pcm) architecture and a method for writing into pcm architecture
US8308915B2 (en) 2006-09-14 2012-11-13 4D-S Pty Ltd. Systems and methods for magnetron deposition
US20130250654A1 (en) * 2012-03-26 2013-09-26 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device
US8563962B2 (en) 2009-12-28 2013-10-22 Panasonic Corporation Memory device and method of manufacturing the same
US20150109850A1 (en) * 2013-10-23 2015-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Memory devices
US9111610B2 (en) 2012-04-20 2015-08-18 Panasonic Intellectual Property Management Co., Ltd. Method of driving nonvolatile memory element and nonvolatile memory device
US20150269983A1 (en) * 2011-03-23 2015-09-24 Kabushiki Kaisha Toshiba Semiconductor memory device
US9218878B2 (en) 2012-11-20 2015-12-22 Elpida Memory, Inc. Semiconductor device and control method for semiconductor device
US20160019962A1 (en) * 2010-10-29 2016-01-21 Rambus Inc. Resistance change memory cell circuits and methods
US9553131B2 (en) 2014-08-19 2017-01-24 Renesas Electronics Corporation Semiconductor device and forming method
US20170076773A1 (en) * 2015-09-15 2017-03-16 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
US10896699B1 (en) 2019-07-11 2021-01-19 Samsung Electronics Co., Ltd. Memory devices including switch circuit that operates regardless of power supply voltage

Families Citing this family (95)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4670252B2 (ja) 2004-01-20 2011-04-13 ソニー株式会社 記憶装置
JP5135406B2 (ja) * 2004-02-20 2013-02-06 ルネサスエレクトロニクス株式会社 半導体装置
JP4365737B2 (ja) 2004-06-30 2009-11-18 シャープ株式会社 可変抵抗素子の駆動方法及び記憶装置
US7443710B2 (en) * 2004-09-28 2008-10-28 Spansion, Llc Control of memory devices possessing variable resistance characteristics
DE602005024840D1 (de) 2004-09-30 2010-12-30 Nxp Bv Integrierte schaltung mit speicherzellen mit einem programmierbaren widerstand und verfahren zum adressieren von speicherzellen mit einem programmierbaren widerstand
US7359236B2 (en) * 2005-03-11 2008-04-15 Adesto Technologies Read, write and erase circuit for programmable memory devices
JP4552745B2 (ja) * 2005-05-10 2010-09-29 ソニー株式会社 記憶素子及びその製造方法
WO2006137110A1 (ja) 2005-06-20 2006-12-28 Fujitsu Limited 不揮発性半導体記憶装置及びその書き込み方法
WO2006137111A1 (ja) 2005-06-20 2006-12-28 Fujitsu Limited 不揮発性半導体記憶装置及びその書き込み方法
US7289351B1 (en) * 2005-06-24 2007-10-30 Spansion Llc Method of programming a resistive memory device
JP4802608B2 (ja) * 2005-08-19 2011-10-26 ソニー株式会社 記憶装置
JP4828901B2 (ja) * 2005-09-22 2011-11-30 株式会社東芝 半導体集積回路装置
US7514706B2 (en) * 2005-10-14 2009-04-07 Adesto Technologies Voltage reference circuit using programmable metallization cells
KR100970383B1 (ko) 2005-10-19 2010-07-15 후지쯔 가부시끼가이샤 불휘발성 반도체 기억 장치의 기입 방법
US7463507B2 (en) 2005-11-09 2008-12-09 Ulrike Gruening-Von Schwerin Memory device with a plurality of memory cells, in particular PCM memory cells, and method for operating such a memory cell device
DE102005063435B4 (de) * 2005-11-09 2015-12-10 Polaris Innovations Ltd. Speicherbauelement mit mehreren Speicherzellen, insbesondere PCM-Speicherzellen, sowie Verfahren zum Betreiben eines derartigen Speicherbauelements
DE102005053496B4 (de) * 2005-11-09 2008-05-08 Qimonda Ag Speicherbauelement mit mehreren resistiv schaltenden Speicherzellen, insbesondere PCM-Speicherzellen
JP4764142B2 (ja) 2005-11-11 2011-08-31 株式会社東芝 半導体記憶装置
JPWO2007074504A1 (ja) * 2005-12-26 2009-06-04 富士通株式会社 不揮発性半導体記憶装置及びその書き込み方法
JP4203506B2 (ja) * 2006-01-13 2009-01-07 シャープ株式会社 不揮発性半導体記憶装置及びその書き換え方法
JP4594878B2 (ja) * 2006-02-23 2010-12-08 シャープ株式会社 可変抵抗素子の抵抗制御方法及び不揮発性半導体記憶装置
JP2007234133A (ja) * 2006-03-01 2007-09-13 Matsushita Electric Ind Co Ltd 半導体記憶装置及び半導体集積回路システム
US7522444B2 (en) 2006-03-13 2009-04-21 Infineon Technologies Ag Memory circuit, method for operating a memory circuit, memory device and method for producing a memory device
KR100868035B1 (ko) * 2006-03-13 2008-11-10 키몬다 아게 메모리 회로, 메모리 회로를 동작시키는 방법, 메모리디바이스 및 메모리 디바이스를 생성하는 방법
EP1835509A1 (de) * 2006-03-14 2007-09-19 Qimonda AG Speicherzelle, Speicher mit einer Speicherzelle und Verfahren zum Einschreiben von Daten in eine Speicherzelle
JP2007294592A (ja) 2006-04-24 2007-11-08 Sony Corp 記憶装置の駆動方法
JP4781431B2 (ja) 2006-05-16 2011-09-28 富士通株式会社 不揮発性半導体記憶装置及びその書き込み方法
US8014199B2 (en) * 2006-05-22 2011-09-06 Spansion Llc Memory system with switch element
US7428163B2 (en) * 2006-07-21 2008-09-23 Infineon Technologies Ag Method and memory circuit for operating a resistive memory cell
WO2008029446A1 (fr) * 2006-09-05 2008-03-13 Fujitsu Limited Procédé d'écriture d'appareil de stockage a semi-conducteur non volatil
KR100809337B1 (ko) 2006-09-06 2008-03-05 삼성전자주식회사 비휘발성 메모리 장치 및 그 구동 방법
KR101258983B1 (ko) * 2006-09-19 2013-04-29 삼성전자주식회사 가변저항 소자를 이용한 반도체 메모리 장치 및 그 동작방법
US7920402B2 (en) 2006-11-17 2011-04-05 Panasonic Corporation Resistance variable memory apparatus
JP2008146740A (ja) 2006-12-08 2008-06-26 Sharp Corp 半導体記憶装置
JP4745956B2 (ja) * 2006-12-25 2011-08-10 富士通株式会社 シミュレーション装置
US8085615B2 (en) 2006-12-29 2011-12-27 Spansion Llc Multi-state resistance changing memory with a word line driver for applying a same program voltage to the word line
JP4221031B2 (ja) 2007-02-09 2009-02-12 シャープ株式会社 不揮発性半導体記憶装置及びその書き換え方法
WO2008129774A1 (ja) * 2007-03-13 2008-10-30 Panasonic Corporation 抵抗変化型記憶装置
US7764537B2 (en) * 2007-04-05 2010-07-27 Qualcomm Incorporated Spin transfer torque magnetoresistive random access memory and design methods
US7852662B2 (en) 2007-04-24 2010-12-14 Magic Technologies, Inc. Spin-torque MRAM: spin-RAM, array
KR100914267B1 (ko) * 2007-06-20 2009-08-27 삼성전자주식회사 가변저항 메모리 장치 및 그것의 형성방법
KR20090009699A (ko) * 2007-07-20 2009-01-23 삼성전자주식회사 커패시터가 없는 동적 메모리 셀을 구비한 반도체 메모리장치, 이 장치를 위한 동적 메모리 셀, 및 이 장치를구비한 메모리 시스템
US9129845B2 (en) 2007-09-19 2015-09-08 Micron Technology, Inc. Buried low-resistance metal word lines for cross-point variable-resistance material memories
JP5253784B2 (ja) * 2007-10-17 2013-07-31 株式会社東芝 不揮発性半導体記憶装置
JP2009141225A (ja) 2007-12-07 2009-06-25 Sharp Corp 可変抵抗素子、可変抵抗素子の製造方法、不揮発性半導体記憶装置
JP5072564B2 (ja) * 2007-12-10 2012-11-14 株式会社東芝 半導体記憶装置及びメモリセル電圧印加方法
JP4356786B2 (ja) * 2007-12-12 2009-11-04 ソニー株式会社 記憶装置および情報再記録方法
CN101952893B (zh) 2008-02-25 2013-09-11 松下电器产业株式会社 电阻变化元件的驱动方法及使用它的电阻变化型存储装置
JP5021029B2 (ja) 2008-05-22 2012-09-05 パナソニック株式会社 抵抗変化型不揮発性記憶装置
JP5221222B2 (ja) * 2008-06-25 2013-06-26 株式会社東芝 半導体記憶装置
WO2010047068A1 (ja) 2008-10-21 2010-04-29 パナソニック株式会社 不揮発性記憶装置及びそのメモリセルへの書き込み方法
US8125817B2 (en) 2008-12-18 2012-02-28 Panasonic Corporation Nonvolatile storage device and method for writing into the same
JP4806046B2 (ja) * 2009-03-16 2011-11-02 株式会社東芝 半導体記憶装置
JP2010225227A (ja) * 2009-03-23 2010-10-07 Toshiba Corp 不揮発性半導体記憶装置
US8320159B2 (en) 2009-03-25 2012-11-27 Panasonic Corporation Resistance variable nonvolatile memory device
US8199576B2 (en) * 2009-04-08 2012-06-12 Sandisk 3D Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a double-global-bit-line architecture
WO2010117912A1 (en) * 2009-04-08 2010-10-14 Sandisk 3D Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a double-global-bit-line architecture
US8351236B2 (en) 2009-04-08 2013-01-08 Sandisk 3D Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture
US7983065B2 (en) 2009-04-08 2011-07-19 Sandisk 3D Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines
WO2010119671A1 (ja) 2009-04-15 2010-10-21 パナソニック株式会社 抵抗変化型不揮発性記憶装置
JP4628500B2 (ja) 2009-04-30 2011-02-09 パナソニック株式会社 不揮発性記憶素子及び不揮発性記憶装置
WO2010131477A1 (ja) * 2009-05-14 2010-11-18 パナソニック株式会社 不揮発性記憶装置及び不揮発性記憶装置へのデータ書込み方法
US8325508B2 (en) * 2009-06-08 2012-12-04 Panasonic Corporation Writing method for variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device
US20120044749A1 (en) * 2009-11-02 2012-02-23 Shunsaku Muraoka Variable resistance nonvolatile storage device and method of forming memory cell
JP5120967B2 (ja) * 2009-12-25 2013-01-16 シャープ株式会社 可変抵抗素子
US8547720B2 (en) 2010-06-08 2013-10-01 Sandisk 3D Llc Non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines
US8526237B2 (en) 2010-06-08 2013-09-03 Sandisk 3D Llc Non-volatile memory having 3D array of read/write elements and read/write circuits and method thereof
JP5069339B2 (ja) * 2010-06-10 2012-11-07 シャープ株式会社 不揮発性可変抵抗素子の抵抗制御方法
US8804398B2 (en) * 2010-08-20 2014-08-12 Shine C. Chung Reversible resistive memory using diodes formed in CMOS processes as program selectors
EP2731110B1 (en) * 2010-12-14 2016-09-07 SanDisk Technologies LLC Architecture for three dimensional non-volatile storage with vertical bit lines
TWI614747B (zh) * 2011-01-26 2018-02-11 半導體能源研究所股份有限公司 記憶體裝置及半導體裝置
JP2014075159A (ja) * 2011-01-27 2014-04-24 Panasonic Corp 不揮発性記憶装置及び不揮発性記憶装置の駆動方法
JP5998059B2 (ja) * 2011-02-01 2016-09-28 パナソニック株式会社 不揮発性半導体記憶装置
CN102290101B (zh) * 2011-07-04 2016-02-24 上海华虹宏力半导体制造有限公司 源线偏置电路及存储器
JP5877338B2 (ja) * 2011-08-31 2016-03-08 パナソニックＩｐマネジメント株式会社 読み出し回路およびこれを用いた不揮発性メモリ
CN103165172B (zh) * 2011-12-09 2015-08-05 中国科学院微电子研究所 混合存储器件及其控制方法、制备方法
KR101959846B1 (ko) 2012-03-02 2019-03-20 삼성전자주식회사 저항성 메모리 장치
US9685608B2 (en) * 2012-04-13 2017-06-20 Crossbar, Inc. Reduced diffusion in metal electrode for two-terminal memory
US9165644B2 (en) * 2012-05-11 2015-10-20 Axon Technologies Corporation Method of operating a resistive memory device with a ramp-up/ramp-down program/erase pulse
JP5830655B2 (ja) 2013-04-30 2015-12-09 パナソニックＩｐマネジメント株式会社 不揮発性記憶素子の駆動方法
US9373399B2 (en) * 2013-07-22 2016-06-21 Micron Technology, Inc. Resistance variable element methods and apparatuses
US10037801B2 (en) 2013-12-06 2018-07-31 Hefei Reliance Memory Limited 2T-1R architecture for resistive RAM
US9029192B1 (en) * 2013-12-20 2015-05-12 Intermolecular, Inc. Metal organic chemical vapor deposition of resistive switching layers for ReRAM cells
US9286976B2 (en) * 2014-05-29 2016-03-15 Intel Corporation Apparatuses and methods for detecting write completion for resistive memory
CN105448330B (zh) * 2014-09-24 2018-10-16 华邦电子股份有限公司 电阻式随机存取存储器装置以及其形成方法
CN105869670B (zh) * 2015-01-19 2019-03-15 华邦电子股份有限公司 电阻式随机存取存储器
KR102394726B1 (ko) * 2015-10-26 2022-05-09 에스케이하이닉스 주식회사 내부전압생성회로
US10770140B2 (en) * 2016-01-27 2020-09-08 Hewlett Packard Enterprise Development Lp Memristive array with parallel reset control devices
JP2018156701A (ja) * 2017-03-16 2018-10-04 東芝メモリ株式会社 不揮発性半導体記憶装置
JP2020098655A (ja) * 2018-12-17 2020-06-25 キオクシア株式会社 半導体記憶装置
CN109903799B (zh) * 2019-01-29 2021-08-03 华中科技大学 一种可变编程级数的三维闪存阵列单元操作方法
JP6723402B1 (ja) * 2019-02-28 2020-07-15 ウィンボンド エレクトロニクス コーポレーション 抵抗変化型ランダムアクセスメモリ
US11423985B2 (en) * 2019-09-25 2022-08-23 Arm Limited Devices and methods for controlling write operations
CN113555047A (zh) * 2020-04-24 2021-10-26 上海磁宇信息科技有限公司 磁性随机存储器
US20230125070A1 (en) * 2021-10-25 2023-04-27 Taiwan Semiconductor Manufacturing Company, Ltd. Multilevel memory device and method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030086285A1 (en) * 2001-10-25 2003-05-08 Tetsuya Yamaguchi Ferroelectric semiconductor memory
US20030161182A1 (en) * 2002-02-27 2003-08-28 Yan Li Operating techniques for reducing program and read disturbs of a non-volatile memory
EP1426972A2 (en) 2002-12-05 2004-06-09 Sharp Kabushiki Kaisha Nonvolatile memory device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030086285A1 (en) * 2001-10-25 2003-05-08 Tetsuya Yamaguchi Ferroelectric semiconductor memory
US20030161182A1 (en) * 2002-02-27 2003-08-28 Yan Li Operating techniques for reducing program and read disturbs of a non-volatile memory
EP1426972A2 (en) 2002-12-05 2004-06-09 Sharp Kabushiki Kaisha Nonvolatile memory device
US20040114429A1 (en) 2002-12-05 2004-06-17 Sharp Kabushiki Kaisha Nonvolatile memory device

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
European Search Report mailed Jul. 12, 2005 for European Patent Application No. 04253457.8, 3 pages.
Hsu, S. T. et al. (2003). "Charge Transport Property In Non-Volatile Resistor Random Access Memory (RRAM)," Non-Volatile Semiconductor Memory Workshop, pp. 97-98.
Zhuang, W. W. et al. (2002). "Novell Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)," IEDM, Paper No. 7.5 IEEE , 4 pages.

Cited By (83)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070007124A1 (en) * 2003-09-15 2007-01-11 Makoto Nagashima Back-biased face target sputtering based memory with low oxygen flow rate
US20070119705A1 (en) * 2003-09-15 2007-05-31 Makoto Nagashima Back-biased face target sputtering based memory data sensing technique
US20050258027A1 (en) * 2003-09-15 2005-11-24 Makoto Nagashima Back-biased face target sputtering based programmable logic device
US20060081466A1 (en) * 2004-10-15 2006-04-20 Makoto Nagashima High uniformity 1-D multiple magnet magnetron source
US20060081467A1 (en) * 2004-10-15 2006-04-20 Makoto Nagashima Systems and methods for magnetron deposition
US20060276036A1 (en) * 2004-10-15 2006-12-07 Makoto Nagashima Systems and methods for plasma etching
US20090046495A1 (en) * 2005-05-11 2009-02-19 Atsushi Shimaoka Nonvolatile semiconductor memory device
US7697317B2 (en) * 2005-05-11 2010-04-13 Sharp Kabushiki Kaisha Nonvolatile semiconductor memory device
US20070008770A1 (en) * 2005-07-08 2007-01-11 Hajime Nagao Storage devices and semiconductor devices
US7426128B2 (en) * 2005-07-11 2008-09-16 Sandisk 3D Llc Switchable resistive memory with opposite polarity write pulses
US20070008773A1 (en) * 2005-07-11 2007-01-11 Matrix Semiconductor, Inc. Nonvolatile memory cell comprising switchable resistor and transistor
US20070070710A1 (en) * 2005-09-27 2007-03-29 Oki Electric Industry Co., Ltd. Nonvolatile semiconductor memory device and data writing method
US20070084717A1 (en) * 2005-10-16 2007-04-19 Makoto Nagashima Back-biased face target sputtering based high density non-volatile caching data storage
US7286395B2 (en) * 2005-10-27 2007-10-23 Grandis, Inc. Current driven switched magnetic storage cells having improved read and write margins and magnetic memories using such cells
US20070097730A1 (en) * 2005-10-27 2007-05-03 Chen Eugene Y Current driven switched magnetic storage cells having improved read and write margins and magnetic memories using such cells
US20070224770A1 (en) * 2006-03-25 2007-09-27 Makoto Nagashima Systems and methods for fabricating self-aligned memory cell
US8395199B2 (en) 2006-03-25 2013-03-12 4D-S Pty Ltd. Systems and methods for fabricating self-aligned memory cell
US7760539B2 (en) * 2006-06-16 2010-07-20 Panasonic Corporation Nonvolatile memory device
US20090046496A1 (en) * 2006-06-16 2009-02-19 Yoshikazu Katoh Nonvolatile memory device
US20080007993A1 (en) * 2006-07-04 2008-01-10 Sharp Kabushiki Kaisha Semiconductor memory device
US20080011600A1 (en) * 2006-07-14 2008-01-17 Makoto Nagashima Dual hexagonal shaped plasma source
US20080014750A1 (en) * 2006-07-14 2008-01-17 Makoto Nagashima Systems and methods for fabricating self-aligned memory cell
US20080011603A1 (en) * 2006-07-14 2008-01-17 Makoto Nagashima Ultra high vacuum deposition of PCMO material
US7932548B2 (en) 2006-07-14 2011-04-26 4D-S Pty Ltd. Systems and methods for fabricating self-aligned memory cell
US8367513B2 (en) 2006-07-14 2013-02-05 4D-S Pty Ltd. Systems and methods for fabricating self-aligned memory cell
US8454810B2 (en) 2006-07-14 2013-06-04 4D-S Pty Ltd. Dual hexagonal shaped plasma source
US20080025070A1 (en) * 2006-07-31 2008-01-31 Sharp Kabushiki Kaisha Semiconductor memory device
US7511986B2 (en) 2006-07-31 2009-03-31 Sharp Kabushiki Kaisha Semiconductor memory device
US7542326B2 (en) * 2006-08-22 2009-06-02 Sharp Kabushiki Kaisha Semiconductor memory device
US20080049487A1 (en) * 2006-08-22 2008-02-28 Sharp Kabushiki Kaisha Semiconductor memory device
US20080062740A1 (en) * 2006-08-28 2008-03-13 In-Gyu Baek Methods of programming a resistive memory device
US20080062752A1 (en) * 2006-09-05 2008-03-13 Stmicroelectronics Sa Phase change memory erasable and programmable by a row decoder
US7869268B2 (en) * 2006-09-05 2011-01-11 Stmicroelectronics Sa Phase change memory erasable and programmable by a row decoder
US8308915B2 (en) 2006-09-14 2012-11-13 4D-S Pty Ltd. Systems and methods for magnetron deposition
US20080101110A1 (en) * 2006-10-25 2008-05-01 Thomas Happ Combined read/write circuit for memory
US7660148B2 (en) 2007-04-24 2010-02-09 Spansion Llc Nonvolatile memory device and method to control the same
US7940563B2 (en) 2007-04-27 2011-05-10 Spansion Llc Nonvolatile storage device and bias control method thereof
US20080316821A1 (en) * 2007-04-27 2008-12-25 Atsushi Yokoi Nonvolatile storage device and bias control method thereof
US8154909B2 (en) * 2007-06-01 2012-04-10 Panasonic Corporation Resistance variable memory apparatus
US8295074B2 (en) * 2007-11-29 2012-10-23 Sony Corporation Memory cell
US20100259967A1 (en) * 2007-11-29 2010-10-14 Sony Corporation Memory cell
US20110149635A1 (en) * 2007-12-12 2011-06-23 Sony Corporation Storage device and information rerecording method
TWI400706B (zh) * 2007-12-12 2013-07-01 Sony Corp Memory device and information re - recording method
US8369128B2 (en) * 2007-12-12 2013-02-05 Sony Corporation Storage device and information rerecording method
US8830730B2 (en) 2008-08-20 2014-09-09 Panasonic Corporation Variable resistance nonvolatile storage device and method of forming memory cell
US8553444B2 (en) 2008-08-20 2013-10-08 Panasonic Corporation Variable resistance nonvolatile storage device and method of forming memory cell
US20110044088A1 (en) * 2008-08-20 2011-02-24 Shunsaku Muraoka Variable resistance nonvolatile storage device and method of forming memory cell
US7889572B2 (en) * 2008-09-04 2011-02-15 Macronix International Co., Ltd. Memory with high reading performance and reading method thereof
US20100054045A1 (en) * 2008-09-04 2010-03-04 Macronix International Co., Ltd. Memory and Reading Method Thereof
US20100271860A1 (en) * 2008-09-30 2010-10-28 Shunsaku Muraoka Driving method of variable resistance element, initialization method of variable resistance element, and nonvolatile storage device
US8345465B2 (en) 2008-09-30 2013-01-01 Panasonic Corporation Driving method of variable resistance element, initialization method of variable resistance element, and nonvolatile storage device
US8144499B2 (en) * 2009-01-22 2012-03-27 Sony Corporation Variable resistance memory device
US20100182820A1 (en) * 2009-01-22 2010-07-22 Sony Corporation Variable resistance memory device
US8369173B2 (en) * 2009-02-26 2013-02-05 Samsung Electronics Co., Ltd. Semiconductor devices and methods for changing operating characteristics and semiconductor systems including the same
US20100214862A1 (en) * 2009-02-26 2010-08-26 Ho Jung Kim Semiconductor Devices and Methods for Changing Operating Characteristics and Semiconductor Systems Including the Same
US8711649B2 (en) 2009-02-26 2014-04-29 Samsung Electronics Co., Ltd. Semiconductor devices and methods for changing operating characteristics and semiconductor systems including the same
US8563962B2 (en) 2009-12-28 2013-10-22 Panasonic Corporation Memory device and method of manufacturing the same
US9570171B2 (en) * 2010-10-29 2017-02-14 Rambus Inc. Resistance change memory cell circuits and methods
US9818480B2 (en) 2010-10-29 2017-11-14 Rambus Inc. Resistance change memory cell circuits and methods
US11848050B2 (en) 2010-10-29 2023-12-19 Hefei Reliance Memory Limited Resistance change memory cell circuits and methods
US20160019962A1 (en) * 2010-10-29 2016-01-21 Rambus Inc. Resistance change memory cell circuits and methods
US10699786B2 (en) 2010-10-29 2020-06-30 Hefei Reliance Memory Limited Resistance change memory cell circuits and methods
US10902915B2 (en) 2010-10-29 2021-01-26 Hefei Reliance Memory Limited Resistance change memory cell circuits and methods
US11380396B2 (en) 2010-10-29 2022-07-05 Hefei Reliance Memory Limited Resistance change memory cell circuits and methods
US10297320B2 (en) 2010-10-29 2019-05-21 Hefei Reliance Memory Limited Resistance change memory cell circuits and methods
US20150269983A1 (en) * 2011-03-23 2015-09-24 Kabushiki Kaisha Toshiba Semiconductor memory device
US9165628B2 (en) * 2011-03-23 2015-10-20 Kabushiki Kaisha Toshiba Semiconductor memory device
US8885399B2 (en) * 2011-03-29 2014-11-11 Nxp B.V. Phase change memory (PCM) architecture and a method for writing into PCM architecture
US20120250401A1 (en) * 2011-03-29 2012-10-04 Nxp B.V. Phase change memory (pcm) architecture and a method for writing into pcm architecture
TWI502589B (zh) * 2012-03-26 2015-10-01 Toshiba Kk 非揮發性半導體記憶裝置
US9424915B2 (en) 2012-03-26 2016-08-23 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device
TWI575525B (zh) * 2012-03-26 2017-03-21 東芝股份有限公司 非揮發性半導體記憶裝置
US20130250654A1 (en) * 2012-03-26 2013-09-26 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device
US8804401B2 (en) * 2012-03-26 2014-08-12 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device
US9111610B2 (en) 2012-04-20 2015-08-18 Panasonic Intellectual Property Management Co., Ltd. Method of driving nonvolatile memory element and nonvolatile memory device
US9218878B2 (en) 2012-11-20 2015-12-22 Elpida Memory, Inc. Semiconductor device and control method for semiconductor device
US20150109850A1 (en) * 2013-10-23 2015-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Memory devices
US9899079B2 (en) 2013-10-23 2018-02-20 Taiwan Seminconductor Manufacturing Co., Ltd. Memory devices
US9286974B2 (en) * 2013-10-23 2016-03-15 Taiwan Semiconductor Manufacturing Co., Ltd. Memory devices
US9553131B2 (en) 2014-08-19 2017-01-24 Renesas Electronics Corporation Semiconductor device and forming method
US9773538B2 (en) * 2015-09-15 2017-09-26 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
US20170076773A1 (en) * 2015-09-15 2017-03-16 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
US10896699B1 (en) 2019-07-11 2021-01-19 Samsung Electronics Co., Ltd. Memory devices including switch circuit that operates regardless of power supply voltage

Also Published As

Publication number Publication date
US20040264244A1 (en) 2004-12-30
EP1486985A3 (en) 2005-08-24
DE602004008833T2 (de) 2008-06-12
KR100547969B1 (ko) 2006-02-02
CN1574076A (zh) 2005-02-02
EP1486985A2 (en) 2004-12-15
DE602004008833D1 (de) 2007-10-25
JP4113493B2 (ja) 2008-07-09
JP2005025914A (ja) 2005-01-27
KR20040107435A (ko) 2004-12-20
TWI237271B (en) 2005-08-01
EP1486985B1 (en) 2007-09-12
TW200506949A (en) 2005-02-16
CN100479057C (zh) 2009-04-15

Similar Documents

Publication Publication Date Title
US6995999B2 (en) Nonvolatile semiconductor memory device and control method thereof
JP4594878B2 (ja) 可変抵抗素子の抵抗制御方法及び不揮発性半導体記憶装置
KR100692262B1 (ko) 비휘발성 반도체 메모리장치
US7209379B2 (en) Storage device and semiconductor device
US7145791B2 (en) Memory device having variable resistive memory element
JP5028011B2 (ja) 二種の抵抗体を含む不揮発性メモリ素子
US8059448B2 (en) Semiconductor memory device with variable resistance elements
JP4460552B2 (ja) 半導体記憶装置
JP4221031B2 (ja) 不揮発性半導体記憶装置及びその書き換え方法
US7719873B2 (en) Memory and semiconductor device with memory state detection
JP4546842B2 (ja) 不揮発性半導体記憶装置及びその制御方法
JP4157582B1 (ja) 半導体記憶装置
US7372718B2 (en) Storage and semiconductor device
JP2008052781A (ja) 半導体記憶装置
JP6256718B2 (ja) 不揮発性半導体記憶装置
WO2014068961A1 (ja) 不揮発性半導体記憶装置
JP4189269B2 (ja) 不揮発性半導体記憶装置、その書き込み・リセット方法、及び、その読み出し方法
JP6653488B2 (ja) 抵抗変化型不揮発性記憶素子のフォーミング方法および抵抗変化型不揮発性記憶装置
CN111599396A (zh) 一种rram电路及rram行形成的方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: SHARP KABUSHIKI KAISHA, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MORIMOTO, HIDENORI;REEL/FRAME:015488/0955

Effective date: 20040519

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: INTELLECTUAL PROPERTIES I KFT., HUNGARY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SHARP KABUSHIKI KAISHA;REEL/FRAME:029598/0529

Effective date: 20120924

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTELLECTUAL PROPERTIES I KFT.;REEL/FRAME:036134/0656

Effective date: 20121008

FPAY Fee payment

Year of fee payment: 12