TWI630621B - 記憶體系統及感測裝置 - Google Patents

記憶體系統及感測裝置 Download PDF

Info

Publication number
TWI630621B
TWI630621B TW106134435A TW106134435A TWI630621B TW I630621 B TWI630621 B TW I630621B TW 106134435 A TW106134435 A TW 106134435A TW 106134435 A TW106134435 A TW 106134435A TW I630621 B TWI630621 B TW I630621B
Authority
TW
Taiwan
Prior art keywords
memory
selector
input terminal
coupled
path
Prior art date
Application number
TW106134435A
Other languages
English (en)
Other versions
TW201901674A (zh
Inventor
吳柏慶
Original Assignee
力旺電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 力旺電子股份有限公司 filed Critical 力旺電子股份有限公司
Application granted granted Critical
Publication of TWI630621B publication Critical patent/TWI630621B/zh
Publication of TW201901674A publication Critical patent/TW201901674A/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0042—Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/4013—Memory devices with multiple cells per bit, e.g. twin-cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0041—Control circuits in which a clock signal is selectively enabled or disabled
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H02M1/007—Plural converter units in cascade
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H02M3/075—Charge pumps of the Schenkel-type including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/159—Applications of delay lines not covered by the preceding subgroups
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Landscapes

  • Power Engineering (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nonlinear Science (AREA)
  • Read Only Memory (AREA)
  • Dc-Dc Converters (AREA)
  • Semiconductor Memories (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

一種記憶體系統包含第一記憶體組、第一路徑選擇器、第二記憶體組、第二路徑選擇器及感測裝置。第一記憶體組包含複數個第一記憶體單元。第二記憶體組包含複數個第二記憶體單元。第一路徑選擇器包含經由複數條第一位元線耦接至複數個第一記憶體單元的複數個輸入端，以及兩個輸出端。第二路徑選擇器包含經由複數條第二位元線耦接至複數個第二記憶體單元的複數個輸入端，以及兩個輸出端。感測裝置耦接於第一路徑選擇器及第二路徑選擇器的輸出端，並根據操作的需要感測參考電流源及兩個路徑選擇器之輸出端中對應兩股電流的差值。

Description

記憶體系統及感測裝置
本發明係有關於一種記憶體系統，特別是能夠具有低耗能讀取操作的記憶體系統。
目前行動電子裝置常被用來執行各種應用，例如看影片、照相、聽音樂…等等。為了能夠支援更多的應用，行動電子裝置常需要大量的記憶體空間，因此如何使行動電子裝置搭載大量的記憶體空間成為設計行動電子裝置的關鍵之一。
然而，隨著記憶體空間的成長，操作記憶體所需的電能也隨著增加。舉例來說，當更多的記憶體單元被嵌入在單一記憶體組(memory bank)時，記憶體組的每一條位元線都會耦接至更多的記憶體單元。在此情況下，若欲經由一條位元線從其中之一記憶體單元讀出儲存資料，則此記憶體單元所產生的讀取電流就必須先對耦接至這條位元線的其他記憶體單元之寄生電容進行充電，最終才能被判別讀取。如此一來，讀取電流會被減弱而不易判別，並且因為位元線上的充電路徑較長，導致讀取速度降低。為解決此一問題，先前技術會使記憶體單元所產生的讀取電流增強，然而，如此又將導致記憶體單元的耗能增加，而與行動電子裝置的低耗能需求相牴觸。
本發明之一實施例提供一種記憶體系統，記憶體系統包含第一記憶體組、第一路徑選擇器、第二記憶體組、第二路徑選擇器及感測裝置。
第一記憶體組包含N條第一位元線，N為大於1之正整數。第一路徑選擇器包含N個輸入端、第一輸出端及第二輸出端。第一路徑選擇器的N個輸入端耦接於N條第一位元線。
第二記憶體組包含N條第二位元線。第二路徑選擇器包含N個輸入端、第一輸出端及第二輸出端。第二路徑選擇器的N個輸入端耦接於N條第二位元線。
感測裝置包含第一記憶體組選擇器、第二記憶體組選擇器及差動感測放大器。第一記憶體組選擇器具有第一輸入端、第二輸入端及輸出端，第一記憶體組選擇器的第一輸入端耦接於第一路徑選擇器之第一輸出端，而第一記憶體組選擇器的第二輸出端耦接於第二路徑選擇器之第一輸出端。第二記憶體組選擇器具有第一輸入端、第二輸入端及輸出端，第二記憶體組選擇器的第一輸入端耦接於第一路徑選擇器之第二輸出端，而第二記憶體組選擇器的第二輸出端耦接於第二路徑選擇器之第二輸出端。差動感測放大器具有第一輸入端及第二輸入端，差動感測放大器的第一輸入端耦接於第一記憶體組選擇器之輸出端，而差動感測放大器的第二輸入端耦接於第二記憶體組選擇器之輸出端。
在選定之第一位元線的檢測操作或邊界讀取(margin read)操作期間，第一記憶體組選擇器及第一路徑選擇器建立差動感測放大器之第一輸入端及選定之第一位元線之間的電性連接，而第二記憶體組選擇器及第二路徑選擇器建立差動感測放大器之第二輸入端及N條第二位元線中之第二位元線之間的電性連接。
本發明之另一實施例提供一種感測裝置，感測裝置包含第一記憶體組選擇器、第二記憶體組選擇器及差動感測放大器。
第一記憶體組選擇器具有第一輸入端、第二輸入端及輸出端，第一記憶體組選擇器的第一輸入端耦接於第一記憶體單元，而第一記憶體組選擇器的第二輸出端耦接於一第二記憶體單元。第二記憶體組選擇器具有第一輸入端、第二輸入端及輸出端，第二記憶體組選擇器的第一輸入端耦接於第三記憶體單元，而第二記憶體組選擇器的第二輸出端耦接於第四記憶體單元。差動感測放大器具有第一輸入端及第二輸入端，差動感測放大器的第一輸入端耦接於第一記憶體組選擇器之輸出端，而差動感測放大器的第二輸入端耦接於第二記憶體組選擇器之輸出端。
第1圖為本發明一實施例之記憶體系統10的示意圖。記憶體系統10包含第一記憶體組(memory bank)MBA、第一路徑選擇器YP1、第二記憶體組MBB、第二路徑選擇器YP2及感測裝置100。
第一記憶體組MBA包含MxN個第一記憶體單元MCA(1,1)至MCA(M,N)，及N條第一位元線BLA至BLAN，其中M為正整數，N為大於1的正整數。每一條第一位元線BLA1至BLAN可耦接於MxN個第一記憶體單元MCA(1,1)至MCA(M,N)中的M個第一記憶體單元。第一路徑選擇器YP1包含N個輸入端、第一輸出端OA1及第二輸出端OA2。第一路徑選擇器YP1的N個輸入端分別耦接於N條第一位元線BLA至BLAN中對應的一條第一位元線。
第二記憶體組MBB包含MxN個第二記憶體單元MCB(1,1)至MCB(M,N)，及N條第二位元線BLB至BLBN。每一條第二位元線BLB1至BLBN可耦接於MxN個第二記憶體單元MCB(1,1)至MCB(M,N)中的M個第二記憶體單元。第二路徑選擇器YP2包含N個輸入端、第一輸出端OB1及第二輸出端OB2。第二路徑選擇器YP2的N個輸入端分別耦接於N條第二位元線BLA至BLAN中對應的一條第二位元線。
感測裝置100耦接於第一路徑選擇器YP1的第一輸出端OA1、第一路徑選擇器YP1的第二輸出端OA2、第二路徑選擇器YP2的第一輸出端OB1及第二路徑選擇器YP2的第一輸出端OB2。感測裝置100可感測所接收之電流的差異。藉由感測電流差異，便能夠判別出第一記憶體單元MCA(1,1)至MCA(M,N)及第二記憶體單元MCB(1,1)至MCB(M,N)中所儲存的資料。
在部分實施例中，第一記憶體組MBA中每M個第一記憶體單元會耦接於同一字元線。舉例來說，第一記憶體單元MCA(1,1)至MCA(1,N)可耦接於字元線WLA1，而第一記憶體單元MCA(M,1)至MCA(M,N)可耦接於字元線WLAM。在此情況下，第一記憶體單元MCA(1,1)至MCA(1,N)可同步被導通，而第一記憶體單元MCA(M,1)至MCA(M,N)也可同步被導通。
雖然每一條字元線WLA1至WLAM可平行地逐列設置，然而第一記憶體組MBA的布局也可能根據系統需求而變動。舉例來說，在部分實施例中，也可將複數條字元線設置於相同一列，使得第一記憶體組MBA的布局接近正方形，減少整體字元線及位元線所需的繞線總長度。
此外，第一記憶體單元MCA(1,1)至MCA(M,N)可包含第一組第一記憶體單元MSA1及第二組第一記憶體單元MSA2，而儲存在第一組第一記憶體單元MSA1中的資料會與儲存在第二組第一記憶體單元MSA2中的資料互補。舉例來說，若N為正偶數，而n為N/2，則第一組第一記憶體單元MSA1可包含第一記憶體單元MCA(1,1)至MCA(M,n)而第二組第一記憶體單元MSA2可包含第一記憶體單元MCA(1,n+1)至MCA(M,N)。若M≧j≧1且n≧k≧1，則其中第一記憶體單元MCA(j,k)會與第一記憶體單元MCA(j,n+k)相對應。也就是說，第一記憶體單元MCA(j,k)中儲存的資料會與第一記憶體單元MCA(j,n+k)中儲存的資料為互補。
在此情況下，在選定之第一記憶體單元，例如第一記憶體單元MCA(1,1)的讀取操作期間，除了選定之第一記憶體單元MCA(1,1)會產生讀取電流之外，儲存資料與第一記憶體單元MCA(1,1)之資料互補的第一記憶體單元MCA(1,n+1)也會對應產生讀取電流，因此感測裝置100便能夠藉由判讀兩股讀取電流的差異來辨別選定之第一記憶體單元中所儲存的資料。
由於儲存在兩個對應的第一記憶體單元MCA(1,1)及MCA(1,n+1)的資料為彼此互補，因此兩個第一記憶體單元MCA(1,1)及MCA(1,n+1)所產生的讀取電流也會相異。舉例來說，若第一記憶體單元MCA(1,1)為寫入狀態，而第一記憶體單元MCA(1,n+1)為清除狀態，則第一記憶體單元MCA(1,1)可能不會產生讀取電流，或僅產生微量的讀取電流，而第一記憶體單元MCA(1,n+1)則會產生足以辨識的讀取電流。第一記憶體單元MCA(1,1)及MCA(1,n+1)所產生之電流間的差異能夠讓感測裝置100更快速且更準確的判別儲存資訊。
相似地，第二記憶體組MBB可與第一記憶體組MBA具有相同的結構，亦即第二記憶體組MBB中每M個第二記憶體單元可耦接於同一字元線。舉例來說，第二記憶體單元MCB(1,1)至MCB(1,N)可耦接於字元線WLB1，而第二記憶體單元MCB(M,1)至MCB(M,N)可耦接於字元線WLBM。此外，第二記憶體單元MCB(1,1)至MCB(M,N)可包含第一組第二記憶體單元MSB1及第二組第二記憶體單元MSB2，而儲存在第一組第二記憶體單元MSB1中的資料會與儲存在第二組第二記憶體單元MSB2中的資料互補。
舉例來說，第一組第二記憶體單元MSB1可包含第二記憶體單元MCB(1,1)至MCB(M,n)而第二組第二記憶體單元MSB2可包含第二記憶體單元MCB(1,n+1)至MCB(M,N)。其中第二記憶體單元MCB(j,k)會與第二記憶體單元MCB(j,n+k)相對應。也就是說，第二記憶體單元MCB(j,k)中儲存的資料會與第二記憶體單元MCB(j,n+k)中儲存的資料為互補。
在此情況下，為確保感測裝置100能夠感測選定記憶體單元及其對應之記憶體單元(例如第一記憶體單元MCA(1,1)及其所對應之第一記憶體單元MCA(1,n+1))所產生的電流差異，記憶體系統10可利用字元線WLA1導通第一記憶體單元MCA(1,1)至MCA(1,N)，第一路徑選擇器YP1可進一步透過位元線BLA1至BLAN選擇所需的第一記憶體單元MCA(1,1)及第一記憶體單元MCA(1,n+1)，而感測裝置100便能夠選擇第一記憶體單元MCA(1,1)及第一記憶體單元MCA(1,n+1)所屬的記憶體組。
第2圖為本發明一實施例之感測裝置100的示意圖。感測裝置100包含第一記憶體組選擇器112A、第二記憶體組選擇器112B及差動感測放大器114。
第一記憶體組選擇器112A具有第一輸入端112A1、第二輸入端112A2及輸出端，第一記憶體組選擇器112A的第一輸入端112A1耦接於第一路徑選擇器YP1的第一輸出端OA1，第一記憶體組選擇器112A的第二輸入端112A2耦接於第二路徑選擇器YP2的第一輸出端OB1。第二記憶體組選擇器112B具有第一輸入端112B1、第二輸入端112B2及輸出端，第二記憶體組選擇器112B的第一輸入端112B1耦接於第一路徑選擇器YP1的第二輸出端OA2，第二記憶體組選擇器112B的第二輸入端112A2耦接於第二路徑選擇器YP2的第二輸出端OB2。差動感測放大器114具有第一輸入端SA1及第二輸入端SA2，差動感測放大器114的第一輸入端SA1耦接於第一記憶體組選擇器112A的輸出端，差動感測放大器114的第二輸入端SA2耦接於第二記憶體組選擇器112B的輸出端。
第3圖為第一記憶體單元記憶體MCA(1,1)被選定進行讀取操作時，記憶體系統10的電流路徑圖。在第一記憶體單元記憶體MCA(1,1)的讀取操作期間，第一路徑選擇器YP1可在第一路徑選擇器YP1中耦接至選定之第一記憶體單元記憶體MCA(1,1)的輸入端及第一輸出端OA1之間建立電性連接，並可在第一路徑選擇器YP1中耦接至對應於第一記憶體單元記憶體MCA(1,1)之第一記憶體單元記憶體MCA(1,n+1)的輸入端及第二輸出端OA2之間建立電性連接。
第一記憶體組選擇器112A可在第一記憶體組選擇器112A之第一輸入端112A1及第一記憶體組選擇器112A之輸出端之間建立電性連接。此外，第二記憶體組選擇器112B可在第二記憶體組選擇器112B之第一輸入端112B1及第二記憶體組選擇器112B之輸出端之間建立電性連接。
如此一來，差動感測放大器114便能夠接收第一記憶體單元MCA(1,1)及MCA(1,n+1)所產生的讀取電流Ir1及Ir(n+1)，而透過感測讀取電流Ir1及Ir(n+1)的差異就能夠判斷儲存在第一記憶體單元MCA(1,1)中的資料。此外，相似的操作原理也可以應用在讀取第二記憶體組MBB之第二記憶體單元中的資料。
在部分實施例中，差動感測放大器114可包含預充電電路114A，預充電電路114A可在感測電流之前將差動感測放大器114的第一輸入端SA1及第二輸入端SA2預先充電至預定的電壓，使得耦接至欲讀取的兩個對應記憶體單元的位元線能夠透過記憶體組選擇器112A及112B及路徑選擇器被預充電至預定的電壓，以確保維持感測的精確度及讀取速度。
舉例來說，預充電電路114A可包含第一N型電晶體及第二N型電晶體。第一N型電晶體具有汲極端及源極端，第一N型電晶體的汲極端耦接於提供預定電壓的電壓源，第一N型電晶體的源極端則耦接於差動感測放大器114的第一輸入端SA1。第二N型電晶體具有汲極端及源極端，第二N型電晶體的汲極端耦接於可提供預定電壓的電壓源，第二N型電晶體的源極端則耦接於差動感測放大器114的第二輸入端SA2。
然而，若充電電路114A是在記憶體單元MCA(1,1)及MCA(1,n+1)皆被導通且與記憶體單元MCA(1,1)及 MCA(1,n+1)之間的電性連接也已建立的情況下進行預充電，則可能會產生漏電流。因此，為了減少漏電流，差動感測放大器114可在第一路徑選擇器YP1建立所需的電性連接之後進行預充電，而字元線WLA1則可在預充電電路114A完成預充電並截止之後，再將選定之第一記憶體單元MCA(1,1)及其對應的第一記憶體單元MCA(1,n+1)導通。也就是說，第一記憶體單元MCA(1,1)及MCA(1,n+1)可在差動感測放大器114完成預充電之後才被導通，因此可避免在預充電的操作期間因產生短路路徑而造成漏電。
然而，在部分實施例中，差動感測放大器114可為栓鎖器型(latch type)的放大器。在此情況下。差動感測放大器114可在第一路徑選擇器YP1建立所需之電性連接之後進行預充電，且字元線WLA1可在差動感測放大器114進行預充電之前導通選定之第一記憶體單元MCA(1,1)及對應之第一記憶體單元MCA(1,n+1)。
由於感測裝置100可感測第一路徑選擇器YP1之第一輸出端OA1及第二輸出端OA2的電流差異，又或是感測第二路徑選擇器YP2之第一輸出端OB1及第二輸出端OB2的電流差異，因此記憶體系統10可以利用感測裝置100來判讀儲存在兩個記憶體組MBA及MBB中的資訊。也就是說，在儲存相同資料量的情況下，先前技術的記憶體系統須利用單一塊大型的記憶體組，而記憶體系統10則可利用兩塊較小的記憶體組來實作。因此，在記憶體系統10中，每一條位元線上所耦接的記憶體單元會較先前技術來得少，進而減少位元線上的寄生電容並減少電能損耗。
再者，在部分實施例中，感測裝置100可進一步感測第一路徑選擇器YP1之第一輸出端OA1之電流、第一路徑選擇器YP1之第二輸出端OA2之電流、第二路徑選擇器YP2之第一輸出端OB1之電流及第二路徑選擇器YP2之第二輸出端OB2之電流四者之一與參考電流的差異。舉例來說，當記憶體系統10在寫入操作或清除操作之後，執行檢測操作以確認寫入操作或清除操作是否正確執行時，又或是記憶體系統10在讀取電流較小而不易判別的狀況下，執行邊界讀取操作以判讀資料時，記憶體系統10都可能會需要將選定之記憶體單元產生的電流與參考電流相比較。
在第2圖中，感測裝置100可另包含參考電流源116、第一感測選擇器118A及第二感測選擇器118B。感測電流源116可產生參考電流Iref。第一感測選擇器118A可耦接於感測電流源116及差動感測放大器114的第一輸入端SA1。第二感測選擇器118B可耦接於感測電流源116及差動感測放大器114的第二輸入端SA2。在部分實施例中，感測選擇器118A及118B可為類比的多工器或開關切換電路。
第4圖為第一記憶體單元記憶體MCA(1,1)被選定進行檢測操作或邊界讀取操作時，記憶體系統10的電流路徑圖。
在第一記憶體單元記憶體MCA(1,1)的檢測操作或邊界讀取操作期間，第一路徑選擇器YP1可在第一路徑選擇器YP1之N輸入端中耦接於選定之第一記憶體單元MCA(1,1)的輸入端及第一路徑選擇器YP1之第一輸出端OA1之間建立電性連接。第二路徑選擇器YP2可在第二路徑選擇器YP2之一輸入端及第二路徑選擇器YP2之第二輸出端OB2之間建立電性連接。第一記憶體組選擇器112A可在第一記憶體組選擇器112A之第一輸入端112A1及第一記憶體組選擇器112A之輸出端之間建立電性連接。第二記憶體組選擇器112B可在第二記憶體組選擇器112B之第二輸入端112B2及第二記憶體組選擇器112B之輸出端之間建立電性連接。此外，第二感測選擇器118B可在參考電流源116及差動感測放大器114之第二輸入端之間建立電性連接。
如此一來，差動感測放大器114便能接收到由第一記憶體單元MCA(1,1)產生之讀取電流Ir1以及參考電流源116所產生的參考電流Iref。
此外，雖然差動感測放大器114的第二輸入端可接收參考電流Iref而非第二記憶體單元MCB(1,1)至MCB(M,N)所產生的讀取電流，然而第二記憶體組選擇器112B及第二路徑選擇器YP2仍可建立對應的電性連接。透過第二記憶體組選擇器112B及第二路徑選擇器YP2所建立的電性連接能夠有助於提供匹配的等效電容。
舉例來說，自差動感測放大器114經第一記憶體組選擇器112A及第一路徑選擇器YP1至第一路徑選擇器YP1之輸入端之路徑的等效電容實質上可等於自差動感測放大器114經第二記憶體組選擇器112B及第二路徑選擇器YP2至第二路徑選擇器YP2之輸入端之路徑的等效電容。因此，第一記憶體單元MCA(1,1)所產生的讀取電流與參考電流源116所產生之參考電流Iref會具有相匹配的負載，藉以提升檢測操作及邊界讀取操作的準確度。
此外，為減少漏電流，差動感測放大器114可在第一路徑選擇器YP1建立電性連接之後進行預充電，而字元線WLA1則可在差動感測放大器114完成預充電之後將第一記憶體單元MCA(1,1)導通。
然而，在部分實施例中，差動感測放大器114可為栓鎖器型(latch type)的放大器。在此情況下。差動感測放大器114可在第一路徑選擇器YP1建立所需之電性連接之後進行預充電，且字元線WLA1可在差動感測放大器114進行預充電之前導通選定之第一記憶體單元MCA(1,1)。
利用感測選擇器118A及118B，差動感測放大器114就能夠在檢測操作期間或邊界讀取操作期間接收參考電流Iref，而不會在第3圖的讀取操作期間接收參考電流Iref。
綜上所述，本發明之實施例所提供的記憶體系統及感測裝置能夠感測相異記憶體組的讀取電流，因此能夠減少單一位元線上的記憶體單元數量。如此一來，記憶體系統便能以較低的讀取電流操作。此外，當執行檢測操作或邊界讀取操作時，記憶體系統及感測裝置也能夠提供匹配的負載，以提升操作的準確度。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10‧‧‧記憶體系統
100‧‧‧感測裝置
MBA‧‧‧第一記憶體組
MBB‧‧‧第二記憶體組
MCA(1,1)至MCA(M,N)‧‧‧第一記憶體單元
MCB(1,1)至MCB(M,N)‧‧‧第二記憶體單元
YP1‧‧‧第一路徑選擇器
YP2‧‧‧第二路徑選擇器
OA1、OB1、OA2、OB2‧‧‧輸出端
BLA1至BLAN‧‧‧第一位元線
BLB1至BLBN‧‧‧第二位元線
MSA1‧‧‧第一組第一記憶體單元
MSA2‧‧‧第二組第一記憶體單元
MSB1‧‧‧第一組第二記憶體單元
MSB2‧‧‧第二組第二記憶體單元
WLA1至WLAN、WLB1至WLBN‧‧‧字元線
112A‧‧‧第一記憶體組選擇器
112B‧‧‧第二記憶體組選擇器
112A1、112B1、112A2、112B2、‧‧‧輸入端
SA1、SA2 114‧‧‧差動感測放大器
114A‧‧‧預充電電路
116‧‧‧參考電流源
118A‧‧‧第一感測選擇器
118B‧‧‧第二感測選擇器
Iref‧‧‧參考電流
Ir1、Ir(n+1)‧‧‧讀取電流
第1圖為本發明一實施例之記憶體系統的示意圖。 第2圖為本發明一實施例之感測裝置的示意圖。 第3圖為第1圖之第一記憶體單元記憶體被選定進行讀取操作時，記憶體系統的電流路徑圖。 第4圖為第1圖之第一記憶體單元記憶體被選定進行檢測操作或邊界讀取操作時，記憶體系統的電流路徑圖。

Claims (15)

  1. 一種記憶體系統，包含：一第一記憶體組，包含N條第一位元線，N為大於1之正整數；一第一路徑選擇器，包含：N個輸入端，耦接於該N條第一位元線；一第一輸出端；及一第二輸出端；一第二記憶體組，包含N條第二位元線；一第二路徑選擇器，包含：N個輸入端，耦接於該N條第二位元線；一第一輸出端；及一第二輸出端；及一感測裝置，包含：一第一記憶體組選擇器，具有一第一輸入端耦接於該第一路徑選擇器之該第一輸出端，一第二輸入端耦接於該第二路徑選擇器之該第一輸出端，及一輸出端；一第二記憶體組選擇器，具有一第一輸入端耦接於該第一路徑選擇器之該第二輸出端，一第二輸入端耦接於該第二路徑選擇器之該第二輸出端，及一輸出端；及一差動感測放大器，具有一第一輸入端耦接於該第一記憶體組選擇器之該輸出端，一第二輸入端耦接於該第二記憶體組選擇器之該輸出端；其中在一選定之第一位元線的一檢測操作或一邊界讀取(margin read)操作期間：該第一記憶體組選擇器及該第一路徑選擇器建立該差動感測放大器之該第一輸入端及該選定之第一位元線之間的一電性連接；及該第二記憶體組選擇器及該第二路徑選擇器建立該差動感測放大器之該第二輸入端及該N條第二位元線中之一第二位元線之間的一電性連接。
  2. 如請求項1所述之記憶體系統，其中：該第一記憶體組另包含MxN個第一記憶體單元，且該N條第一位元線中每一條第一位元線係耦接於該MxN個第一記憶體單元中的M個第一記憶體單元，其中M為正整數；及該第二記憶體組另包含MxN個第二記憶體單元，且該N條第二位元線中每一條第二位元線係耦接於該MxN個第二記憶體單元中的M個第二記憶體單元。
  3. 如請求項2所述之記憶體系統，其中：該MxN個第一記憶體單元包含一第一組第一記憶體單元及一第二組第一記憶體單元，且該第一組第一記憶體單元中所儲存的資料與該第二組第一記憶體單元中所儲存的資料為互補；及該MxN個第二記憶體單元包含一第一組第二記憶體單元及一第二組第二記憶體單元，且該第一組第二記憶體單元中所儲存的資料與該第二組第二記憶體單元中所儲存的資料為互補。
  4. 如請求項3所述之記憶體系統，其中在該第一組第一記憶體之一選定之第一記憶體單元的一讀取操作期間：該第一路徑選擇器於該第一路徑選擇器之該N輸入端中耦接於該選定之第一記憶體單元的一輸入端及該第一路徑選擇器之該第一輸出端之間建立一第一電性連接，並於該第一路徑選擇器之該N輸入端中耦接於該第二組第一記憶體單元中與該選定之第一記憶體單元互補之一第一記憶體單元的一輸入端及該第一路徑選擇器之該第二輸出端之間建立一第二電性連接；該第一記憶體組選擇器於該第一記憶體組選擇器之該第一輸入端及該第一記憶體組選擇器之該輸出端之間建立一電性連接；及該第二記憶體組選擇器於該第二記憶體組選擇器之該第一輸入端及該第二記憶體組選擇器之該輸出端之間建立一電性連接。
  5. 如請求項4所述之記憶體系統，其中該選定之第一記憶體單元及與該選定之第一記憶體單元互補之該第一記憶體單元係耦接於相同之一字元線。
  6. 如請求項5所述之記憶體系統，其中：該差動感測放大器係在該第一路徑選擇器建立該第一電性連接及該第二電性連接之後進行預充電；及該字元線係在該差動感測放大器進行預充電之後導通該選定之第一記憶體單元及與該選定之第一記憶體單元互補之該第一記憶體單元。
  7. 如請求項2所述之記憶體系統，其中感測裝置另包含：一參考電流源，用以產生一感測電流；一第一感測選擇器，耦接於該參考電流源及該感測差動放大器之該第一輸入端；及一第二感測選擇器，耦接於該參考電流源及該感測差動放大器之該第二輸入端。
  8. 如請求項7所述之記憶體系統，在該MxM個第一記憶體單元之一選定之第一記憶體單元的一檢測操作期間或一邊界讀取操作期間：該第一路徑選擇器於該第一路徑選擇器之該N輸入端中耦接於該選定之第一記憶體單元的一輸入端及該第一路徑選擇器之該第一輸出端之間建立一電性連接；該第二路徑選擇器於該第二路徑選擇器之一輸入端及該第二路徑選擇器之該第二輸出端之間建立一電性連接；該第一記憶體組選擇器於該第一記憶體組選擇器之該第一輸入端及該第一記憶體組選擇器之該輸出端之間建立一電性連接；該第二記憶體組選擇器於該第二記憶體組選擇器之該第二輸入端及該第二記憶體組選擇器之該輸出端之間建立一電性連接；及該第二感測選擇器於該參考電流源及該差動感測放大器之該第二輸入端之間建立一電性連接。
  9. 如請求項8所述之記憶體系統，其中：該差動感測放大器係在該第一路徑選擇器建立該電性連接之後進行預充電；及一字元線係在該差動感測放大器進行預充電之後導通該選定之第一記憶體單元。
  10. 如請求項8所述之記憶體系統，其中：該差動感測放大器係為一栓鎖器型(latch type)的放大器，且該差動感測放大器係在該第一路徑選擇器建立該電性連接之後進行預充電；及一字元線係在該差動感測放大器進行預充電之前導通該選定之第一記憶體單元。
  11. 如請求項8所述之記憶體系統，其中自該差動感測放大器經該第一記憶體組選擇器及該第一路徑選擇器至該第一路徑選擇器之該輸入端之一路徑的一等效電容實質上等於自該差動感測放大器經該第二記憶體組選擇器及該第二路徑選擇器至該第二路徑選擇器之該輸入端之一路徑的一等效電容。
  12. 如請求項2所述之記憶體系統，其中：該第一記憶體組另包含M條字元線，每一字元線耦接於該MxN個第一記憶體單元中的N個第一記憶體單元；及該第二記憶體組另包含M條字元線，每一字元線耦接於該MxN個第二記憶體單元中的N個第二記憶體單元。
  13. 一種感測裝置，包含：一第一記憶體組選擇器，具有一第一輸入端耦接於一第一記憶體單元，一第二輸入端耦接於一第二記憶體單元，及一輸出端；一第二記憶體組選擇器，具有一第一輸入端耦接於一第三記憶體單元，一第二輸入端耦接於一第四記憶體單元，及一輸出端；及一差動感測放大器，具有一第一輸入端耦接於該第一記憶體組選擇器之該輸出端，及一第二輸入端耦接於該第二記憶體組選擇器之該輸出端；其中：儲存於該第一記憶體單元的資料與儲存於該第二記憶體單元的資料為互補；及在該第一記憶體單元的一讀取操作期間：該第一記憶體組選擇器於該第一記憶體組選擇器之該第一輸入端及該第一記憶體組選擇器之該輸出端之間建立一電性連接；及該第二記憶體組選擇器於該第二記憶體組選擇器之該第一輸入端及該第二記憶體組選擇器之該輸出端之間建立一電性連接。
  14. 如請求項13所述之感測裝置，另包含：一參考電流源，用以產生一感測電流；一第一感測選擇器，耦接於該參考電流源及該感測差動放大器之該第一輸入端；及一第二感測選擇器，耦接於該參考電流源及該感測差動放大器之該第二輸入端。
  15. 如請求項14所述之感測裝置，其中在該第一記憶體單元的一檢測操作期間或一邊界讀取操作期間：該第一記憶體組選擇器於該第一記憶體組選擇器之該第一輸入端及該第一記憶體組選擇器之該輸出端之間建立一電性連接；該第二記憶體組選擇器於該第二記憶體組選擇器之該第二輸入端及該第二記憶體組選擇器之該輸出端之間建立一電性連接；及該第二感測選擇器於該參考電流源及該差動感測放大器之該第二輸入端之間建立一電性連接。
TW106134435A 2016-05-25 2017-10-06 記憶體系統及感測裝置 TWI630621B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662341105P 2016-05-25 2016-05-25
US15/603,478 US10090027B2 (en) 2016-05-25 2017-05-24 Memory system with low read power
US15/603,478 2017-05-24

Publications (2)

Publication Number Publication Date
TWI630621B true TWI630621B (zh) 2018-07-21
TW201901674A TW201901674A (zh) 2019-01-01

Family

ID=60418184

Family Applications (4)

Application Number Title Priority Date Filing Date
TW106125243A TWI666865B (zh) 2016-05-25 2017-07-27 電荷泵電路
TW106127886A TWI636652B (zh) 2016-05-25 2017-08-17 電荷泵單元及電荷泵電路
TW106133409A TWI630708B (zh) 2016-05-25 2017-09-28 非揮發性記憶體及程式化具有非揮發性記憶體之記憶體陣列的方法
TW106134435A TWI630621B (zh) 2016-05-25 2017-10-06 記憶體系統及感測裝置

Family Applications Before (3)

Application Number Title Priority Date Filing Date
TW106125243A TWI666865B (zh) 2016-05-25 2017-07-27 電荷泵電路
TW106127886A TWI636652B (zh) 2016-05-25 2017-08-17 電荷泵單元及電荷泵電路
TW106133409A TWI630708B (zh) 2016-05-25 2017-09-28 非揮發性記憶體及程式化具有非揮發性記憶體之記憶體陣列的方法

Country Status (5)

Country Link
US (5) US10090027B2 (zh)
EP (1) EP3407355B1 (zh)
JP (2) JP6389925B1 (zh)
CN (4) CN108964444B (zh)
TW (4) TWI666865B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113243031A (zh) * 2018-12-21 2021-08-10 美光科技公司 存储器装置中的多路复用信号开发

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI824467B (zh) 2016-12-14 2023-12-01 成真股份有限公司 標準大宗商品化現場可編程邏輯閘陣列(fpga)積體電路晶片組成之邏輯驅動器
US11625523B2 (en) 2016-12-14 2023-04-11 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips
US10447274B2 (en) 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
US10957679B2 (en) 2017-08-08 2021-03-23 iCometrue Company Ltd. Logic drive based on standardized commodity programmable logic semiconductor IC chips
US10630296B2 (en) 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
US10608642B2 (en) 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10623000B2 (en) 2018-02-14 2020-04-14 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10608638B2 (en) 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
KR102577262B1 (ko) 2018-08-14 2023-09-11 삼성전자주식회사 확산 방지 영역을 갖는 반도체 소자
US10892011B2 (en) 2018-09-11 2021-01-12 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US10937762B2 (en) 2018-10-04 2021-03-02 iCometrue Company Ltd. Logic drive based on multichip package using interconnection bridge
US11616046B2 (en) 2018-11-02 2023-03-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US11056197B2 (en) 2018-11-08 2021-07-06 Samsung Electronics Co., Ltd. Charge pump and memory device including the same
KR20200053324A (ko) * 2018-11-08 2020-05-18 삼성전자주식회사 차지 펌프 및 차지 펌프를 포함하는 메모리 장치
TWI708253B (zh) 2018-11-16 2020-10-21 力旺電子股份有限公司 非揮發性記憶體良率提升的設計暨測試方法
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US10818592B1 (en) * 2019-04-29 2020-10-27 Nanya Technology Corporation Semiconductor memory device including decoupling capacitor array arranged overlying one-time programmable device
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
US10985154B2 (en) 2019-07-02 2021-04-20 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits
US11404415B2 (en) * 2019-07-05 2022-08-02 Globalfoundries U.S. Inc. Stacked-gate transistors
CN110299173B (zh) * 2019-07-05 2021-05-04 合肥联诺科技股份有限公司 一种用于nor flash编程处理的可控放电模块
US11887930B2 (en) 2019-08-05 2024-01-30 iCometrue Company Ltd. Vertical interconnect elevator based on through silicon vias
US11637056B2 (en) 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
US10957701B1 (en) * 2019-11-11 2021-03-23 Globalfoundries U.S. Inc. Fin-based anti-fuse device for integrated circuit (IC) products, methods of making such an anti-fuse device and IC products comprising such an anti-fuse device
US11600526B2 (en) 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
US11328957B2 (en) 2020-02-25 2022-05-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11270780B2 (en) 2020-03-31 2022-03-08 Taiwan Semiconductor Manufacturing Co., Ltd. Memory readout circuit and method
US11183502B1 (en) * 2020-08-20 2021-11-23 Nanya Technology Corporation Memory cell and Method for reading out data therefrom
CN112039335A (zh) * 2020-08-21 2020-12-04 厦门半导体工业技术研发有限公司 一种电压发生器和半导体器件
US20220199622A1 (en) * 2020-12-18 2022-06-23 Ememory Technology Inc. Resistive memory cell and associated cell array structure
CN116137493A (zh) 2021-11-17 2023-05-19 科奇芯有限公司 电荷泵电路
US20230016311A1 (en) * 2021-12-03 2023-01-19 Wuxi Esiontech Co., Ltd. Clock skew-adjustable chip clock architecture of progarmmable logic chip

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6498764B1 (en) * 2001-11-23 2002-12-24 Hynix Semiconductor Inc. Flash memory device having a multi-bank structure
TW200903509A (en) * 2007-03-22 2009-01-16 Toshiba Kk Semiconductor memory device
TW200908002A (en) * 2007-03-30 2009-02-16 Qualcomm Inc Semi-shared sense amplifier and global read line architecture
TWI311761B (en) * 2005-06-24 2009-07-01 Macronix Int Co Ltd Method for refreshing a flash memory and sense amplifier circuit
TWI316254B (en) * 2005-07-25 2009-10-21 Toshiba Kk Semiconductor memory device and a data read method thereof
US20100165755A1 (en) * 2008-12-30 2010-07-01 Stmicroelectronics Pvt. Ltd. Single-ended bit line based storage system
US20110188311A1 (en) * 2010-01-29 2011-08-04 Texas Instruments Incorporated Efficient Memory Sense Architecture
US9111642B2 (en) * 2010-12-28 2015-08-18 Seiko Epson Corporation Non-volatile memory device and electronic apparatus

Family Cites Families (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2537264B2 (ja) 1988-04-13 1996-09-25 株式会社東芝 半導体記憶装置
JP3076606B2 (ja) 1990-12-14 2000-08-14 富士通株式会社 半導体記憶装置およびその検査方法
US5126590A (en) * 1991-06-17 1992-06-30 Micron Technology, Inc. High efficiency charge pump
JP3178946B2 (ja) 1993-08-31 2001-06-25 沖電気工業株式会社 半導体記憶装置及びその駆動方法
JPH0778465A (ja) 1993-09-10 1995-03-20 Oki Micro Design Miyazaki:Kk 半導体集積回路
EP0696839B1 (en) 1994-08-12 1998-02-25 Co.Ri.M.Me. Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Voltage elevator of the charge pump type
KR0142403B1 (ko) * 1994-12-20 1998-07-15 김광호 반도체 메모리장치의 전원승압회로
KR0149220B1 (ko) 1994-12-27 1998-12-01 김주용 챠지 펌프 회로
US5729493A (en) 1996-08-23 1998-03-17 Motorola Inc. Memory suitable for operation at low power supply voltages and sense amplifier therefor
JP3378457B2 (ja) * 1997-02-26 2003-02-17 株式会社東芝 半導体装置
JP3557090B2 (ja) 1998-03-31 2004-08-25 株式会社東芝 半導体記憶装置
US6483377B2 (en) 2001-01-10 2002-11-19 Texas Instruments Incorporated Low slew rate charge pump
US6501325B1 (en) * 2001-01-18 2002-12-31 Cypress Semiconductor Corp. Low voltage supply higher efficiency cross-coupled high voltage charge pumps
US6661682B2 (en) * 2001-02-16 2003-12-09 Imec (Interuniversitair Microelectronica Centrum) High voltage generating charge pump circuit
JP2003077282A (ja) 2001-08-31 2003-03-14 Fujitsu Ltd 不揮発性半導体記憶装置
KR100404001B1 (ko) * 2001-12-29 2003-11-05 주식회사 하이닉스반도체 차지 펌프 회로
KR100538883B1 (ko) * 2003-04-29 2005-12-23 주식회사 하이닉스반도체 반도체 메모리 장치
CN1455574A (zh) * 2003-05-30 2003-11-12 无敌科技(西安)有限公司 选择性信息储存系统及其实现方法
US7411840B2 (en) * 2004-03-02 2008-08-12 Via Technologies, Inc. Sense mechanism for microprocessor bus inversion
US6995603B2 (en) * 2004-03-03 2006-02-07 Aimtron Technology Corp. High efficiency charge pump with prevention from reverse current
JP4727261B2 (ja) 2005-03-16 2011-07-20 三菱電機株式会社 分周回路、電源回路及び表示装置
JP2007034943A (ja) * 2005-07-29 2007-02-08 Sony Corp 共有メモリ装置
US7301380B2 (en) 2006-04-12 2007-11-27 International Business Machines Corporation Delay locked loop having charge pump gain independent of operating frequency
KR20080029696A (ko) * 2006-09-29 2008-04-03 주식회사 하이닉스반도체 리던던시 회로를 구비한 반도체 메모리 장치
CN101154683B (zh) * 2006-09-29 2011-03-30 旺宏电子股份有限公司 晶体管结构及其制造方法
JP4883780B2 (ja) * 2006-11-14 2012-02-22 ルネサスエレクトロニクス株式会社 チャージポンプ回路
KR100818710B1 (ko) * 2006-11-21 2008-04-01 주식회사 하이닉스반도체 전압펌핑장치
TWI331447B (en) 2007-03-20 2010-10-01 Novatek Microelectronics Corp Charge pump circuit
US7446596B1 (en) 2007-05-25 2008-11-04 Atmel Corporation Low voltage charge pump
CN101409554B (zh) * 2007-10-11 2012-05-16 北京朗波芯微技术有限公司 用于电荷泵锁相环的环路滤波电路
KR101102776B1 (ko) 2008-02-13 2012-01-05 매그나칩 반도체 유한회사 비휘발성 메모리 소자의 단위 셀 및 이를 구비한 비휘발성메모리 소자
US7859043B2 (en) * 2008-02-25 2010-12-28 Tower Semiconductor Ltd. Three-terminal single poly NMOS non-volatile memory cell
CN101685677A (zh) * 2008-09-27 2010-03-31 英华达（上海）科技有限公司 闪存检测装置及其方法
US8144537B2 (en) 2008-11-11 2012-03-27 Stmicroelectronics Pvt. Ltd. Balanced sense amplifier for single ended bitline memory architecture
US8742833B2 (en) 2008-12-02 2014-06-03 Himax Technologies Limited Charge pump circuit and method thereof
US8305790B2 (en) 2009-03-16 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical anti-fuse and related applications
TW201203253A (en) 2010-07-06 2012-01-16 Maxchip Electronics Corp One time programmable memory and the manufacturing method and operation method thereof
CN102646387B (zh) * 2011-05-19 2014-09-17 京东方科技集团股份有限公司 移位寄存器及行扫描驱动电路
KR20130093303A (ko) * 2012-02-14 2013-08-22 에스케이하이닉스 주식회사 전하 펌프 장치 및 그 단위 셀
FR2988535B1 (fr) * 2012-03-23 2014-03-07 Soitec Silicon On Insulator Circuit de pompage de charge a transistors munis de portes doubles en phase, et procédé de fonctionnement dudit circuit.
JP5444414B2 (ja) 2012-06-04 2014-03-19 株式会社東芝 磁気ランダムアクセスメモリ
CN103456711B (zh) * 2012-06-05 2016-03-23 中芯国际集成电路制造(上海)有限公司 鳍型反熔丝结构及其制造方法
US9070424B2 (en) 2012-06-29 2015-06-30 Samsung Electronics Co., Ltd. Sense amplifier circuitry for resistive type memory
US9536883B2 (en) * 2012-07-12 2017-01-03 Broadcom Corporation Dual anti-fuse
US9337318B2 (en) * 2012-10-26 2016-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with dummy gate on non-recessed shallow trench isolation (STI)
US9601499B2 (en) * 2013-05-16 2017-03-21 Ememory Technology Inc. One-time programmable memory cell capable of reducing leakage current and preventing slow bit response, and method for programming a memory array comprising the same
TWI502722B (zh) 2013-07-24 2015-10-01 Ememory Technology Inc 改善讀取特性的反熔絲單次可程式記憶胞及記憶體的操作方法
US20150078103A1 (en) * 2013-09-13 2015-03-19 Lsi Corporation Sensing technique for single-ended bit line memory architectures
US20150194433A1 (en) * 2014-01-08 2015-07-09 Broadcom Corporation Gate substantial contact based one-time programmable device
CN104979362B (zh) * 2014-04-10 2019-11-19 三星电子株式会社 具有翅片式有源图案和栅极节点的半导体装置
US9171752B1 (en) 2014-08-12 2015-10-27 Globalfoundries Inc. Product comprised of FinFET devices with single diffusion break isolation structures, and methods of making such a product
US9460761B2 (en) * 2014-08-14 2016-10-04 Stmicroelectronics (Rousset) Sas Lower power sense amplifier for reading non-volatile memory cells
KR102179169B1 (ko) * 2014-09-02 2020-11-18 삼성전자주식회사 반도체 장치 및 반도체 장치의 제조방법
DE102014115433A1 (de) * 2014-10-23 2016-05-12 Infineon Technologies Ag Ladungspumpe
US9491151B2 (en) * 2015-01-07 2016-11-08 Ememory Technology Inc. Memory apparatus, charge pump circuit and voltage pumping method thereof
US9620176B2 (en) 2015-09-10 2017-04-11 Ememory Technology Inc. One-time programmable memory array having small chip area
US10109364B2 (en) 2015-10-21 2018-10-23 Avago Technologies General Ip (Singapore) Pte. Ltd. Non-volatile memory cell having multiple signal pathways to provide access to an antifuse of the memory cell
US9613714B1 (en) * 2016-01-19 2017-04-04 Ememory Technology Inc. One time programming memory cell and memory array for physically unclonable function technology and associated random code generating method
JP6200983B2 (ja) * 2016-01-25 2017-09-20 力旺電子股▲ふん▼有限公司ｅＭｅｍｏｒｙ Ｔｅｃｈｎｏｌｏｇｙ Ｉｎｃ． ワンタイムプログラマブルメモリセル、該メモリセルを含むメモリアレイのプログラム方法及び読み込み方法
US9536991B1 (en) 2016-03-11 2017-01-03 Globalfoundries Inc. Single diffusion break structure
CN107306082B (zh) * 2016-04-18 2020-05-22 晶门科技（深圳）有限公司 电荷泵电路
CN205883044U (zh) * 2016-07-06 2017-01-11 西安紫光国芯半导体有限公司 电荷泵电路及其单级电路
US9589970B1 (en) 2016-08-02 2017-03-07 United Microelectronics Corp. Antifuse one-time programmable memory

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6498764B1 (en) * 2001-11-23 2002-12-24 Hynix Semiconductor Inc. Flash memory device having a multi-bank structure
TWI311761B (en) * 2005-06-24 2009-07-01 Macronix Int Co Ltd Method for refreshing a flash memory and sense amplifier circuit
TWI316254B (en) * 2005-07-25 2009-10-21 Toshiba Kk Semiconductor memory device and a data read method thereof
TW200903509A (en) * 2007-03-22 2009-01-16 Toshiba Kk Semiconductor memory device
TW200908002A (en) * 2007-03-30 2009-02-16 Qualcomm Inc Semi-shared sense amplifier and global read line architecture
US20100165755A1 (en) * 2008-12-30 2010-07-01 Stmicroelectronics Pvt. Ltd. Single-ended bit line based storage system
US20110188311A1 (en) * 2010-01-29 2011-08-04 Texas Instruments Incorporated Efficient Memory Sense Architecture
US9111642B2 (en) * 2010-12-28 2015-08-18 Seiko Epson Corporation Non-volatile memory device and electronic apparatus

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113243031A (zh) * 2018-12-21 2021-08-10 美光科技公司 存储器装置中的多路复用信号开发
US11221797B2 (en) 2018-12-21 2022-01-11 Micron Technology, Inc. Domain-based access in a memory device
TWI762840B (zh) * 2018-12-21 2022-05-01 美商美光科技公司 電子設備及用於記憶體裝置中之多工信號開發之方法
US11340833B2 (en) 2018-12-21 2022-05-24 Micron Technology, Inc. Systems and methods for data relocation using a signal development cache
US11360704B2 (en) 2018-12-21 2022-06-14 Micron Technology, Inc. Multiplexed signal development in a memory device
US11372595B2 (en) 2018-12-21 2022-06-28 Micron Technology, Inc. Read broadcast operations associated with a memory device
US11520529B2 (en) 2018-12-21 2022-12-06 Micron Technology, Inc. Signal development caching in a memory device
US11656801B2 (en) 2018-12-21 2023-05-23 Micron Technology, Inc. Systems and methods for data relocation using a signal development cache
US11669278B2 (en) 2018-12-21 2023-06-06 Micron Technology, Inc. Page policies for signal development caching in a memory device
US11693599B2 (en) 2018-12-21 2023-07-04 Micron Technology, Inc. Domain-based access in a memory device
US11709634B2 (en) 2018-12-21 2023-07-25 Micron Technology, Inc. Multiplexed signal development in a memory device
US11726714B2 (en) 2018-12-21 2023-08-15 Micron Technology, Inc. Content-addressable memory for signal development caching in a memory device
US11934703B2 (en) 2018-12-21 2024-03-19 Micron Technology, Inc. Read broadcast operations associated with a memory device
CN113243031B (zh) * 2018-12-21 2024-05-14 美光科技公司 存储器装置中的多路复用信号开发
US11989450B2 (en) 2018-12-21 2024-05-21 Micron Technology, Inc. Signal development caching in a memory device

Also Published As

Publication number Publication date
US20170346393A1 (en) 2017-11-30
CN108964444B (zh) 2020-05-29
CN108964446B (zh) 2020-08-25
EP3407355B1 (en) 2020-04-29
US20170345464A1 (en) 2017-11-30
US20190147922A1 (en) 2019-05-16
TWI666865B (zh) 2019-07-21
US20170346394A1 (en) 2017-11-30
CN108962332A (zh) 2018-12-07
JP2018201002A (ja) 2018-12-20
US9935113B2 (en) 2018-04-03
CN108964444A (zh) 2018-12-07
JP2018198105A (ja) 2018-12-13
US10003258B2 (en) 2018-06-19
US10090027B2 (en) 2018-10-02
CN108962332B (zh) 2021-03-23
TW201901929A (zh) 2019-01-01
CN108964446A (zh) 2018-12-07
CN108932965B (zh) 2020-12-01
TW201901674A (zh) 2019-01-01
EP3407355A1 (en) 2018-11-28
CN108932965A (zh) 2018-12-04
US10224079B2 (en) 2019-03-05
TW201902096A (zh) 2019-01-01
US20170345828A1 (en) 2017-11-30
US10714155B2 (en) 2020-07-14
TWI636652B (zh) 2018-09-21
TWI630708B (zh) 2018-07-21
JP6389925B1 (ja) 2018-09-12
TW201902097A (zh) 2019-01-01

Similar Documents

Publication Publication Date Title
TWI630621B (zh) 記憶體系統及感測裝置
CN100485808C (zh) 静态随机存取存储器装置及其控制电路及控制方法
US10546630B2 (en) Semiconductor memory device and control method of semiconductor memory device
CN102426852B (zh) 一种存储阵列单元信息读取方法及系统
CN104599700A (zh) 高密度存储器结构
CN101276638B (zh) 具有铁电器件的半导体存储器器件及其更新方法
KR20180019052A (ko) 독출 컬럼 선택 네거티브 부스트 드라이버 회로 및 시스템
TW320723B (en) Semiconductor memory device and testing method thereof
US20110242919A1 (en) Precharge Voltage Supplying Circuit
TW201312566A (zh) 於交叉點陣列中透過耦合電容器之地磚層級突返檢測技術
EP3249654B1 (en) Systems and methods for non-volatile flip flops
TWI825797B (zh) 記憶體裝置及其感測方法
US10262725B1 (en) Selective bit-line sensing method and storage device utilizing the same
CN104952483A (zh) 具有分层位线结构的阻变存储装置
US9064555B2 (en) Secondary bit line equalizer
KR100933861B1 (ko) 불휘발성 메모리 소자 및 그 프로그램 검증 방법
CN100576337C (zh) 用于数据的永久存储的方法和存储设备
KR20110006449A (ko) 계층적 비트라인 구조를 갖는 반도체 메모리 장치 및 그 구동 방법
JP2012009100A (ja) 不揮発性記憶装置
TW201521026A (zh) 非揮發性記憶體
US6885601B2 (en) Memory circuit and method of reading data
KR100355950B1 (ko) 동기식 반도체 기억장치
CN110556148B (zh) 一种3d nand存储器的读取方法及装置
US8429578B2 (en) Method of verifying logic circuit including decoders and apparatus for the same
JP6908997B2 (ja) 半導体記憶装置及びデータ書込方法