CN108964446B - 电荷泵单元及电荷泵电路 - Google Patents

电荷泵单元及电荷泵电路 Download PDF

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CN108964446B
CN108964446B CN201710729296.4A CN201710729296A CN108964446B CN 108964446 B CN108964446 B CN 108964446B CN 201710729296 A CN201710729296 A CN 201710729296A CN 108964446 B CN108964446 B CN 108964446B
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terminal
type transistor
coupled
terminal coupled
charge pump
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CN108964446A (zh
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张武昌
杨政德
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eMemory Technology Inc
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eMemory Technology Inc
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
    • G—PHYSICS
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    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
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    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
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    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
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    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
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    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
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Abstract

本发明公开了一种电荷泵电路包括电压输入端口、电压输出端口、串接于电压输入端口及电压输出端口之间的多个电荷泵单元、时钟信号源及N个时钟延迟组件。时钟信号源产生主要时钟信号，而N个时钟延迟组件延迟主要时钟信号以产生电荷泵单元所需的时钟信号。主要时钟信号的上升沿领先最后一电荷泵单元所接收的最末时钟信号的上升沿，且主要时钟信号的下降沿落后于最末时钟信号的上升沿。每一电荷泵单元包括两组反相器及延迟组件以产生两个互补的时钟信号。

Description

电荷泵单元及电荷泵电路
技术领域
本发明是有关于一种电荷泵电路，尤其是一种具有低逆向电流及低峰值电流的电荷泵电路。
背景技术
为满足电子装置对于低耗能的需求，集成电路(integrated circuits，IC)的电力规格也被重新设计成能够在低电压的环境中操作，以减少电能损耗。举例来说，过去电力规格是5V的集成电路现在常被减至3.3V或甚至低于2V。虽然低电压的操作能够减少电力损耗，然而在部分的情况下，电路仍然需要较高的电压来完成操作。举例来说，闪存就需要较高的电压来进行写入及清除操作。其中较高的电压常会利用电荷泵电路来提供。
现有技术的电荷泵电路常利用互补的时钟信号来控制。互补的时钟信号则常是将主要时钟信号通过两个具有不同数量的反相器的信号路径来产生。然而，由于这两个互补的时钟信号是经由不同的信号路径产生，因此两者的相位差并非180度。也就是说，其中一个时钟信号会领先另一个时钟信号。这样非完美的互补时钟信号将导致电荷泵电路产生逆向电流，并增加电流损耗。此外，为了提供更高的电压，电荷泵电路须具备更多级的电路。在此情况下，倘若未能妥善控制时钟信号，则将导致高峰值电流产生。亦即，随着电荷泵的级数变多，时钟信号的控制也变得更加复杂。
发明内容
本发明的一实施例提供一种电荷泵单元，电荷泵单元包括输入端、输出端、第一N型晶体管、第二N型晶体管、第一P型晶体管、第二P型晶体管、第一电容、第二电容、时钟输入端、P个第一反相器及R个延迟组件。
第一N型晶体管具有第一端、第二端及控制端，第一N型晶体管的第一端耦接于输入端。第二N型晶体管具有第一端、第二端及控制端，第二N型晶体管的第一端耦接于输入端，第二N型晶体管的第二端耦接于第一N型晶体管的控制端，而第二N型晶体管的控制端耦接于第一N型晶体管的第二端。第一P型晶体管具有第一端、第二端及控制端，第一P型晶体管的第一端耦接于第一N型晶体管的第二端，而第一P型晶体管的第二端耦接于输出端。第二P型晶体管具有第一端、第二端及控制端，第二P型晶体管的第一端耦接于第二N型晶体管的第二端及第一P型晶体管的控制端，第二P型晶体管的第二端耦接于输出端，而第二P型晶体管的控制端耦接于第一P型晶体管的第一端。第一电容具有第一端及第二端，第一电容的第一端耦接于第一N型晶体管的第二端。第二电容具有第一端及第二端，第二电容的第一端耦接于第二N型晶体管的第二端。
时钟输入端接收时钟信号。P个第一反相器串联于时钟输入端及第一电容的第二端之间，其中P是正整数。R个延迟组件串联于时钟输入端及第二电容的第二端之间，其中R是正整数。
本发明的另一实施例提供一种电荷泵电路。电荷泵电路包括电压输入端口、电压输出端口、多个电荷泵单元、时钟信号源及N个时钟延迟组件。
电压输入端口接收输入电压，而电压输出端口输出抬升电压。多个电荷泵单元串接于电压输入端口及电压输出端口之间。时钟信号源产生主要时钟信号。N个时钟延迟组件耦接于时钟信号源，并可延迟主要时钟信号以产生多个电荷泵单元中至少一电荷泵单元所需的至少一时钟信号。
多个电荷泵单元中的第一电荷泵单元接收主要时钟信号。主要时钟信号的上升沿领先至少一电荷泵单元中最后一电荷泵单元所接收的最末时钟信号的上升沿，且主要时钟信号的下降沿落后于最末时钟信号的上升沿。
附图说明
图1是本发明一实施例的电荷泵单元的示意图。
图2是图1的电荷泵单元的时钟信号波形图。
图3是本发明一实施例的反相器的示意图。
图4是本发明一实施例的延迟组件的示意图。
图5是本发明一实施例的电荷泵电路的示意图。
图6是图5的电荷泵电路的时钟信号波形图。
图7是本发明另一实施例的电荷泵电路的示意图。
其中，附图标记说明如下：
100、1001至100(2N+2) 电荷泵单元
N1 第一N型晶体管
N2 第二N型晶体管
N3 第三N型晶体管
N4 第四N型晶体管
N5 第五N型晶体管
N6 第六N型晶体管
P1 第一P型晶体管
P2 第二P型晶体管
P3 第三P型晶体管
P4 第四P型晶体管
P5 第五P型晶体管
P6 第六P型晶体管
C1 第一电容
C2 第二电容
110 第一反相器
120 第二反相器
130 延迟组件
WS1 第一井电位切换电路
WS2 第二井电位切换电路
WS3 第三井电位切换电路
WS4 第四井电位切换电路
IT1 第一初始升压晶体管
IT2 第二初始升压晶体管
TT1 第一升压充电晶体管
TT2 第二升压充电晶体管
CLK 时钟输入端
IN 输入端
OUT 输出端
VDD 第一电压
2VDD 第三电压
SIGCLK、SIGCLA、SIGCLKB、SIGCLK1至SIGCLK(N+1) 时钟信号
VSS 第二电压
T1、T2 时段
INV 反相器
INVN、DEN N型晶体管
INVP、DEP P型晶体管
DE 延迟组件
10、20 电荷泵电路
VIN 电压输入端口
VOUT 电压输出端口
12 时钟信号源
141至14N 时钟延迟组件
RE1、RE2、REi、RE(i+1)、RE(N+1) 上升沿
FE1、FE2、FEi、FE(i+1) 下降沿
具体实施方式
图1是本发明一实施例的电荷泵单元100的示意图。电荷泵单元100包括输入端IN、输出端OUT、第一N型晶体管N1、第二N型晶体管N2、第一P型晶体管P1、第二P型晶体管P2、第一电容C1、第二电容C2、时钟输入端CLK、P个第一反相器110、Q个第二反相器120及R个延迟组件130。P是正整数，Q是小于P的正整数或0，而R是正整数。
第一N型晶体管N1具有第一端、第二端、控制端及基体端。第一N型晶体管N1的第一端耦接于输入端IN。第二N型晶体管N2具有第一端、第二端、控制端及基体端。第二N型晶体管N2的第一端耦接于输入端IN，第二N型晶体管N2的第二端耦接于第一N型晶体管N1的控制端，而第二N型晶体管N2的控制端耦接于第一N型晶体管N1的第二端。
第一P型晶体管P1具有第一端、第二端、控制端及基体端。第一P型晶体管P1的第一端耦接于第一N型晶体管N1的第二端，而第一P型晶体管P1的第二端耦接于输出端OUT。第二P型晶体管P2具有第一端、第二端、控制端及基体端。第二P型晶体管P2的第一端耦接于第二N型晶体管N2的第二端及第一P型晶体管P1的控制端，第二P型晶体管P2的第二端耦接于输出端OUT，而第二P型晶体管P2的控制端耦接于第一P型晶体管P1的第一端。
第一电容C1具有第一端及第二端。第一电容C1的第一端耦接于第一N型晶体管N1的第二端。第二电容C2具有第一端及第二端。第二电容C2的第一端耦接于第二N型晶体管N2的第二端。
时钟输入端CLK接收时钟信号SIGCLK。P个第一反相器110可串联于时钟输入端CLK及第一电容C1的第二端之间。Q个第二反相器120及R个延迟组件130可串联于时钟输入端CLK及第二电容C2的第二端之间。
此外，P与Q的差值可为奇数，因此由第一电容C1所接收到的时钟信号SIGCLKA与第二电容C2所接收到的时钟信号SIGCLKB可为互补。举例来说，P可为3，而Q可为2。为确保时钟信号SIGCLKA与时钟信号SIGCLKB之间的相位差保持在180度，R个延迟组件130可与Q个第二反相器120一起串联在时钟输入端CLK及第二电容C2的第二端之间。R个延迟组件130可设计成能够提供适当的延迟，使得P个第一反相器110所造成的延迟实质上可与Q个第二反相器120及R个延迟组件130所共同造成的延迟相等。如此一来，时钟信号SIGCLKA与时钟信号SIGCLKB就可以同步变换电位，减少电荷泵单元100产生逆向电流。
图2是时钟信号SIGCLKA与时钟信号SIGCLKB的波形图。在图2中，在时段T1，时钟信号SIGCLKA是第一电压VDD，而时钟信号SIGCLKB是第二电压VSS，第二电压VSS低于第一电压VDD。在部分实施例中，电荷泵单元100的输入端IN也可接收第一电压VDD。
在时段T1先前的时段中，第一电容C1的第一端可先经由第一N型晶体管N1被充电至第一电压VDD，而第一电容C1的第二端则是第二电压VSS。在时段T1中，由于时钟信号SIGCLKA会被抬升至第一电压VDD，因此第一电容C1的第一端会被抬升到第三电压2VDD，亦即第一电压VDD的两倍。如此一来，第二N型晶体管N2会被导通，使得第二电容C2的第一端会经由第二N型晶体管N2被充电至第一电压VDD，同时第二电容C2的第二端则会随着时钟信号SIGCLKB处于第二电压VSS。
再者，第一P型晶体管P1会被导通，而第二P型晶体管P2会被截止。因此，电荷泵单元100可经由第一P型晶体管P1自输出端OUT输出第三电压2VDD。
相似地，在时段T2中，时钟信号SIGCLKA变为第二电压VSS而时钟信号SIGCLKB变为第一电压VDD。由于第二电容C2的第一端已经在时段T1中经由第二N型晶体管N2被充电至第一电压VDD，因此在时段T2中，第二电容C2的第一端会随着时钟信号SIGCLKB抬升而被抬升至第三电压2VDD。如此一来，第一N型晶体管N1将被导通，因此第一电容C1的第一端会被充电至第一电压VDD，而第一电容C1的第二端则会随着时钟信号SIGCLKA而处于第二电压VSS。
再者，第二P型晶体管P2会被导通，而第一P型晶体管P1会被截止。因此，第三电压2VDD会经由第二P型晶体管P2输出至输出端OUT。
如此一来，第一P型晶体管P1及第二P型晶体管P2可以交替地输出第三电压2VDD，亦即输入电压VDD的两倍。在现有技术中，若时钟信号SIGCLKA及时钟信号SIGCLKB未能同步变换电位，则将可能导致逆向电流产生。举例来说，若在时钟信号SIGCLKA自第二电压VSS变为第一电压VDD的之前，时钟信号SIGCLKB就先自第一电压VDD变为第二电压VSS，则时钟信号SIGCLKA及时钟信号SIGCLKB会有短暂的时间同时处于第二电压VSS。在这个短暂的时间内，第一P型晶体管P1及第二P型晶体管P2可能都会被导通，因而产生自输出端OUT流经第一P型晶体管P1及第二P型晶体管P2至第一P型晶体管P1的第一端及第二P型晶体管P2的第一端的逆向电流。
然而，由于P个第一反相器110所造成的延迟实质上会与Q个第二反相器120及R个延迟组件130所共同造成的延迟相同，因此电荷泵单元100能够减少因为时钟信号不匹配而导致的逆向电流。
图3是本发明一实施例的反相器INV的示意图。P个第一反相器110及Q个第二反相器120中的每一个反相器皆可与反相器INV具有相同的结构。反相器INV包括输入端、输出端、P型晶体管INVP及N型晶体管INVN。P型晶体管INVP具有第一端、第二端及控制端。P型晶体管INVP的第一端可接收第一偏压，例如第一电压VDD，P型晶体管INVP的第二端耦接于反相器INV的输出端，而P型晶体管的控制端耦接于反相器INV的输入端。N型晶体管INVN具有第一端、第二端及控制端。N型晶体管INVN的第一端耦接于P型晶体管的第二端及反相器INV的输出端，N型晶体管INVN的第二端可接收第二偏压，例如第二电压VSS，而N型晶体管的控制端耦接于反相器INV的输入端。
图4是本发明一实施例的延迟组件DE的示意图。R个延迟组件130中的每一个延迟组件都可与延迟组件DE具有相同的结构。延迟组件DE具有输入端、输出端、N型晶体管DEN及P型晶体管DEP。N型晶体管DEN具有第一端、第二端及控制端，N型晶体管DEN的第一端耦接于延迟组件DE的输入端，N型晶体管DEN的第二端耦接于延迟组件DE的输出端，而N型晶体管DEN的控制端接收第一偏压，例如第一电压VDD。P型晶体管DEP具有第一端、第二端及控制端，P型晶体管DEP的第一端耦接于延迟组件DE的输入端，P型晶体管DEP的第二端耦接于延迟组件DE的输出端，而P型晶体管DEP的控制端可接收第二偏压，例如第二电压VSS。亦即，第一偏压会大于第二偏压。
为提供与反相器INV相同的延迟效果，延迟组件DE可设计成使其中的N型晶体管DEN的信道宽长比(channel width-to-length ratio)实质上与反相器INV的N型晶体管INVN的信道宽长比相等。此外，延迟组件DE的P型晶体管DEP的信道宽长比实质上也可相等于反相器INV的P型晶体管INVP的信道宽长比。
在此情况下，若P个第一反相器110及Q个第二反相器120皆以反相器INV来实作，且R个延迟组件130皆以延迟组件DE来实作，则R与Q的和可等于P。如此一来，P个第一反相器110所造成的延迟便会与Q个第二反相器120及R个延迟组件130所造成的延迟相等。举例来说，P可为3，Q可为2，而R可为1。或者，在另一个实施例中，P可为5，Q可为2，而R可为3。此外，电荷泵单元100也可仅利用第一反相器110及延迟组件130，而不使用第二反相器120。举例来说，P可为1，Q可为0，而R可为1。在此情况下，第一电容C1及第二电容C2仍然可以接收到同步且互补的时钟信号，并得以避免逆向电流产生。
再者，在部分实施例中，延迟组件130造成的延迟可能会与反相器110或120所造成的延迟不同，此时P、Q及R的数值亦可根据系统的需求加以调整。
在图1中，电荷泵单元100可另包括第一初始升压晶体管IT1及第二初始升压晶体管IT2。第一初始升压晶体管IT1具有第一端、第二端及控制端，第一初始升压晶体管IT1的第一端耦接于电荷泵单元100的输入端IN，第一初始升压晶体管IT1的第二端耦接于第一N型晶体管N1的第二端，而第一初始升压晶体管IT1的控制端耦接于电荷泵单元100的输入端IN。第二初始升压晶体管IT2具有第一端、第二端及控制端，第二初始升压晶体管IT2的第一端耦接于电荷泵单元100的输入端IN，第二初始升压晶体管IT2的第二端耦接于第二N型晶体管N2的第二端，而第二初始升压晶体管IT2的控制端耦接于电荷泵单元100的输入端IN。
初始升压晶体管IT1及IT2可为N型晶体管，且可用以在升压过程的初期将第一N型晶体管N1的第二端及第二N型晶体管N2的第二端充电至(VDD-Vthn)，其中Vthn是N型晶体管的临界电压，以确保电荷泵单元100能够快速地进入稳定状态并输出高电压。
此外，电荷泵单元100还可包括第一升压充电晶体管TT1及第二升压充电晶体管TT2。第一升压充电晶体管TT1具有第一端、第二端及控制端。第一升压充电晶体管TT1的第一端耦接于第一N型晶体管N1的第二端，第一升压充电晶体管TT1的第二端耦接于电荷泵单元100的输出端OUT，而第一升压充电晶体管TT1的控制端耦接于电荷泵单元100的输出端OUT。第二升压充电晶体管TT2具有第一端、第二端及控制端。第二升压充电晶体管TT2的第一端耦接于第二N型晶体管N2的第二端，第二升压充电晶体管TT2的第二端耦接于电荷泵单元100的输出端OUT，而第二升压充电晶体管TT2的控制端耦接于电荷泵单元100的输出端OUT。
升压充电晶体管TT1及TT2可为P型晶体管，并可用来在升压过程的初期对第一P型晶体管P1的第二端及第二P型晶体管P2的第二端进行预充电，以减少电荷泵100输出电压的准备时间。举例来说，若时钟信号SIGCLKA自第二电压VSS变为第一电压VDD，第一电容C1的第一端会被抬升至第三电压2VDD，此时第一升压充电晶体管TT1就可以将第一P型晶体管的第二端充电至(2VDD-Vthp)，其中Vthp是P型晶体管的临界电压，以确保电荷泵单元100能够快速地进入稳定状态并输出高电压。
再者，为减少基体效应(body effect)，并避免第一N型晶体管N1的接面崩溃产生漏电流，电荷泵单元100还可包括第一井电位切换电路WS1。第一井电位切换电路WS1包括第三N型晶体管及第四N型晶体管N4。
第三N型晶体管N3具有第一端、第二端、控制端及基体端。第三N型晶体管N3的第一端耦接于第一N型晶体管N1的基体端，第三N型晶体管N3的第二端耦接于第一N型晶体管N1的第二端，第三N型晶体管N3的控制端耦接于第一N型晶体管N1的第一端，而第三N型晶体管N3的基体端耦接于第一N型晶体管N1的基体端。第四N型晶体管N4具有第一端、第二端、控制端及基体端，第四N型晶体管N4的第一端耦接于第一N型晶体管N1的第一端，第四N型晶体管N4的第二端耦接于第一N型晶体管N1的基体端，第四N型晶体管N4的控制端耦接于第一N型晶体管N1的第二端，而第四N型晶体管N4的基体端耦接于第一N型晶体管N1的基体端。
透过井电位切换电路WS1，第一N型晶体管N1的基体端电压就可被控制在不大于第一N型晶体管N1的第一端电压，亦不大于第一N型晶体管N1的第二端电压。因此得以避免第一N型晶体管N1产生基体效应并减少漏电流。
相似地，在图1中，电荷泵单元100还可包括第二井电位切换电路WS2、第三井电位切换电路WS3及第四井电位切换电路WS4，以避免第二N型晶体管N2、第一P型晶体管P1及第二P型晶体管P2因为基体效应而产生漏电流。
第二井电位切换电路WS2至第四井电位切换电路WS4可皆与第一井电位切换电路WS1具有相似的结构。也就是说，第二井电位切换电路WS2可包括第五N型晶体管N5及第六N型晶体管N6。第五N型晶体管N5及第六N型晶体管N6可耦接至第二N型晶体管N2，且其耦接方式会与第三N型晶体管N3及第四N型晶体管耦接至第一N型晶体管N1的方式相同。
再者，第三井电位切换电路WS3可包括第三P型晶体管P3及第四P型晶体管P4。第三P型晶体管P3及第四P型晶体管P4可耦接至第一P型晶体管P1，且其耦接方式会与第三N型晶体管N3及第四N型晶体管耦接至第一N型晶体管N1的方式相同。第四井电位切换电路WS4可包括第五P型晶体管P5及第六P型晶体管P6。第五P型晶体管P5及第六P型晶体管P6可耦接至第二P型晶体管P2，且其耦接方式会与第三N型晶体管N3及第四N型晶体管耦接至第一N型晶体管N1的方式相同。
图5是本发明一实施例的电荷泵电路10的示意图。电荷泵电路10包括电压输入端口VIN、电压输出端口VOUT、(N+1)个电荷泵单元1001至100(N+1)、时钟信号源12及N个时钟延迟组件141至14N，N是正整数。(N+1)个电荷泵单元1001至100(N+1)可串接于电压输入端口VIN及电压输出端口VOUT之间。也就是说，(N+1)个电荷泵单元中的第一电荷泵单元1001可耦接于电压输入端口VIN，而(N+1)个电荷泵单元中的最末电荷泵单元100(N+1)可耦接于电压输出端口VOUT。
在部分实施例中，每一个(N+1)个电荷泵单元1001至100(N+1)可与图1中的电荷泵单元100具有相同的结构。因此，若电压输入端口VIN接收到第一电压VDD，则电压输出端口VOUT则可输出(N+2)倍的第一电压VDD，亦即(N+2)VDD。
此外，利用图1的结构，电荷泵单元1001至100(N+1)也能够根据所接收到的单一时钟信号，而自行产生两个同步且互补的时钟信号。
也就是说，当接收到时钟信号源12所产生的主时钟信号SIGCLK1时，电荷泵单元1001至100(N+1)可对应地产生两个互补的时钟信号。然而，倘若电荷泵单元1001至100(N+1)所产生的互补时钟信号是同时变换电位，则将导致电荷泵单元1001至100(N+1)中的电容会在同时充电，使得每次时钟信号变换电位时都会产生高峰值电流。因此，在图5中，N个时钟延迟组件141至14N可串接至时钟信号源12，并藉由延迟主时钟信号SIGCLK1产生电荷泵单元1001至100(N+1)所需的时钟信号。此外，每一个时钟延迟组件141至14N可藉由将所接收到的时钟信号延迟一预定时间以产生所需的时钟信号。
举例来说，第一时钟延迟组件141的输出端可耦接于第二电荷泵单元1002的时钟输入端CLK，而第二时钟延迟组件142的输出端可耦接于第三电荷泵单元1003的时钟输入端CLK。此外，时钟信号SIGCLK2可输出至第二时钟延迟组件142以产生时钟信号SIGCLK3。亦即，时钟信号SIGCLK3可利用延迟时钟信号SIGCLK2来产生。
图6是时钟信号源12所产生的主时钟信号SIGCLK1及时钟延迟组件141至14N所产生的时钟信号SIGCLK2至SIGCLK(N+1)的波形图。在图6中，主时钟信号SIGCLK1及时钟信号SIGCLK2至SIGCLK(N+1)会依序变换电位。举例来说，主时钟信号SIGCLK1的上升沿RE1会领先时钟信号SIGCLK2的上升沿RE2，且时钟信号SIGCLK2的上升沿RE2会领先时钟信号SIGCLK3的上升沿RE3。此外，时钟信号SIGCLKi的上升沿REi会领先时钟信号SIGCLK(i+1)的上升沿RE(i+1)，其中i是大于1且小于(N+1)的整数。然而，主时钟信号SIGCLK1的下降沿FE1会落后时钟信号SIGCLK(N+1)的上升沿RE(N+1)。此外，主时钟信号SIGCLK1的下降沿FE1会领先时钟信号SIGCLK2的下降沿FE2，而时钟信号SIGCLKi的下降沿FEi会领先时钟信号SIGCLK(i+1)的下降沿FE(i+1)。也就是说，时钟信号SIGCLK2至SIGCLK(N+1)可为在时序上平移主时钟信号SIGCLK1所产生的一序列时钟信号。
在此情况下，接收的主时钟信号SIGCLK1的第一电荷泵单元1001会最先被充电，而接收时钟信号SIGCLK2的第二电荷泵单元1002则会第二个被充电，并依此类推。如此一来，就能够尽量避免电荷泵单元1001至100(N+1)同时充电，进而能够较现有技术减少高峰值电流。
在图5中，电荷泵单元1001至100(N+1)可接收相异的时钟信号。然而，在部分实施例中，部分电荷泵单元也可能接收相同的时钟信号以减少时钟延迟组件所需的面积。图7是本发明另一实施例的电荷泵电路20的示意图。
在图7中，电荷泵电路20与电荷泵电路10的结构相似。然而，电荷泵电路20包括(2N+2)个电荷泵单元1001至100(2N+2)。在此情况下，每一对电荷泵单元将会接收到相同的时钟信号。举例来说，电荷泵单元1001及1002会接收到主时钟信号SIGCLK1，而电荷泵单元100(2N+1)及100(2N+2)会接收到相同的时钟信号SIGCLK(N+1)。因此相较于电荷泵电路10，当电荷泵单元数量的增加时，电荷泵电路20的时钟延迟组件的数量会增加的较慢，进而减少电荷泵电路所需的面积。然而，当有越多的电荷泵单元共享相同的时钟信号时，也将导致电荷泵电路的高峰值电流上升。因此，电荷泵电路可根据系统的需求，选择让适当数量的电荷泵单元接收相同的时钟信号。
综上所述，本发明的实施例所提供的电荷泵单元及电荷泵电路可利用延迟组件及反相器来产生精准而互补的时钟信号，进而减少反向电流，并可简化电荷泵电路对时钟信号的控制。此外，藉由让电荷泵电路中每一级的电荷泵单元接收到依序延迟的时钟信号，也能够有效的减少高峰值电流。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (13)

1.一种电荷泵单元，其特征在于，包括：
输入端；
输出端；
第一N型晶体管，具有耦接于所述输入端的第一端，第二端，及控制端；
第二N型晶体管，具有耦接于所述输入端的第一端，耦接于所述第一N型晶体管的所述控制端的第二端，及耦接于所述第一N型晶体管的所述第二端的控制端；
第一P型晶体管，具有耦接于所述第一N型晶体管的所述第二端的第一端，耦接于所述输出端的第二端，及控制端；
第二P型晶体管，具有耦接于所述第二N型晶体管的所述第二端及所述第一P型晶体管的所述控制端的第一端，耦接于所述输出端的第二端，及耦接于所述第一P型晶体管的所述第一端的控制端；
第一电容，具有耦接于所述第一N型晶体管的所述第二端的第一端，及第二端；
第二电容，具有耦接于所述第二N型晶体管的所述第二端的第一端，及第二端；
时钟输入端，用以接收时钟信号；
P个第一反相器，串联于所述时钟输入端及所述第一电容的所述第二端之间，其中P是正整数；
Q个第二反相器；及
R个延迟组件，与所述Q个第二反相器串联于所述时钟输入端及所述第二电容的所述第二端之间，其中R是正整数，所述R个延迟组件的每一延迟组件包括：
输入端；
输出端；
N型晶体管，具有耦接于所述延迟组件的所述输入端的第一端，耦接于所述延迟组件的所述输出端的第二端，及用以接收第一偏压的控制端；及
P型晶体管，具有耦接于所述延迟组件的所述输入端的第一端，耦接于所述延迟组件的所述输出端的第二端，及用以接收第二偏压的控制端；
其中：
所述第一偏压大于所述第二偏压；
Q是小于P的正整数，且P与Q的差值是奇数；及
所述P个第一反相器所造成的延迟与所述Q个第二反相器及所述R个延迟组件所造成的延迟相同。
2.如权利要求1所述的电荷泵单元，其特征在于所述P个第一反相器及所述Q个第二反相器的每一反相器包括：
输入端；
输出端；
P型晶体管，具有用以接收所述第一偏压的第一端，耦接于所述反相器的所述输出端的第二端，及耦接于所述反相器的所述输入端的控制端；及
N型晶体管，具有耦接于所述反相器的所述输出端的第一端，用以接收所述第二偏压的第二端，及耦接于所述反相器的所述输入端的控制端；
其中：
所述反相器的所述N型晶体管的信道宽长比相等于所述延迟组件的所述N型晶体管的信道宽长比；及
所述反相器的所述P型晶体管的信道宽长比相等于所述延迟组件的所述P型晶体管的信道宽长比。
3.如权利要求1所述的电荷泵单元，其特征在于，另包括：
第一初始升压晶体管，具有耦接于所述电荷泵单元的所述输入端的第一端，耦接于所述第一N型晶体管的所述第二端的第二端，及耦接于所述电荷泵单元的所述输入端的控制端；及
第二初始升压晶体管，具有耦接于所述电荷泵单元的所述输入端的第一端，耦接于所述第二N型晶体管的所述第二端的第二端，及耦接于所述电荷泵单元的所述输入端的控制端。
4.如权利要求1所述的电荷泵单元，其特征在于，另包括：
第一升压充电晶体管，具有耦接于所述第一N型晶体管的所述第二端的第一端，耦接于所述电荷泵单元的所述输出端的第二端，及耦接于所述电荷泵单元的所述输出端的控制端；及
第二升压充电晶体管，具有耦接于所述第二N型晶体管的所述第二端的第一端，耦接于所述电荷泵单元的所述输出端的第二端，及耦接于所述电荷泵单元的所述输出端的控制端。
5.如权利要求1所述的电荷泵单元，其特征在于，另包括：
第一井电位切换电路，包括：
第三N型晶体管，具有耦接于所述第一N型晶体管的一基体端的第一端，耦接于所述第一N型晶体管的所述第二端的第二端，耦接于所述第一N型晶体管的所述第一端的控制端，及耦接于所述第一N型晶体管的所述基体端的基体端；及
第四N型晶体管，具有耦接于所述第一N型晶体管的一第一端的第一端，耦接于所述第一N型晶体管的所述基体端的第二端，耦接于所述第一N型晶体管的所述第二端的控制端，及耦接于所述第一N型晶体管的所述基体端的基体端。
6.如权利要求5所述的电荷泵单元，其特征在于，另包括：
第二井电位切换电路，包括：
第五N型晶体管，具有耦接于所述第二N型晶体管的一基体端的第一端，耦接于所述第二N型晶体管的所述第二端的第二端，耦接于所述第二N型晶体管的所述第一端的控制端，及耦接于所述第二N型晶体管的所述基体端的基体端；及
第六N型晶体管，具有耦接于所述第二N型晶体管的第一端的第一端，耦接于所述第二N型晶体管的所述基体端的第二端，耦接于所述第二N型晶体管的所述第二端的控制端，及耦接于所述第二N型晶体管的所述基体端的基体端。
7.如权利要求6所述的电荷泵单元，其特征在于，另包括：
第三井电位切换电路，包括：
第三P型晶体管，具有耦接于所述第一P型晶体管的基体端的第一端，耦接于所述第一P型晶体管的所述第二端的第二端，耦接于所述第一P型晶体管的所述第一端的控制端，及耦接于所述第一P型晶体管的所述基体端的基体端；及
第四P型晶体管，具有耦接于所述第一P型晶体管的所述第一端的第一端，耦接于所述第一P型晶体管的所述基体端的第二端，耦接于所述第一P型晶体管的所述第二端的控制端，及耦接于所述第一P型晶体管的所述基体端的基体端。
8.如权利要求7所述的电荷泵单元，其特征在于，另包括：
第四井电位切换电路，包括：
第五P型晶体管，具有耦接于所述第二P型晶体管的一基体端的第一端，耦接于所述第二P型晶体管的所述第二端的第二端，耦接于所述第二P型晶体管的所述第一端的控制端，及耦接于所述第二P型晶体管的所述基体端的基体端；及
第六P型晶体管，具有耦接于所述第二P型晶体管的所述第一端的第一端，耦接于所述第二P型晶体管的所述基体端的第二端，耦接于所述第二P型晶体管的所述第二端的控制端，及耦接于所述第二P型晶体管的所述基体端的基体端。
9.一种电荷泵电路，其特征在于，包括：
电压输入端口，用以接收输入电压；
电压输出端口，用以输出抬升电压；
多个电荷泵单元，串接于所述电压输入端口及所述电压输出端口之间，所述多个电荷泵单元中的每一电荷泵单元包括：
输入端；
输出端；
第一N型晶体管，具有耦接于所述输入端的第一端，第二端，及控制端；
第二N型晶体管，具有耦接于所述输入端的第一端，耦接于所述第一N型晶体管的所述控制端的第二端，及耦接于所述第一N型晶体管的所述第二端的控制端；
第一P型晶体管，具有耦接于所述第一N型晶体管的所述第二端的第一端，耦接于所述输出端的第二端，及控制端；
第二P型晶体管，具有耦接于所述第二N型晶体管的所述第二端及所述第一P型晶体管的所述控制端的第一端，耦接于所述输出端的第二端，及耦接于所述第一P型晶体管的所述第一端的控制端；
第一电容，具有耦接于所述第一N型晶体管的所述第二端的第一端，及第二端；
第二电容，具有耦接于所述第二N型晶体管的所述第二端的第一端，及第二端；
时钟输入端，用以接收时钟信号；
P个第一反相器，串联于所述时钟输入端及所述第一电容的所述第二端之间，其中P是正整数；
Q个第二反相器；及
R个延迟组件，与所述Q个第二反相器串联于所述时钟输入端及所述第二电容的所述第二端之间，其中R是正整数，所述R个延迟组件的每一延迟组件包括：
输入端；
输出端；
N型晶体管，具有耦接于所述延迟组件的所述输入端的第一端，耦接于所述延迟组件的所述输出端的第二端，及用以接收第一偏压的控制端；及
P型晶体管，具有耦接于所述延迟组件的所述输入端的第一端，
耦接于所述延迟组件的所述输出端的第二端，及用以接收第二偏压的控制端，其中所述第一偏压大于所述第二偏压；
时钟信号源，用以产生主要时钟信号；及
N个时钟延迟组件，耦接于所述时钟信号源，并用以延迟所述主要时钟信号以产生所述多个电荷泵单元中至少一电荷泵单元所需的至少一时钟信号；
其中：
所述多个电荷泵单元中的第一电荷泵单元接收所述主要时钟信号；
所述主要时钟信号的上升沿领先所述至少一电荷泵单元中最后一电荷泵单元所接收的最末时钟信号的上升沿，且所述主要时钟信号的下降沿落后于所述最末时钟信号的上升沿；
Q是小于P的正整数，且P与Q的差值是奇数；及
所述P个第一反相器所造成的延迟与所述Q个第二反相器及所述R个延迟组件所造成的延迟相同。
10.如权利要求9所述的电荷泵电路，其特征在于所述P个第一反相器及所述Q个第二反相器的每一反相器包括：
输入端；
输出端；
P型晶体管，具有用以接收所述第一偏压的第一端，耦接于所述反相器的所述输出端的第二端，及耦接于所述反相器的所述输入端的控制端；及
N型晶体管，具有耦接于所述反相器的所述输出端的第一端，用以接收所述第二偏压的第二端，及耦接于所述反相器的所述输入端的控制端；
其中：
所述反相器的所述N型晶体管的信道宽长比相等于所述延迟组件的所述N型晶体管的信道宽长比；及
所述反相器的所述P型晶体管的信道宽长比相等于所述延迟组件的所述P型晶体管的信道宽长比。
11.如权利要求9所述的电荷泵电路，其特征在于所述每一电荷泵单元另包括：
第一井电位切换电路包括：
第三N型晶体管，具有耦接于所述第一N型晶体管的基体端的第一端，耦接于所述第一N型晶体管的所述第二端的第二端，耦接于所述第一N型晶体管的所述第一端的控制端，及耦接于所述第一N型晶体管的所述基体端的基体端；及
第四N型晶体管，具有耦接于所述第一N型晶体管的所述第一端的第一端，耦接于所述第一N型晶体管的所述基体端的第二端，耦接于所述第一N型晶体管的所述第二端的控制端，及耦接于所述第一N型晶体管的所述基体端的基体端。
12.如权利要求9所述的电荷泵电路，其特征在于所述每一电荷泵单元另包括：
第二井电位切换电路，包括：
第三P型晶体管，具有耦接于所述第一P型晶体管的一基体端的第一端，耦接于所述第一P型晶体管的所述第二端的第二端，耦接于所述第一P型晶体管的所述第一端的控制端，及耦接于所述第一P型晶体管的所述基体端的基体端；及
第四P型晶体管，具有耦接于所述第一P型晶体管的所述第一端的第一端，耦接于所述第一P型晶体管的所述基体端的第二端，耦接于所述第一P型晶体管的所述第二端的控制端，及耦接于所述第一P型晶体管的所述基体端的基体端。
13.如权利要求9所述的电荷泵电路，其特征在于：
所述多个电荷泵单元包括(N+1)个电荷泵单元；及
第i个时钟延迟组件的输出端耦接于第(i+1)电荷泵单元的时钟输入端，且N≧i≧1。
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