TWI636652B - 電荷泵單元及電荷泵電路 - Google Patents

電荷泵單元及電荷泵電路 Download PDF

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Publication number
TWI636652B
TWI636652B TW106127886A TW106127886A TWI636652B TW I636652 B TWI636652 B TW I636652B TW 106127886 A TW106127886 A TW 106127886A TW 106127886 A TW106127886 A TW 106127886A TW I636652 B TWI636652 B TW I636652B
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Taiwan
Prior art keywords
terminal
type transistor
coupled
charge pump
pump unit
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TW106127886A
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English (en)
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TW201902097A (zh
Inventor
張武昌
楊政德
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力旺電子股份有限公司
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Publication of TW201902097A publication Critical patent/TW201902097A/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
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    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
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    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators
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    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
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    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
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    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
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    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
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    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
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    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
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    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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    • G11C2013/0042—Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
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    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
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    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/4013—Memory devices with multiple cells per bit, e.g. twin-cells
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    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
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    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
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Abstract

電荷泵電路包含電壓輸入埠、電壓輸出埠、串接於電壓輸入埠及電壓輸出埠之間的複數個電荷泵單元、時脈訊號源及N個時脈延遲元件。時脈訊號源產生主要時脈訊號，而N個時脈延遲元件延遲主要時脈訊號以產生電荷泵單元所需之時脈訊號。主要時脈訊號之正緣領先最後一電荷泵單元所接收之最末時脈訊號的正緣，且主要時脈訊號之負緣落後於最末時脈訊號的正緣。每一電荷泵單元包含兩組反向器及延遲元件以產生兩個互補的時脈訊號。

Description

電荷泵單元及電荷泵電路
本發明係有關於一種電荷泵電路，尤其是一種具有低逆向電流及低峰值電流的電荷泵電路。
為滿足電子裝置對於低耗能的需求，積體電路(integrated circuits，IC)的電力規格也被重新設計成能夠在低電壓的環境中操作，以減少電能損耗。舉例來說，過去電力規格為5V的積體電路現在常被減至3.3V或甚至低於2V。雖然低電壓的操作能夠減少電力損耗，然而在部分的情況下，電路仍然需要較高的電壓來完成操作。舉例來說，快閃記憶體就需要較高的電壓來進行寫入及清除操作。其中較高的電壓常會利用電荷泵電路來提供。
先前技術的電荷泵電路常利用互補的時脈訊號來控制。互補的時脈訊號則常是透過將主要時脈訊號經由兩個具有不同數量之反向器的訊號路徑來產生。然而，由於這兩個互補的時脈訊號是經由不同的訊號路徑產生，因此兩者的相位差並非180度。也就是說，其中一個時脈訊號會領先另一個時脈訊號。這樣非完美的互補時脈訊號將導致電荷泵電路產生逆向電流，並增加電流損耗。此外，為了提供更高的電壓，電荷泵電路須具備更多級的電路。在此情況下，倘若未能妥善控制時脈訊號，則將導致高峰值電流產生。亦即，隨著電荷泵路的級數變多，時脈訊號的控制也變得更加複雜。
本發明之一實施例提供一種電荷泵單元，電荷泵單元包含輸入端、輸出端、第一N型電晶體、第二N型電晶體、第一P型電晶體、第二P型電晶體、第一電容、第二電容、時脈輸入端、P個第一反向器及R個延遲元件。
第一N型電晶體具有第一端、第二端及控制端，第一N型電晶體的第一端耦接於輸入端。第二N型電晶體具有第一端、第二端及控制端，第二N型電晶體的第一端耦接於輸入端，第二N型電晶體的第二端耦接於第一N型電晶體之控制端，而第二N型電晶體的控制端耦接於第一N型電晶體之第二端。第一P型電晶體具有第一端、第二端及控制端，第一P型電晶體的第一端耦接於第一N型電晶體之第二端，而第一P型電晶體的第二端耦接於輸出端。第二P型電晶體具有第一端、第二端及控制端，第二P型電晶體的第一端耦接於第二N型電晶體之第二端及第一P型電晶體的控制端，第二P型電晶體的第二端耦接於輸出端，而第二P型電晶體的控制端耦接於第一P型電晶體之第一端。第一電容具有第一端及第二端，第一電容的第一端耦接於第一N型電晶體之第二端。第二電容具有第一端及第二端，第二電容的第一端耦接於第二N型電晶體之第二端。
時脈輸入端接收時脈訊號。P個第一反向器串聯於時脈輸入端及第一電容之第二端之間，其中P為正整數。R個延遲元件串聯於時脈輸入端及第二電容之第二端之間，其中R為正整數。
本發明之另一實施例提供一種電荷泵電路。電荷泵電路包含電壓輸入埠、電壓輸出埠、複數個電荷泵單元、時脈訊號源及N個時脈延遲元件。
電壓輸入埠接收輸入電壓，而電壓輸出埠輸出抬升電壓。複數個電荷泵單元串接於電壓輸入埠及電壓輸出埠之間。時脈訊號源產生主要時脈訊號。N個時脈延遲元件耦接於時脈訊號源，並可延遲主要時脈訊號以產生複數個電荷泵單元中至少一電荷泵單元所需之至少一時脈訊號。
複數個電荷泵單元中的第一電荷泵單元接收主要時脈訊號。主要時脈訊號的正緣領先至少一電荷泵單元中最後一電荷泵單元所接收之最末時脈訊號的正緣，且主要時脈訊號之負緣係落後於最末時脈訊號的正緣。
第1圖為本發明一實施例之電荷泵單元100的示意圖。電荷泵單元100包含輸入端IN、輸出端OUT、第一N型電晶體N1、第二N型電晶體N2、第一P型電晶體P1、第二P型電晶體P2、第一電容C1、第二電容C2、時脈輸入端CLK、P個第一反向器110、Q個第二反向器120及R個延遲元件130。P為正整數，Q為小於P的正整數或0，而R為正整數。
第一N型電晶體N1具有第一端、第二端、控制端及基體端。第一N型電晶體N1的第一端耦接於輸入端IN。第二N型電晶體N2具有第一端、第二端、控制端及基體端。第二N型電晶體N2的第一端耦接於輸入端IN，第二N型電晶體N2的第二端耦接於第一N型電晶體N1的控制端，而第二N型電晶體N2的控制端耦接於第一N型電晶體N1的第二端。
第一P型電晶體P1具有第一端、第二端、控制端及基體端。第一P型電晶體P1的第一端耦接於第一N型電晶體N1的第二端，而第一P型電晶體P1的第二端耦接於輸出端OUT。第二P型電晶體P2具有第一端、第二端、控制端及基體端。第二P型電晶體P2的第一端耦接於第二N型電晶體N2的第二端及第一P型電晶體P1的控制端，第二P型電晶體P2的第二端耦接於輸出端OUT，而第二P型電晶體P2的控制端耦接於第一P型電晶體P1的第一端。
第一電容C1具有第一端及第二端。第一電容C1的第一端耦接於第一N型電晶體N1的第二端。第二電容C2具有第一端及第二端。第二電容C2的第一端耦接於第二N型電晶體N2的第二端。
時脈輸入端CLK接收時脈訊號SIG CLK。P個第一反向器110可串聯於時脈輸入端CLK及第一電容C1之第二端之間。Q個第二反向器120及R個延遲元件130可串聯於時脈輸入端CLK及第二電容C2之第二端之間。
此外，P與Q的差值可為奇數，因此由第一電容C1所接收到的時脈訊號SIG CLKA與第二電容C2所接收到的時脈訊號SIG CLKB可為互補。舉例來說，P可為3，而Q可為2。為確保時脈訊號SIG CLKA與時脈訊號SIG CLKB之間的相位差保持在180度，R個延遲元件130可與Q個第二反向器120一起串聯在時脈輸入端CLK及第二電容C2之第二端之間。R個延遲元件130可設計成能夠提供適當的延遲，使得P個第一反向器110所造成的延遲實質上可與Q個第二反向器120及R個延遲元件130所共同造成的延遲相等。如此一來，時脈訊號SIG CLKA與時脈訊號SIG CLKB就可以同步變換電位，減少電荷泵單元100產生逆向電流。
第2圖為時脈訊號SIG CLKA與時脈訊號SIG CLKB的波形圖。在第2圖中，在時段T1，時脈訊號SIG CLKA為第一電壓VDD，而時脈訊號SIG CLKB為第二電壓VSS，第二電壓VSS低於第一電壓VDD。在部分實施例中，電荷泵單元100的輸入端IN也可接收第一電壓VDD。
在時段T1先前的時段中，第一電容C1的第一端可先經由第一N型電晶體N1被充電至第一電壓VDD，而第一電容C1的第二端則為第二電壓VSS。在時段T1中，由於時脈訊號SIG CLKA會被抬升至第一電壓VDD，因此第一電容C1的第一端會被抬升到第三電壓2VDD，亦即第一電壓VDD的兩倍。如此一來，第二N型電晶體N2會被導通，使得第二電容C2的第一端會經由第二N型電晶體N2被充電至第一電壓VDD，同時第二電容C2的第二端則會隨著時脈訊號SIG CLKB處於第二電壓VSS。
再者，第一P型電晶體P1會被導通，而第二P型電晶體P2會被截止。因此，電荷泵單元100可經由第一P型電晶體P1自輸出端OUT輸出第三電壓2VDD。
相似地，在時段T2中，時脈訊號SIG CLKA變為第二電壓VSS而時脈訊號SIG CLKB變為第一電壓VDD。由於第二電容C2的第一端已經在時段T1中經由第二N型電晶體N2被充電至第一電壓VDD，因此在時段T2中，第二電容C2的第一端會隨著時脈訊號SIG CLKB抬升而被抬升至第三電壓2VDD。如此一來，第一N型電晶體N1將被導通，因此第一電容C1的第一端會被充電至第一電壓VDD，而第一電容C1的第二端則會隨著時脈訊號SIG CLKA而處於第二電壓VSS。
再者，第二P型電晶體P2會被導通，而第一P型電晶體P1會被截止。因此，第三電壓2VDD會經由第二P型電晶體P2輸出至輸出端OUT。
如此一來，第一P型電晶體P1及第二P型電晶體P2可以交替地輸出第三電壓2VDD，亦即輸入電壓VDD的兩倍。在先前技術中，若時脈訊號SIG CLKA及時脈訊號SIG CLKB未能同步變換電位，則將可能導致逆向電流產生。舉例來說，若在時脈訊號SIG CLKA自第二電壓VSS變為第一電壓VDD之前，時脈訊號SIG CLKB就先自第一電壓VDD變為第二電壓VSS，則時脈訊號SIG CLKA及時脈訊號SIG CLKB會有短暫的時間同時處於第二電壓VSS。在這個短暫的時間內，第一P型電晶體P1及第二P型電晶體P2可能都會被導通，因而產生自輸出端OUT流經第一P型電晶體P1及第二P型電晶體P2至第一P型電晶體P1的第一端及第二P型電晶體P2的第一端的逆向電流。
然而，由於P個第一反向器110所造成的延遲實質上會與Q個第二反向器120及R個延遲元件130所共同造成的延遲相同，因此電荷泵單元100能夠減少因為時脈訊號不匹配而導致的逆向電流。
第3圖為本發明一實施例之反向器INV的示意圖。P個第一反向器110及Q個第二反向器120中的每一個反向器皆可與反向器INV具有相同的結構。反向器INV包含輸入端、輸出端、P型電晶體INVP及N型電晶體INVN。P型電晶體INVP具有第一端、第二端及控制端。P型電晶體INVP的第一端可接收第一偏壓，例如第一電壓VDD，P型電晶體INVP的第二端耦接於反向器INV的輸出端，而P型電晶體的控制端耦接於反向器INV的輸入端。N型電晶體INVN具有第一端、第二端及控制端。N型電晶體INVN的第一端耦接於P型電晶體的第二端及反向器INV的輸出端，N型電晶體INVN的第二端可接收第二偏壓，例如第二電壓VSS，而N型電晶體的控制端耦接於反向器INV的輸入端。
第4圖為本發明一實施例之延遲元件DE的示意圖。R個延遲元件130中的每一個延遲元件都可與延遲元件DE具有相同的結構。延遲元件DE具有輸入端、輸出端、N型電晶體DEN及P型電晶體DEP。N型電晶體DEN具有第一端、第二端及控制端，N型電晶體DEN的第一端耦接於延遲元件DE之輸入端，N型電晶體DEN的第二端耦接於延遲元件DE之輸出端，而N型電晶體DEN的控制端接收第一偏壓，例如為第一電壓VDD。P型電晶體DEP具有第一端、第二端及控制端，P型電晶體DEP的第一端耦接於延遲元件DE之輸入端，P型電晶體DEP的第二端耦接於延遲元件DE之輸出端，而P型電晶體DEP的控制端可接收第二偏壓，例如為第二電壓VSS。亦即，第一偏壓會大於第二偏壓。
為提供與反向器INV相同的延遲效果，延遲元件DE可設計成使其中的N型電晶體DEN的通道寬長比(channel width-to-length ratio)實質上與反向器INV之N型電晶體INVN之通道寬長比相等。此外，延遲元件DE之P型電晶體DEP之通道寬長比實質上也可相等於反向器INV之P型電晶體INVP之通道寬長比。
在此情況下，若P個第一反向器110及Q個第二反向器120皆以反向器INV來實作，且R個延遲元件130皆以延遲元件DE來實作，則R與Q的和可等於P。如此一來，P個第一反向器110所造成的延遲便會與Q個第二反向器120及R個延遲元件130所造成的延遲相等。舉例來說，P可為3，Q可為2，而R可為1。或者，在另一個實施例中，P可為5，Q可為2，而R可為3。此外，電荷泵單元100也可僅利用第一反向器110及延遲元件130，而不使用第二反向器120。舉例來說，P可為1，Q可為0，而R可為1。在此情況下，第一電容C1及第二電容C2仍然可以接收到同步且互補的時脈訊號，並得以避免逆向電流產生。
再者，在部分實施例中，延遲元件130造成的延遲可能會與反向器110或120所造成的延遲不同，此時P、Q及R的數值亦可根據系統的需求加以調整。
在第1圖中，電荷泵單元100可另包含第一初始升壓電晶體IT1及第二初始升壓電晶體IT2。第一初始升壓電晶體IT1具有第一端、第二端及控制端，第一初始升壓電晶體IT1的第一端耦接於電荷泵單元100之輸入端IN，第一初始升壓電晶體IT1的第二端耦接於第一N型電晶體N1之第二端，而第一初始升壓電晶體IT1的控制端耦接於電荷泵單元100之輸入端IN。第二初始升壓電晶體IT2具有第一端、第二端及控制端，第二初始升壓電晶體IT2的第一端耦接於電荷泵單元100之輸入端IN，第二初始升壓電晶體IT2的第二端耦接於第二N型電晶體N2之第二端，而第二初始升壓電晶體IT2的控制端耦接於電荷泵單元100之輸入端IN。
初始升壓電晶體IT1及IT2可為N型電晶體，且可用以在升壓過程的初期將第一N型電晶體N1的第二端及第二N型電晶體N2的第二端充電至(VDD-Vthn)，其中Vthn為N型電晶體的臨界電壓，以確保電荷泵單元100能夠快速地進入穩定狀態並輸出高電壓。
此外，電荷泵單元100還可包含第一升壓充電電晶體TT1及第二升壓充電電晶體TT2。第一升壓充電電晶體TT1具有第一端、第二端及控制端。第一升壓充電電晶體TT1的第一端耦接於第一N型電晶體N1之第二端，第一升壓充電電晶體TT1的第二端耦接於電荷泵單元100之輸出端OUT，而第一升壓充電電晶體TT1的控制端耦接於電荷泵單元100之輸出端OUT。第二升壓充電電晶體TT2具有第一端、第二端及控制端。第二升壓充電電晶體TT2的第一端耦接於第二N型電晶體N2之第二端，第二升壓充電電晶體TT2的第二端耦接於電荷泵單元100之輸出端OUT，而第二升壓充電電晶體TT2的控制端耦接於電荷泵單元100之輸出端OUT。
升壓充電電晶體TT1及TT2可為P型電晶體，並可用來在升壓過程的初期對第一P型電晶體P1之第二端及第二P型電晶體P2之第二端進行預充電，以減少電荷泵100輸出電壓的準備時間。舉例來說，若時脈訊號SIG CLKA自第二電壓VSS變為第一電壓VDD，第一電容C1的第一端會被抬升至第三電壓2VDD，此時第一升壓充電電晶體TT1就可以將第一P型電晶體的第二端充電至(2VDD-Vthp)，其中Vthp為P型電晶體的臨界電壓，以確保電荷泵單元100能夠快速地進入穩定狀態並輸出高電壓。
再者，為減少基體效應(body effect)，並避免第一N型電晶體N1的接面崩潰產生漏電流，電荷泵單元100還可包含第一井電位切換電路WS1。第一井電位切換電路WS1包含第三N型電晶體及第四N型電晶體N4。
第三N型電晶體N3具有第一端、第二端、控制端及基體端。第三N型電晶體N3的第一端耦接於第一N型電晶體N1之基體端，第三N型電晶體N3的第二端耦接於第一N型電晶體N1之第二端，第三N型電晶體N3的控制端耦接於第一N型電晶體N1之第一端，而第三N型電晶體N3的基體端耦接於第一N型電晶體N1之基體端。第四N型電晶體N4具有第一端、第二端、控制端及基體端，第四N型電晶體N4的第一端耦接於第一N型電晶體N1之第一端，第四N型電晶體N4的第二端耦接於第一N型電晶體N1之基體端，第四N型電晶體N4的控制端耦接於第一N型電晶體N1之第二端，而第四N型電晶體N4的基體端耦接於第一N型電晶體N1之基體端。
透過井電位切換電路WS1，第一N型電晶體N1的基體端電壓就可被控制在不大於第一N型電晶體N1之第一端電壓，亦不大於第一N型電晶體N1之第二端電壓。因此得以避免第一N型電晶體N1產生基體效應並減少漏電流。
相似地，在第1圖中，電荷泵單元100還可包含第二井電位切換電路WS2、第三井電位切換電路WS3及第四井電位切換電路WS4，以避免第二N型電晶體N2、第一P型電晶體P1及第二P型電晶體P2因為基體效應而產生漏電流。
第二井電位切換電路WS2至第四井電位切換電路WS4可皆與第一井電位切換電路WS1具有相似的結構。也就是說，第二井電位切換電路WS2可包含第五N型電晶體N5及第六N型電晶體N6。第五N型電晶體N5及第六N型電晶體N6可耦接至第二N型電晶體N2，且其耦接方式會與第三N型電晶體N3及第四N型電晶體耦接至第一N型電晶體N1的方式相同。
再者，第三井電位切換電路WS3可包含第三P型電晶體P3及第四P型電晶體P4。第三P型電晶體P3及第四P型電晶體P4可耦接至第一P型電晶體P1，且其耦接方式會與第三N型電晶體N3及第四N型電晶體耦接至第一N型電晶體N1的方式相同。第四井電位切換電路WS4可包含第五P型電晶體P5及第六P型電晶體P6。第五P型電晶體P5及第六P型電晶體P6可耦接至第二P型電晶體P2，且其耦接方式會與第三N型電晶體N3及第四N型電晶體耦接至第一N型電晶體N1的方式相同。
第5圖為本發明一實施例之電荷泵電路10的示意圖。電荷泵電路10包含電壓輸入埠VIN、電壓輸出埠VOUT、(N+1)個電荷泵單元1001至100(N+1)、時脈訊號源12及N個時脈延遲元件141至14N，N為正整數。(N+1)個電荷泵單元1001至100(N+1)可串接於電壓輸入埠VIN及電壓輸出埠VOUT之間。也就是說，(N+1)個電荷泵單元中的第一電荷泵單元1001可耦接於電壓輸入埠VIN，而(N+1)個電荷泵單元中的最末電荷泵單元100(N+1)可耦接於電壓輸出埠VOUT。
在部分實施例中，每一個(N+1)個電荷泵單元1001至100(N+1)可與第1圖中的電荷泵單元100具有相同的結構。因此，若電壓輸入埠VIN接收到第一電壓VDD，則電壓輸出埠VOUT則可輸出(N+2)倍的第一電壓VDD，亦即(N+2)VDD。
此外，利用第1圖的結構，電荷泵單元1001至100(N+1)也能夠根據所接收到的單一時脈訊號，而自行產生兩個同步且互補的時脈訊號。
也就是說，當接收到時脈訊號源12所產生的主時脈訊號SIG CLK1時，電荷泵單元1001至100(N+1)可對應地產生兩個互補的時脈訊號。然而，倘若電荷泵單元1001至100(N+1)所產生的互補時脈訊號是同時變換電位，則將導致電荷泵單元1001至100(N+1)中的電容會在同時充電，使得每次時脈訊號變換電位時都會產生高峰值電流。因此，在第5圖中，N個時脈延遲元件141至14N可串接至時脈訊號源12，並藉由延遲主時脈訊號SIG CLK1產生電荷泵單元1001至100(N+1)所需的時脈訊號。此外，每一個時脈延遲元件141至14N可藉由將所接收到的時脈訊號延遲一預定時間以產生所需的時脈訊號。
舉例來說，第一時脈延遲元件141的輸出端可耦接於第二電荷泵單元1002的時脈輸入端CLK，而第二時脈延遲元件142的輸出端可耦接於第三電荷泵單元1003的時脈輸入端CLK。此外，時脈訊號SIG CLK2可輸出至第二時脈延遲元件142以產生時脈訊號SIG CLK3。亦即，時脈訊號SIG CLK3可利用延遲時脈訊號SIG CLK2來產生。
第6圖為時脈訊號源12所產生之主時脈訊號SIG CLK1及時脈延遲元件141至14N所產生之時脈訊號SIG CLK2至SIG CLK (N+1)的波形圖。在第6圖中，主時脈訊號SIG CLK1及時脈訊號SIG CLK2至SIG CLK (N+1)會依序變換電位。舉例來說，主時脈訊號SIG CLK1的正緣RE1會領先時脈訊號SIG CLK2的正緣RE2，且時脈訊號SIG CLK2的正緣RE2會領先時脈訊號SIG CLK3的正緣RE3。此外，時脈訊號SIG CLKi的正緣REi會領先時脈訊號SIG CLK(i+1)的正緣RE(i+1)，其中i為大於1且小於(N+1)的整數。然而，主時脈訊號SIG CLK1的負緣FE1會落後時脈訊號SIG CLK(N+1)的正緣RE(N+1)。此外，主時脈訊號SIG CLK1的負緣FE1會領先時脈訊號SIG CLK2的負緣FE2，而時脈訊號SIG CLKi的負緣FEi會領先時脈訊號SIG CLK(i+1)的負緣FE(i+1)。也就是說，時脈訊號SIG CLK2至SIG CLK(N+1)可為在時序上平移主時脈訊號SIG CLK1所產生的一序列時脈訊號。
在此情況下，接收的主時脈訊號SIG CLK1的第一電荷泵單元1001會最先被充電，而接收時脈訊號SIG CLK2的第二電荷泵單元1002則會第二個被充電，並依此類推。如此一來，就能夠盡量避免電荷泵單元1001至100(N+1)同時充電，進而能夠較先前技術減少高峰值電流。
在第5圖中，電荷泵單元1001至100(N+1)可接收相異的時脈訊號。然而，在部分實施例中，部分電荷泵單元也可能接收相同的時脈訊號以減少時脈延遲元件所需的面積。第7圖為本發明另一實施例之電荷泵電路20的示意圖。
在第7圖中，電荷泵電路20與電荷泵電路10的結構相似。然而，電荷泵電路20包含(2N+2)個電荷泵單元1001至100(2N+2)。在此情況下，每一對電荷泵單元將會接收到相同的時脈訊號。舉例來說，電荷泵單元1001及1002會接收到主時脈訊號SIG CLK1，而電荷泵單元100(2N+1)及100(2N+2)會接收到相同的時脈訊號SIG CLK(N+1)。因此相較於電荷泵電路10，當電荷泵單元數量的增加時，電荷泵電路20的時脈延遲元件的數量會增加的較慢，進而減少電荷泵電路所需的面積。然而，當有越多的電荷泵單元共用相同的時脈訊號時，也將導致電荷泵電路的高峰值電流上升。因此，電荷泵電路可根據系統的需求，選擇讓適當數量的電荷泵單元接收相同的時脈訊號。
綜上所述，本發明之實施例所提供的電荷泵單元及電荷泵電路可利用延遲元件及反向器來產生精準而互補的時脈訊號，進而減少反向電流，並可簡化電荷泵電路對時脈訊號的控制。此外，藉由讓電荷泵電路中每一級的電荷泵單元接收到依序延遲的時脈訊號，也能夠有效的減少高峰值電流。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
100、1001至100(2N+2)‧‧‧電荷泵單元
N1‧‧‧第一N型電晶體
N2‧‧‧第二N型電晶體
N3‧‧‧第三N型電晶體
N4‧‧‧第四N型電晶體
N5‧‧‧第五N型電晶體
N6‧‧‧第六N型電晶體
P1‧‧‧第一P型電晶體
P2‧‧‧第二P型電晶體
P3‧‧‧第三P型電晶體
P4‧‧‧第四P型電晶體
P5‧‧‧第五P型電晶體
P6‧‧‧第六P型電晶體
C1‧‧‧第一電容
C2‧‧‧第二電容
110‧‧‧第一反向器
120‧‧‧第二反向器
130‧‧‧延遲元件
WS1‧‧‧第一井電位切換電路
WS2‧‧‧第二井電位切換電路
WS3‧‧‧第三井電位切換電路
WS4‧‧‧第四井電位切換電路
IT1‧‧‧第一初始升壓電晶體
IT2‧‧‧第二初始升壓電晶體
TT1‧‧‧第一升壓充電電晶體
TT2‧‧‧第二升壓充電電晶體
CLK‧‧‧時脈輸入端
IN‧‧‧輸入端
OUT‧‧‧輸出端
VDD‧‧‧第一電壓
2VDD‧‧‧第三電壓
SIGCLK、SIGCLA、SIGCLKB、SIGCLK1至SIGCLK(N+1)‧‧‧時脈訊號
VSS‧‧‧第二電壓
T1、T2‧‧‧時段
INV‧‧‧反向器
INVN、DEN‧‧‧N型電晶體
INVP、DEP‧‧‧P型電晶體
DE‧‧‧延遲元件
10、20‧‧‧電荷泵電路
VIN‧‧‧電壓輸入埠
VOUT‧‧‧電壓輸出埠
12‧‧‧時脈訊號源
141至14N‧‧‧時脈延遲元件
RE1、RE2、REi、RE(i+1)、RE(N+1)‧‧‧正緣
FE1、FE2、FEi、FE(i+1)‧‧‧負緣
第1圖為本發明一實施例之電荷泵單元的示意圖。 第2圖為第1圖之電荷泵單元的時脈訊號波形圖。 第3圖為本發明一實施例之反向器的示意圖。 第4圖為本發明一實施例之延遲元件的示意圖。 第5圖為本發明一實施例之電荷泵電路的示意圖。 第6圖為第5圖之電荷泵電路的時脈訊號波形圖。 第7圖為本發明另一實施例之電荷泵電路的示意圖。

Claims (22)

  1. 一種電荷泵單元，包含： 一輸入端； 一輸出端； 一第一N型電晶體，具有一第一端耦接於該輸入端，一第二端，及一控制端； 一第二N型電晶體，具有一第一端耦接於該輸入端，一第二端耦接於該第一N型電晶體之該控制端，及一控制端耦接於該第一N型電晶體之該第二端； 一第一P型電晶體，具有一第一端耦接於該第一N型電晶體之該第二端，一第二端耦接於該輸出端，及一控制端； 一第二P型電晶體，具有一第一端耦接於該第二N型電晶體之該第二端及該第一P型電晶體的該控制端，一第二端耦接於該輸出端，及一控制端耦接於該第一P型電晶體之該第一端； 一第一電容，具有一第一端耦接於該第一N型電晶體之該第二端，及一第二端； 一第二電容，具有一第一端耦接於該第二N型電晶體之該第二端，及一第二端； 一時脈輸入端，用以接收一時脈訊號； P個第一反向器，串聯於該時脈輸入端及該第一電容之該第二端之間，其中P為正整數；及 R個延遲元件，串聯於該時脈輸入端及該第二電容之該第二端之間，其中R為正整數。
  2. 如請求項1所述之電荷泵單元，其中該P個第一反向器所造成的延遲實質上與該R個延遲元件所造成的延遲相同。
  3. 如請求項1所述之電荷泵單元，另包含Q個第二反向器，與該R個延遲元件相串聯，其中Q為小於P的正整數，且P與Q的差值為奇數。
  4. 如請求項3所述之電荷泵單元，其中該P個第一反向器所造成的延遲實質上與該Q個第二反向器及該R個延遲元件所造成的延遲相同。
  5. 如請求項3所述之電荷泵單元，其中該R個延遲元件之每一延遲元件包含： 一輸入端； 一輸出端； 一N型電晶體，具有一第一端耦接於該延遲元件之該輸入端，一第二端耦接於該延遲元件之該輸出端，及一控制端用以接收一第一偏壓；及 一P型電晶體，具有一第一端耦接於該延遲元件之該輸入端，一第二端耦接於該延遲元件之該輸出端，及一控制端用以接收一第二偏壓； 其中該第一偏壓大於該第二偏壓。
  6. 如請求項5所述之電荷泵單元，其中該P個第一反向器及該Q個第二反向器之每一反向器包含： 一輸入端； 一輸出端； 一P型電晶體，具有一第一端用以接收該第一偏壓，一第二端耦接於該反向器之該輸出端，及一控制端耦接於該反向器之該輸入端；及 一N型電晶體，具有一第一端耦接於該反向器之該輸出端，一第二端用以接收該第二偏壓，及一控制端耦接於該反向器之該輸入端； 其中： 該反向器之該N型電晶體之一通道寬長比實質上相等於該延遲元件之該N型電晶體之一通道寬長比；及 該反向器之該P型電晶體之一通道寬長比實質上相等於該延遲元件之該P型電晶體之一通道寬長比。
  7. 如請求項1所述之電荷泵單元，另包含： 一第一初始升壓電晶體，具有一第一端耦接於該電荷泵單元之該輸入端，一第二端耦接於該第一N型電晶體之該第二端，及一控制端耦接於該電荷泵單元之該輸入端；及 一第二初始升壓電晶體，具有一第一端耦接於該電荷泵單元之該輸入端，一第二端耦接於該第二N型電晶體之該第二端，及一控制端耦接於該電荷泵單元之該輸入端。
  8. 如請求項1所述之電荷泵單元，另包含： 一第一升壓充電電晶體，具有一第一端耦接於該第一N型電晶體之該第二端，一第二端耦接於該電荷泵單元之該輸出端，及一控制端耦接於該電荷泵單元之該輸出端；及 一第二升壓充電電晶體，具有一第一端耦接於該第二N型電晶體之該第二端，一第二端耦接於該電荷泵單元之該輸出端，及一控制端耦接於該電荷泵單元之該輸出端。
  9. 如請求項1所述之電荷泵單元，另包含： 一第一井電位切換電路，包含： 一第三N型電晶體，具有一第一端耦接於該第一N型電晶體之一基體端，一第二端耦接於該第一N型電晶體之該第二端，一控制端耦接於該第一N型電晶體之該第一端，及一基體端耦接於該第一N型電晶體之該基體端；及 一第四N型電晶體，具有一第一端耦接於該第一N型電晶體之一第一端，一第二端耦接於該第一N型電晶體之該基體端，一控制端耦接於該第一N型電晶體之該第二端，及一基體端耦接於該第一N型電晶體之該基體端。
  10. 如請求項9所述之電荷泵單元，另包含： 一第二井電位切換電路，包含： 一第五N型電晶體，具有一第一端耦接於該第二N型電晶體之一基體端，一第二端耦接於該第二N型電晶體之該第二端，一控制端耦接於該第二N型電晶體之該第一端，及一基體端耦接於該第二N型電晶體之該基體端；及 一第六N型電晶體，具有一第一端耦接於該第二N型電晶體之一第一端，一第二端耦接於該第二N型電晶體之該基體端，一控制端耦接於該第二N型電晶體之該第二端，及一基體端耦接於該第二N型電晶體之該基體端。
  11. 如請求項10所述之電荷泵單元，另包含： 一第三井電位切換電路，包含： 一第三P型電晶體，具有一第一端耦接於該第一P型電晶體之一基體端，一第二端耦接於該第一P型電晶體之該第二端，一控制端耦接於該第一P型電晶體之該第一端，及一基體端耦接於該第一P型電晶體之該基體端；及 一第四P型電晶體，具有一第一端耦接於該第一P型電晶體之一第一端，一第二端耦接於該第一P型電晶體之該基體端，一控制端耦接於該第一P型電晶體之該第二端，及一基體端耦接於該第一P型電晶體之該基體端。
  12. 如請求項11所述之電荷泵單元，另包含： 一第四井電位切換電路，包含： 一第五P型電晶體，具有一第一端耦接於該第二P型電晶體之一基體端，一第二端耦接於該第二P型電晶體之該第二端，一控制端耦接於該第二P型電晶體之該第一端，及一基體端耦接於該第二P型電晶體之該基體端；及 一第六P型電晶體，具有一第一端耦接於該第二P型電晶體之一第一端，一第二端耦接於該第二P型電晶體之該基體端，一控制端耦接於該第二P型電晶體之該第二端，及一基體端耦接於該第二P型電晶體之該基體端。
  13. 一種電荷泵電路，包含： 一電壓輸入埠，用以接收一輸入電壓； 一電壓輸出埠，用以輸出一抬升電壓； 複數個電荷泵單元，串接於該電壓輸入埠及該電壓輸出埠之間； 一時脈訊號源，用以產生一主要時脈訊號；及 N個時脈延遲元件，耦接於該時脈訊號源，並用以延遲該主要時脈訊號以產生該些電荷泵單元中至少一電荷泵單元所需之至少一時脈訊號； 其中： 該些電荷泵單元中之一第一電荷泵單元接收該主要時脈訊號；及 該主要時脈訊號之一正緣係領先該至少一電荷泵單元中最後一電荷泵單元所接收之一最末時脈訊號的正緣，且該主要時脈訊號之一負緣係落後於該最末時脈訊號的正緣。
  14. 如請求項13所述之電荷泵電路，其中該些電荷泵單元中的每一電荷泵單元包含： 一輸入端； 一輸出端； 一第一N型電晶體，具有一第一端耦接於該輸入端，一第二端，及一控制端； 一第二N型電晶體，具有一第一端耦接於該輸入端，一第二端耦接於該第一N型電晶體之該控制端，及一控制端耦接於該第一N型電晶體之該第二端； 一第一P型電晶體，具有一第一端耦接於該第一N型電晶體之該第二端，一第二端耦接於該輸出端，及一控制端； 一第二P型電晶體，具有一第一端耦接於該第二N型電晶體之該第二端及該第一P型電晶體的該控制端，一第二端耦接於該輸出端，及一控制端耦接於該第一P型電晶體之該第一端； 一第一電容，具有一第一端耦接於該第一N型電晶體之該第二端，及一第二端； 一第二電容，具有一第一端耦接於該第二N型電晶體之該第二端，及一第二端； 一時脈輸入端，用以接收一時脈訊號； P個第一反向器，串聯於該時脈輸入端及該第一電容之該第二端之間，其中P為正整數；及 R個延遲元件，串聯於該時脈輸入端及該第二電容之該第二端之間，其中R為正整數。
  15. 如請求項14所述之電荷泵電路，其中該P個第一反向器所造成的延遲實質上與該R個延遲元件所造成的延遲相同。
  16. 如請求項14所述之電荷泵電路，其中該每一電荷泵單元另包含Q個第二反向器，與該R個延遲元件相串聯，其中Q為小於P的正整數，且P與Q的差值為奇數。
  17. 如請求項16所述之電荷泵電路，其中該P個第一反向器所造成的延遲實質上與該Q個第二反向器及該R個延遲元件所造成的延遲相同。
  18. 如請求項17所述之電荷泵電路，其中該P個第一反向器及該Q個第二反向器之每一反向器包含： 一輸入端； 一輸出端； 一P型電晶體，具有一第一端用以接收該第一偏壓，一第二端耦接於該反向器之該輸出端，及一控制端耦接於該反向器之該輸入端；及 一N型電晶體，具有一第一端耦接於該反向器之該輸出端，一第二端用以接收該第二偏壓，及一控制端耦接於該反向器之該輸入端； 其中： 該反向器之該N型電晶體之一通道寬長比實質上相等於該延遲元件之該N型電晶體之一通道寬長比；及 該反向器之該P型電晶體之一通道寬長比實質上相等於該延遲元件之該P型電晶體之一通道寬長比。
  19. 如請求項14所述之電荷泵電路，其中該R個延遲元件之每一延遲元件包含： 一輸入端； 一輸出端； 一N型電晶體，具有一第一端耦接於該延遲元件之該輸入端，一第二端耦接於該延遲元件之該輸出端，及一控制端用以接收一第一偏壓；及 一P型電晶體，具有一第一端耦接於該延遲元件之該輸入端，一第二端耦接於該延遲元件之該輸出端，及一控制端用以接收一第二偏壓； 其中該第一偏壓大於該第二偏壓。
  20. 如請求項14所述之電荷泵電路，其中該每一電荷泵單元另包含： 一第一井電位切換電路包含： 一第三N型電晶體，具有一第一端耦接於該第一N型電晶體之一基體端，一第二端耦接於該第一N型電晶體之該第二端，一控制端耦接於該第一N型電晶體之該第一端，及一基體端耦接於該第一N型電晶體之該基體端；及 一第四N型電晶體，具有一第一端耦接於該第一N型電晶體之一第一端，一第二端耦接於該第一N型電晶體之該基體端，一控制端耦接於該第一N型電晶體之該第二端，及一基體端耦接於該第一N型電晶體之該基體端。
  21. 如請求項14所述之電荷泵電路，其中該每一電荷泵單元另包含： 一第二井電位切換電路，包含： 一第三P型電晶體，具有一第一端耦接於該第一P型電晶體之一基體端，一第二端耦接於該第一P型電晶體之該第二端，一控制端耦接於該第一P型電晶體之該第一端，及一基體端耦接於該第一P型電晶體之該基體端；及 一第四P型電晶體，具有一第一端耦接於該第一P型電晶體之一第一端，一第二端耦接於該第一P型電晶體之該基體端，一控制端耦接於該第一P型電晶體之該第二端，及一基體端耦接於該第一P型電晶體之該基體端。
  22. 如請求項13所述之電荷泵電路，其中： 該些電荷泵單元包含(N+1)個電荷泵單元；及 一第i個時脈延遲元件之一輸出端係耦接於一第(i+1)電荷泵單元之一時脈輸入端，且N≧i≧1。
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