CN108962332B - 内存系统及感测装置 - Google Patents

内存系统及感测装置 Download PDF

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CN108962332B
CN108962332B CN201710972339.1A CN201710972339A CN108962332B CN 108962332 B CN108962332 B CN 108962332B CN 201710972339 A CN201710972339 A CN 201710972339A CN 108962332 B CN108962332 B CN 108962332B
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memory
selector
output
input
coupled
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CN108962332A (zh
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吴柏庆
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eMemory Technology Inc
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eMemory Technology Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
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    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
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    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
    • G—PHYSICS
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    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
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    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
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Abstract

本发明公开了一种内存系统包括第一内存组、第一路径选择器、第二内存组、第二路径选择器及感测装置。第一内存组包括多个第一内存单元。第二内存组包括多个第二内存单元。第一路径选择器包括经由多条第一位线耦接至多个第一内存单元的多个输入端，以及两个输出端。第二路径选择器包括经由多条第二位线耦接至多个第二内存单元的多个输入端，以及两个输出端。感测装置耦接于第一路径选择器及第二路径选择器的输出端，并根据操作的需要感测参考电流源及两个路径选择器的输出端中对应两股电流的差值。

Description

内存系统及感测装置
技术领域
本发明是有关于一种内存系统，特别是能够具有低耗能读取操作的内存系统。
背景技术
目前行动电子装置常被用来执行各种应用，例如看影片、照相、听音乐…等等。为了能够支持更多的应用，行动电子装置常需要大量的内存空间，因此如何使行动电子装置搭载大量的内存空间成为设计行动电子装置的关键的一。
然而，随着内存空间的成长，操作内存所需的电能也随着增加。举例来说，当更多的内存单元被嵌入在单一内存组(memory bank)时，内存组的每一条位线都会耦接至更多的内存单元。在此情况下，若欲经由一条位线从其中的一内存单元读出储存数据，则此内存单元所产生的读取电流就必须先对耦接至这条位线的其他内存单元的寄生电容进行充电，最终才能被判别读取。如此一来，读取电流会被减弱而不易判别，并且因为位在线的充电路径较长，导致读取速度降低。为解决此一问题，现有技术会使内存单元所产生的读取电流增强，然而，如此又将导致内存单元的耗能增加，而与行动电子装置的低耗能需求相抵触。
发明内容
本发明的一实施例提供一种内存系统，内存系统包括第一内存组、第一路径选择器、第二内存组、第二路径选择器及感测装置。
第一内存组包括N条第一位线，N为大于1的正整数。第一路径选择器包括N个输入端、第一输出端及第二输出端。第一路径选择器的N个输入端耦接于N条第一位线。
第二内存组包括N条第二位线。第二路径选择器包括N个输入端、第一输出端及第二输出端。第二路径选择器的N个输入端耦接于所述N条第二位线。
感测装置包括第一内存组选择器、第二内存组选择器及差动感测放大器。第一内存组选择器具有耦接于第一路径选择器的第一输出端的第一输入端，耦接于第二路径选择器的第一输出端的第二输出端，及输出端。第二内存组选择器具有耦接于第一路径选择器的第二输出端的第一输入端，耦接于第二路径选择器的第二输出端的第二输出端，及输出端。差动感测放大器具有耦接于第一内存组选择器的输出端的第一输入端，耦接于第二内存组选择器的输出端的第二输入端。
在选定的第一位线的检测操作或边界读取操作期间，第一内存组选择器及第一路径选择器建立差动感测放大器的第一输入端及选定的第一位线之间的电性连接，且第二内存组选择器及第二路径选择器建立差动感测放大器的第二输入端及N条第二位线中的第二位线之间的电性连接。
附图说明
图1为本发明一实施例的内存系统的示意图。
图2为本发明一实施例的感测装置的示意图。
图3为图1的第一内存单元被选定进行读取操作时，内存系统的电流路径图。图4为图1的第一内存单元被选定进行检测操作或边界读取操作时，内存系统的电流路径图。
其中，附图标记说明如下：
10 内存系统
100 感测装置
MBA 第一内存组
MBB 第二内存组
MCA(1,1)至MCA(M,N) 第一内存单元
MCB(1,1)至MCB(M,N) 第二内存单元
YP1 第一路径选择器
YP2 第二路径选择器
OA1、OB1、OA2、OB2 输出端
BLA1至BLAN 第一位线
BLB1至BLBN 第二位线
MSA1 第一组第一内存单元
MSA2 第二组第一内存单元
MSB1 第一组第二内存单元
MSB2 第二组第二内存单元
WLA1至WLAN、WLB1至WLBN 字符线
112A 第一内存组选择器
112B 第二内存组选择器
112A1、112B1、112A2、112B2、 输入端
SA1、SA2
114 差动感测放大器
114A 预充电电路
116 参考电流源
118A 第一感测选择器
118B 第二感测选择器
Iref 参考电流
Ir1、Ir(n+1) 读取电流
具体实施方式
图1为本发明一实施例的内存系统10的示意图。内存系统10包括第一内存组(memory bank)MBA、第一路径选择器YP1、第二内存组MBB、第二路径选择器YP2及感测装置100。
第一内存组MBA包括MxN个第一内存单元MCA(1,1)至MCA(M,N)，及N条第一位线BLA至BLAN，其中M为正整数，N为大于1的正整数。每一条第一位线BLA1至BLAN可耦接于MxN个第一内存单元MCA(1,1)至MCA(M,N)中的M个第一内存单元。第一路径选择器YP1包括N个输入端、第一输出端OA1及第二输出端OA2。第一路径选择器YP1的N个输入端分别耦接于N条第一位线BLA至BLAN中对应的一条第一位线。
第二内存组MBB包括MxN个第二内存单元MCB(1,1)至MCB(M,N)，及N条第二位线BLB至BLBN。每一条第二位线BLB1至BLBN可耦接于MxN个第二内存单元MCB(1,1)至MCB(M,N)中的M个第二内存单元。第二路径选择器YP2包括N个输入端、第一输出端OB1及第二输出端OB2。第二路径选择器YP2的N个输入端分别耦接于N条第二位线BLA至BLAN中对应的一条第二位线。
感测装置100耦接于第一路径选择器YP1的第一输出端OA1、第一路径选择器YP1的第二输出端OA2、第二路径选择器YP2的第一输出端OB1及第二路径选择器YP2的第一输出端OB2。感测装置100可感测所接收的电流的差异。藉由感测电流差异，便能够判别出第一内存单元MCA(1,1)至MCA(M,N)及第二内存单元MCB(1,1)至MCB(M,N)中所储存的数据。
在部分实施例中，第一内存组MBA中每M个第一内存单元会耦接于同一字符线。举例来说，第一内存单元MCA(1,1)至MCA(1,N)可耦接于字符线WLA1，而第一内存单元MCA(M,1)至MCA(M,N)可耦接于字符线WLAM。在此情况下，第一内存单元MCA(1,1)至MCA(1,N)可同步被导通，而第一内存单元MCA(M,1)至MCA(M,N)也可同步被导通。
虽然每一条字符线WLA1至WLAM可平行地逐列设置，然而第一内存组MBA的布局也可能根据系统需求而变动。举例来说，在部分实施例中，也可将多条字符线设置于相同一列，使得第一内存组MBA的布局接近正方形，减少整体字符线及位线所需的绕线总长度。
此外，第一内存单元MCA(1,1)至MCA(M,N)可包括第一组第一内存单元MSA1及第二组第一内存单元MSA2，而储存在第一组第一内存单元MSA1中的数据会与储存在第二组第一内存单元MSA2中的数据互补。举例来说，若N为正偶数，而n为N/2，则第一组第一内存单元MSA1可包括第一内存单元MCA(1,1)至MCA(M,n)而第二组第一内存单元MSA2可包括第一内存单元MCA(1,n+1)至MCA(M,N)。若M≧j≧1且n≧k≧1，则其中第一内存单元MCA(j,k)会与第一内存单元MCA(j,n+k)相对应。也就是说，第一内存单元MCA(j,k)中储存的数据会与第一内存单元MCA(j,n+k)中储存的数据为互补。
在此情况下，在选定的第一内存单元，例如第一内存单元MCA(1,1)的读取操作期间，除了选定的第一内存单元MCA(1,1)会产生读取电流之外，储存数据与第一内存单元MCA(1,1)的数据互补的第一内存单元MCA(1,n+1)也会对应产生读取电流，因此感测装置100便能够藉由判读两股读取电流的差异来辨别选定的第一内存单元中所储存的数据。
由于储存在两个对应的第一内存单元MCA(1,1)及MCA(1,n+1)的数据为彼此互补，因此两个第一内存单元MCA(1,1)及MCA(1,n+1)所产生的读取电流也会相异。举例来说，若第一内存单元MCA(1,1)为写入状态，而第一内存单元MCA(1,n+1)为清除状态，则第一内存单元MCA(1,1)可能不会产生读取电流，或仅产生微量的读取电流，而第一内存单元MCA(1,n+1)则会产生足以辨识的读取电流。第一内存单元MCA(1,1)及MCA(1,n+1)所产生的电流间的差异能够让感测装置100更快速且更准确的判别储存信息。
相似地，第二内存组MBB可与第一内存组MBA具有相同的结构，亦即第二内存组MBB中每M个第二内存单元可耦接于同一字符线。举例来说，第二内存单元MCB(1,1)至MCB(1,N)可耦接于字符线WLB1，而第二内存单元MCB(M,1)至MCB(M,N)可耦接于字符线WLBM。此外，第二内存单元MCB(1,1)至MCB(M,N)可包括第一组第二内存单元MSB1及第二组第二内存单元MSB2，而储存在第一组第二内存单元MSB1中的数据会与储存在第二组第二内存单元MSB2中的数据互补。
举例来说，第一组第二内存单元MSB1可包括第二内存单元MCB(1,1)至MCB(M,n)而第二组第二内存单元MSB2可包括第二内存单元MCB(1,n+1)至MCB(M,N)。其中第二内存单元MCB(j,k)会与第二内存单元MCB(j,n+k)相对应。也就是说，第二内存单元MCB(j,k)中储存的数据会与第二内存单元MCB(j,n+k)中储存的数据为互补。
在此情况下，为确保感测装置100能够感测选定内存单元及其对应的内存单元(例如第一内存单元MCA(1,1)及其所对应的第一内存单元MCA(1,n+1))所产生的电流差异，内存系统10可利用字符线WLA1导通第一内存单元MCA(1,1)至MCA(1,N)，第一路径选择器YP1可进一步透过位线BLA1至BLAN选择所需的第一内存单元MCA(1,1)及第一内存单元MCA(1,n+1)，而感测装置100便能够选择第一内存单元MCA(1,1)及第一内存单元MCA(1,n+1)所属的内存组。
图2为本发明一实施例的感测装置100的示意图。感测装置100包括第一内存组选择器112A、第二内存组选择器112B及差动感测放大器114。
第一内存组选择器112A具有第一输入端112A1、第二输入端112A2及输出端，第一内存组选择器112A的第一输入端112A1耦接于第一路径选择器YP1的第一输出端OA1，第一内存组选择器112A的第二输入端112A2耦接于第二路径选择器YP2的第一输出端OB1。第二内存组选择器112B具有第一输入端112B1、第二输入端112B2及输出端，第二内存组选择器112B的第一输入端112B1耦接于第一路径选择器YP1的第二输出端OA2，第二内存组选择器112B的第二输入端112A2耦接于第二路径选择器YP2的第二输出端OB2。差动感测放大器114具有第一输入端SA1及第二输入端SA2，差动感测放大器114的第一输入端SA1耦接于第一内存组选择器112A的输出端，差动感测放大器114的第二输入端SA2耦接于第二内存组选择器112B的输出端。
图3为第一内存单元MCA(1,1)被选定进行读取操作时，内存系统10的电流路径图。在第一内存单元MCA(1,1)的读取操作期间，第一路径选择器YP1可在第一路径选择器YP1中耦接至选定的第一内存单元MCA(1,1)的输入端及第一输出端OA1之间建立电性连接，并可在第一路径选择器YP1中耦接至对应于第一内存单元MCA(1,1)的第一内存单元MCA(1,n+1)的输入端及第二输出端OA2之间建立电性连接。
第一内存组选择器112A可在第一内存组选择器112A的第一输入端112A1及第一内存组选择器112A的输出端之间建立电性连接。此外，第二内存组选择器112B可在第二内存组选择器112B的第一输入端112B1及第二内存组选择器112B的输出端之间建立电性连接。
如此一来，差动感测放大器114便能够接收第一内存单元MCA(1,1)及MCA(1,n+1)所产生的读取电流Ir1及Ir(n+1)，而透过感测读取电流Ir1及Ir(n+1)的差异就能够判断储存在第一内存单元MCA(1,1)中的数据。此外，相似的操作原理也可以应用在读取第二内存组MBB的第二内存单元中的数据。
在部分实施例中，差动感测放大器114可包括预充电电路114A，预充电电路114A可在感测电流之前将差动感测放大器114的第一输入端SA1及第二输入端SA2预先充电至预定的电压，使得耦接至欲读取的两个对应内存单元的位线能够透过内存组选择器112A及112B及路径选择器被预充电至预定的电压，以确保维持感测的精确度及读取速度。
举例来说，预充电电路114A可包括第一N型晶体管及第二N型晶体管。第一N型晶体管具有汲极端及源极端，第一N型晶体管的汲极端耦接于提供预定电压的电压源，第一N型晶体管的源极端则耦接于差动感测放大器114的第一输入端SA1。第二N型晶体管具有汲极端及源极端，第二N型晶体管的汲极端耦接于可提供预定电压的电压源，第二N型晶体管的源极端则耦接于差动感测放大器114的第二输入端SA2。
然而，若充电电路114A是在内存单元MCA(1,1)及MCA(1,n+1)皆被导通且与内存单元MCA(1,1)及MCA(1,n+1)之间的电性连接也已建立的情况下进行预充电，则可能会产生漏电流。因此，为了减少漏电流，差动感测放大器114可在第一路径选择器YP1建立所需的电性连接之后进行预充电，而字符线WLA1则可在预充电电路114A完成预充电并截止之后，再将选定的第一内存单元MCA(1,1)及其对应的第一内存单元MCA(1,n+1)导通。也就是说，第一内存单元MCA(1,1)及MCA(1,n+1)可在差动感测放大器114完成预充电之后才被导通，因此可避免在预充电的操作期间因产生短路路径而造成漏电。
然而，在部分实施例中，差动感测放大器114可为栓锁器型(latch type)的放大器。在此情况下。差动感测放大器114可在第一路径选择器YP1建立所需的电性连接之后进行预充电，且字符线WLA1可在差动感测放大器114进行预充电之前导通选定的第一内存单元MCA(1,1)及对应的第一内存单元MCA(1,n+1)。
由于感测装置100可感测第一路径选择器YP1的第一输出端OA1及第二输出端OA2的电流差异，又或是感测第二路径选择器YP2的第一输出端OB1及第二输出端OB2的电流差异，因此内存系统10可以利用感测装置100来判读储存在两个内存组MBA及MBB中的信息。也就是说，在储存相同数据量的情况下，现有技术的内存系统须利用单一块大型的内存组，而内存系统10则可利用两块较小的内存组来实作。因此，在内存系统10中，每一条位在线所耦接的内存单元会较现有技术来得少，进而减少位在线的寄生电容并减少电能损耗。
再者，在部分实施例中，感测装置100可进一步感测第一路径选择器YP1的第一输出端OA1的电流、第一路径选择器YP1的第二输出端OA2的电流、第二路径选择器YP2的第一输出端OB1的电流及第二路径选择器YP2的第二输出端OB2的电流四者的一与参考电流的差异。举例来说，当内存系统10在写入操作或清除操作之后，执行检测操作以确认写入操作或清除操作是否正确执行时，又或是内存系统10在读取电流较小而不易判别的状况下，执行边界读取(margin read)操作以判读数据时，内存系统10都可能会需要将选定的内存单元产生的电流与参考电流相比较。
在图2中，感测装置100可另包括参考电流源116、第一感测选择器118A及第二感测选择器118B。感测电流源116可产生参考电流Iref。第一感测选择器118A可耦接于感测电流源116及差动感测放大器114的第一输入端SA1。第二感测选择器118B可耦接于感测电流源116及差动感测放大器114的第二输入端SA2。在部分实施例中，感测选择器118A及118B可为模拟的多任务器或开关切换电路。
图4为第一内存单元MCA(1,1)被选定进行检测操作或边界读取操作时，内存系统10的电流路径图。
在第一内存单元MCA(1,1)的检测操作或边界读取操作期间，第一路径选择器YP1可在第一路径选择器YP1的N输入端中耦接于选定的第一内存单元MCA(1,1)的输入端及第一路径选择器YP1的第一输出端OA1之间建立电性连接。第二路径选择器YP2可在第二路径选择器YP2的一输入端及第二路径选择器YP2的第二输出端OB2之间建立电性连接。第一内存组选择器112A可在第一内存组选择器112A的第一输入端112A1及第一内存组选择器112A的输出端之间建立电性连接。第二内存组选择器112B可在第二内存组选择器112B的第二输入端112B2及第二内存组选择器112B的输出端之间建立电性连接。此外，第二感测选择器118B可在参考电流源116及差动感测放大器114的第二输入端之间建立电性连接。
如此一来，差动感测放大器114便能接收到由第一内存单元MCA(1,1)产生的读取电流Ir1以及参考电流源116所产生的参考电流Iref。
此外，虽然差动感测放大器114的第二输入端可接收参考电流Iref而非第二内存单元MCB(1,1)至MCB(M,N)所产生的读取电流，然而第二内存组选择器112B及第二路径选择器YP2仍可建立对应的电性连接。透过第二内存组选择器112B及第二路径选择器YP2所建立的电性连接能够有助于提供匹配的等效电容。
举例来说，自差动感测放大器114经第一内存组选择器112A及第一路径选择器YP1至第一路径选择器YP1的输入端的路径的等效电容实质上可等于自差动感测放大器114经第二内存组选择器112B及第二路径选择器YP2至第二路径选择器YP2的输入端的路径的等效电容。因此，第一内存单元MCA(1,1)所产生的读取电流与参考电流源116所产生的参考电流Iref会具有相匹配的负载，藉以提升检测操作及边界读取操作的准确度。
此外，为减少漏电流，差动感测放大器114可在第一路径选择器YP1建立电性连接之后进行预充电，而字符线WLA1则可在差动感测放大器114完成预充电之后将第一内存单元MCA(1,1)导通。
然而，在部分实施例中，差动感测放大器114可为栓锁器型(latch type)的放大器。在此情况下。差动感测放大器114可在第一路径选择器YP1建立所需的电性连接之后进行预充电，且字符线WLA1可在差动感测放大器114进行预充电之前导通选定的第一内存单元MCA(1,1)。
利用感测选择器118A及118B，差动感测放大器114就能够在检测操作期间或边界读取操作期间接收参考电流Iref，而不会在图3的读取操作期间接收参考电流Iref。
综上所述，本发明的实施例所提供的内存系统及感测装置能够感测相异内存组的读取电流，因此能够减少单一位在线的内存单元数量。如此一来，内存系统便能以较低的读取电流操作。此外，当执行检测操作或边界读取操作时，内存系统及感测装置也能够提供匹配的负载，以提升操作的准确度。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (15)

1.一种内存系统，其特征在于，包括：
第一内存组，包括N条第一位线，N为大于1的正整数；
第一路径选择器，包括：
N个输入端，耦接于所述N条第一位线；
第一输出端；及
第二输出端；
第二内存组，包括N条第二位线；
第二路径选择器，包括：
N个输入端，耦接于所述N条第二位线；
第一输出端；及
第二输出端；及
感测装置，包括：
第一内存组选择器，具有耦接于所述第一路径选择器的所述第一输出端的第一输入端，耦接于所述第二路径选择器的所述第一输出端的第二输出端，及输出端；
第二内存组选择器，具有耦接于所述第一路径选择器的所述第二输出端的第一输入端，耦接于所述第二路径选择器的所述第二输出端的第二输出端，及输出端；及
差动感测放大器，具有耦接于所述第一内存组选择器的所述输出端的第一输入端，耦接于所述第二内存组选择器的所述输出端的第二输入端；
其中在选定的第一位线的检测操作或边界读取操作期间：
所述第一内存组选择器及所述第一路径选择器建立所述差动感测放大器的所述第一输入端及所述选定的第一位线之间的电性连接；及
所述第二内存组选择器及所述第二路径选择器建立所述差动感测放大器的所述第二输入端及所述N条第二位线中的第二位线之间的电性连接。
2.如权利要求1所述的内存系统，其特征在于：
所述第一内存组另包括MxN个第一内存单元，且所述N条第一位线中每一条第一位线是耦接于所述MxN个第一内存单元中的M个第一内存单元，其中M为正整数；及
所述第二内存组另包括MxN个第二内存单元，且所述N条第二位线中每一条第二位线是耦接于所述MxN个第二内存单元中的M个第二内存单元。
3.如权利要求2所述的内存系统，其特征在于：
所述MxN个第一内存单元包括第一组第一内存单元及第二组第一内存单元，且所述第一组第一内存单元中所储存的数据与所述第二组第一内存单元中所储存的数据为互补；及
所述MxN个第二内存单元包括第一组第二内存单元及第二组第二内存单元，且所述第一组第二内存单元中所储存的数据与所述第二组第二内存单元中所储存的数据为互补。
4.如权利要求3所述的内存系统，其特征在于在所述第一组第一内存单元中选定的第一内存单元的读取操作期间：
所述第一路径选择器于所述第一路径选择器的所述N个输入端中耦接于所述选定的第一内存单元的输入端及所述第一路径选择器的所述第一输出端之间建立第一电性连接，并于所述第一路径选择器的所述N个输入端中耦接于所述第二组第一内存单元中与所述选定的第一内存单元互补的第一内存单元的输入端及所述第一路径选择器的所述第二输出端之间建立第二电性连接；
所述第一内存组选择器于所述第一内存组选择器的所述第一输入端及所述第一内存组选择器的所述输出端之间建立电性连接；及
所述第二内存组选择器于所述第二内存组选择器的所述第一输入端及所述第二内存组选择器的所述输出端之间建立电性连接。
5.如权利要求4所述的内存系统，其特征在于所述选定的第一内存单元及与所述选定的第一内存单元互补的所述第一内存单元是耦接于相同的字符线。
6.如权利要求5所述的内存系统，其特征在于：
所述差动感测放大器是在所述第一路径选择器建立所述第一电性连接及所述第二电性连接之后进行预充电；及
所述字符线是在所述差动感测放大器进行预充电之后导通所述选定的第一内存单元及与所述选定的第一内存单元互补的所述第一内存单元。
7.如权利要求2所述的内存系统，其特征在于所述感测装置另包括：
参考电流源，用以产生感测电流；
第一感测选择器，耦接于所述参考电流源及所述差动感测放大器的所述第一输入端；及
第二感测选择器，耦接于所述参考电流源及所述差动感测放大器的所述第二输入端。
8.如权利要求7所述的内存系统，其特征在于在所述MxN个第一内存单元的选定的第一内存单元的检测操作期间或边界读取操作期间：
所述第一路径选择器于所述第一路径选择器的所述N个输入端中耦接于所述选定的第一内存单元的输入端及所述第一路径选择器的所述第一输出端之间建立电性连接；
所述第二路径选择器在所述第二路径选择器的输入端及所述第二路径选择器的所述第二输出端之间建立电性连接；
所述第一内存组选择器在所述第一内存组选择器的所述第一输入端及所述第一内存组选择器的所述输出端之间建立电性连接；
所述第二内存组选择器在所述第二内存组选择器的所述第二输入端及所述第二内存组选择器的所述输出端之间建立电性连接；及
所述第二感测选择器在所述参考电流源及所述差动感测放大器的所述第二输入端之间建立电性连接。
9.如权利要求8所述的内存系统，其特征在于：
所述差动感测放大器是在所述第一路径选择器建立所述电性连接之后进行预充电；及
字符线是在所述差动感测放大器进行预充电之后导通所述选定的第一内存单元。
10.如权利要求8所述的内存系统，其特征在于：
所述差动感测放大器是栓锁器型的放大器，且所述差动感测放大器是在所述第一路径选择器建立所述电性连接之后进行预充电；及
字符线是在所述差动感测放大器进行预充电之前导通所述选定的第一内存单元。
11.如权利要求8所述的内存系统，其特征在于自所述差动感测放大器经所述第一内存组选择器及所述第一路径选择器至所述第一路径选择器的所述输入端的路径的等效电容实质上等于自所述差动感测放大器经所述第二内存组选择器及所述第二路径选择器至所述第二路径选择器的所述输入端的路径的等效电容。
12.如权利要求2所述的内存系统，其特征在于：
所述第一内存组另包括M条字符线，每一字符线耦接于所述MxN个第一内存单元中的N个第一内存单元；及
所述第二内存组另包括M条字符线，每一字符线耦接于所述MxN个第二内存单元中的N个第二内存单元。
13.一种感测装置，其特征在于，包括：
第一内存组选择器，具有耦接于第一内存单元的第一输入端，耦接于第二内存单元的第二输出端，及输出端；
第二内存组选择器，具有耦接于第三内存单元的第一输入端，耦接于第四内存单元的第二输出端，及输出端；及
差动感测放大器，具有耦接于所述第一内存组选择器的所述输出端的第一输入端，及耦接于所述第二内存组选择器的所述输出端的第二输入端；
其中：
储存在所述第一内存单元的数据与储存在所述第二内存单元的数据为互补；及
在所述第一内存单元的读取操作期间：
所述第一内存组选择器在所述第一内存组选择器的所述第一输入端及所述第一内存组选择器的所述输出端之间建立电性连接；及
所述第二内存组选择器在所述第二内存组选择器的所述第一输入端及所述第二内存组选择器的所述输出端之间建立电性连接。
14.一种感测装置，其特征在于，包括：
第一内存组选择器，具有耦接于第一内存单元的第一输入端，耦接于第二内存单元的第二输出端，及输出端；
第二内存组选择器，具有耦接于第三内存单元的第一输入端，耦接于第四内存单元的第二输出端，及输出端；
差动感测放大器，具有耦接于所述第一内存组选择器的所述输出端的第一输入端，及耦接于所述第二内存组选择器的所述输出端的第二输入端；
参考电流源，用以产生感测电流；
第一感测选择器，耦接于所述参考电流源及所述差动感测放大器的所述第一输入端；及
第二感测选择器，耦接于所述参考电流源及所述差动感测放大器的所述第二输入端。
15.如权利要求14所述的感测装置，其特征在于在所述第一内存单元的检测操作期间或边界读取操作期间：
所述第一内存组选择器于所述第一内存组选择器的所述第一输入端及所述第一内存组选择器的所述输出端之间建立电性连接；
所述第二内存组选择器于所述第二内存组选择器的所述第二输入端及所述第二内存组选择器的所述输出端之间建立电性连接；及
所述第二感测选择器于所述参考电流源及所述差动感测放大器的所述第二输入端之间建立电性连接。
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