TWI466256B - 絕緣體上半導體金屬結構、形成該等結構之方法、及包括該等結構之半導體裝置 - Google Patents
絕緣體上半導體金屬結構、形成該等結構之方法、及包括該等結構之半導體裝置 Download PDFInfo
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- TWI466256B TWI466256B TW100106777A TW100106777A TWI466256B TW I466256 B TWI466256 B TW I466256B TW 100106777 A TW100106777 A TW 100106777A TW 100106777 A TW100106777 A TW 100106777A TW I466256 B TWI466256 B TW I466256B
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- semiconductor substrate
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- conductive material
- insulator
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Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02518—Deposited layers
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- H01L21/02532—Silicon, silicon germanium, germanium
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/30604—Chemical etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
- H01L27/1021—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
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Description
在各種實施例中本發明大體而言係關於包括一掩埋式導電材料之半導體結構,及形成此等半導體結構之方法。更具體而言,本發明之實施例係關於具有一掩埋式導電材料之一絕緣體上半導體金屬(SMOI)結構及形成此結構之方法。另外,本發明係關於包括此等SMOI結構之半導體裝置及形成此等半導體裝置之方法。
本申請案係關於在2010年3月2日提出申請之序列號為12/715,843且題目為「FLOATING BODY CELL STRUCTURES,DEVICES INCLUDING SAME,AND METHODS FOR FORMING SAME」之共同待決美國專利申請案;在2010年3月2日提出申請之序列號為12/715,743且題目為「SEMICONDUCTOR DEVICES INCLUDING A DIODE STRUCTURE OVER A CONDUCTIVE STRAP,AND METHODS OF FORMING SUCH SEMICONDUCTOR DEVICES」之共同待決美國專利申請案;在2010年3月2日提出申請之序列號為12/715,889且題目為「THYRISTOR-BASED MEMORY CELLS,DEVICES AND SYSTEMS INCLUDING THE SAME AND METHODS FOR FORMING THE SAME」之共同待決美國專利申請案;及在2010年3月2日提出申請之序列號為12/715,922且題目為「SEMICONDUCTOR CELLS,ARRAYS,DEVICES AND SYSTEMS HAVING A BURIED
CONDUCTIVE LINE AND METHODS FOR FORMING THESAME」之共同待決美國專利申請案,該等共同待決美國專利申請案所揭示之內容皆以引用之方式併入本文中。
電子行業中之共同趨勢中之一者係電子裝置微型化。對於透過使用半導體微晶片而操作之電子裝置而言尤其是這樣。微晶片通常被視為大多數電子裝置之腦子。一般而言,一微晶片包含一小的矽晶圓,可在該矽晶圓上構建經整合組態以形成電子電路之數以百萬計或數以億計的奈米觀電子裝置。以一獨特方式互連該等電路以執行一期望功能。
在期望製造高密度微晶片之情形下,有必要減小個別電子裝置及其上之互連件之大小。亦稱作所謂的「按比例縮小」運動之此運動已增加了一單個微晶片上電路之數目及複雜性。
傳統上,在一共同基板(諸如矽晶圓)上之一單個平面中並排地形成電子裝置。然而,此並排定位使用該基板上之一相對大量之表面積或「面積」。因此,可垂直地形成裝置以試圖利用較少的基板面積。為了具有競爭力,以高縱橫比(亦即,高度與寬度之比率)來形成此等垂直裝置。然而,隨著一裝置之縱橫比增加,變得越來越難以滿足對應互連件之領域及電子要求兩者。出於此原因,實際上到目前為止較簡單的平面型裝置按比例縮小在該行業佔主要地位。
一最近的趨勢係在一基板上垂直堆疊半導體裝置。然而,半導體裝置之堆疊對於連接半導體裝置之組件以及在該等堆疊之間提供有效互連添加一額外複雜性。
因此,需要形成一垂直半導體裝置之一方法,該垂直半導體裝置提供互連件對一堆疊式半導體裝置中之一電子裝置之有競爭性的可存取性。
本發明揭示一種絕緣體上半導體金屬(SMOI)結構及形成此一SMOI結構之方法。在一項實施例中,此等結構包括一第一半導體基板上之一絕緣體材料、接合至該絕緣體材料之一非晶矽材料、該非晶矽材料上方之一導電材料及該導電材料上方之一第二半導體基板。在一項實施例中,形成此等結構之方法包括形成包括形成於一第一半導體基板上方之一絕緣體材料之一受體晶圓,形成一施體晶圓,其包括:在一前驅體半導體基板上方形成一導電材料,在該導電材料上方形成一非晶矽材料,及在一深度處將離子植入至該前驅體半導體基板中以形成一經植入區。該施體晶圓之非晶矽材料可接合至該受體晶圓之絕緣體材料。然後可移除該經植入區之上的該前驅體半導體基板之一部分。
根據本發明之各種實施例而形成之SMOI結構包括接合至一絕緣體材料、一導電材料或一額外非晶矽材料之一非晶矽材料。該非晶矽材料以放熱方式與該絕緣體材料、該導電材料或該額外非晶矽材料結晶或發生反應,這允許矽原子重排,這又可改良該非晶矽材料與該絕緣體材料、該導電材料或該額外矽材料之間的介面處之接合強度。因此,產生於該非晶矽材料與該絕緣體材料、該導電材料及該額外非晶矽材料中之至少一者之間的該接合可大致比形成於兩個絕緣體材料(諸如兩個氧化物材料)之間的一接合更強。另外,該非晶矽材料至該絕緣體材料的該接合可發生在一相對低的溫度時(諸如在室溫時(自大約20℃至大約25℃)),且因此減小損壞形成於該第一半導體基板上之任一下伏裝置之風險。下文更加詳細地闡述該非晶矽材料至該絕緣體材料、該導電材料及該額外非晶矽材料中之至少一者的接合。根據本發明之各種實施例而形成之SMOI結構亦可包括安置於該絕緣體材料與該第二半導體基板之間的一導電材料。該導電材料掩埋於該第二半導體基板下面。在一些實施例中可使用該導電材料來形成一互連件(諸如一字線或一位元線)或形成一金屬條帶。可使用此一互連件以促進對形成於該第二半導體基板中之一半導體裝置之存取。
可使用根據本發明之各種實施例而形成之SMOI結構來製造各種各樣的半導體裝置,諸如包括形成於該第一半導體基板中/上之一邏輯裝置及形成該第二半導體基板中/上之一記憶體裝置之一積體電路。由於該導電材料掩埋於該第二半導體基板下面,因此可在相對少的製程動作中形成形成於該第二半導體基板上之裝置,如下文更詳細闡述。另外,形成於該第二半導體基板上/中之該等裝置可與下伏互連件及/或源極及汲極接觸件自對準從而消除對一單獨電接觸件之需要。此外,由於可在形成該SMOI結構及該記憶體裝置之前在該第一半導體基板上形成一邏輯裝置,因此該記憶體裝置不曝露至用於形成邏輯裝置之處理條件。藉由形成此等垂直自對準之堆疊式積體電路可減小單元大小,這提供增加的快取記憶體密度。
以下說明提供具體細節(諸如材料類型及處理條件),以提供對本發明之實施例之透徹說明。然而,熟習此項技術者將理解,可在不採用此等具體細節之情形下且結合習用製造技術來實踐本發明之實施例。另外,本文所提供之說明不形成用於製造包括SMOI結構之一半導體裝置之一完整製程流程。下文僅詳細闡述理解本發明之實施例所必需之彼等製程動作及結構。用以根據本發明之實施例形成包括SMOI結構之一完整半導體裝置之額外動作可藉由習用技術來執行。另外,應理解本文所闡述之方法可如所期望重複許多次以形成多個堆疊式SMOI結構。
本文所闡述之材料可藉由任一適合技術形成,包括但不限於旋塗、毯覆式塗佈、化學氣相沈積(「CVD」)、電漿增強型化學氣相沈積(「PECVD」)、原子層沈積(「ALD」)、電漿增強型ALD或物理氣相沈積(「PVD」)。另一選擇為,材料可係原位生長。熟習此項技術者可選擇適於沈積或生長一特定材料之一技術。儘管本文中所闡述及圖解說明之材料可作為層而形成,但該等材料並不限於此且可以其他三維組態而形成。
在以下實施方式中,將參照構成本文之一部分之隨附圖式,在該等隨附圖式中以圖解說明方式展示其中可實踐本發明之具體實施例。充分詳細地闡述此等實施例以使熟習此項技術者能夠實踐本發明。然而,可在不背離本發明之範疇的情形下利用其他實施例且可作出結構、邏輯及電方面之改變。本文中所呈現之圖解說明並非意欲作為任一特定系統、邏輯裝置、記憶體單元或半導體裝置之實際視圖,而僅係用以闡述本發明之實施例之理想化表示形式。本文中所呈現之該等圖式未必按比例繪製。另外,圖式之間共同的元件可保留相同數字標記。
現在參照該等圖式,其中相同元件由相同參考編號標記,圖1到圖6係形成包括一掩埋式導電材料204之一SMOI結構30(圖6)之一實施例之一方法之部分剖視圖。藉由將一受體晶圓10(圖1)與一施體晶圓20(圖2)接合來形成SMOI結構30。圖1繪示受體晶圓10。受體晶圓10可包括其上形成有一絕緣體材料104之一第一半導體基板102。第一半導體基板102可包括一製造基板,諸如半導體材料(例如矽、砷化鎵、磷化銦等)之一全或部分晶圓、一全或部分絕緣體上矽金屬(SMOI)型基板(諸如一玻璃上矽(SOG)、陶瓷上矽(SOC)或藍寶石上矽(SOS)基板)或任一其他已知適合的製造基板。如本文中所使用,術語「晶圓」包括習用晶圓以及其他塊狀半導體基板。第一半導體基板102可經摻雜或未經摻雜。一至少經部分製造之邏輯裝置(未展示)(諸如一CMOS裝置)可視需要存在於第一半導體基板102上且可係由習用技術形成。在一項實施例中,第一半導體基板102係塊狀結晶矽。
絕緣體材料104可係藉助非限定性實例包括二氧化矽、摻雜硼磷之矽玻璃(BPSG)、硼矽酸鹽玻璃(BSG)、磷矽酸鹽玻璃(PSG)或諸如此類之一介電材料。在一項實施例中,絕緣體材料104係一掩埋式氧化物。絕緣體材料104可厚為自約500至約2 μm,諸如自約1000至約2000。用於沈積且原位生長此等介電材料之技術在此項技術中習知且可包括(例如)化學氣相沈積(CVD)(諸如低壓CVD或電漿增強CVD)、原子層沈積(ALD)、旋塗沈積、熱分解或熱生長。絕緣體材料104包括一上部表面106。
圖2係用以形成SMOI結構30(圖6)之施體晶圓20之一項實施例之一部分剖視圖。施體晶圓20可包括其上形成有一導電材料204及一非晶矽材料206之一前驅體半導體基板202。在一些實施例中,一多晶矽材料或另一非晶材料(諸如非晶鍺)可替代非晶矽材料206。前驅體半導體基板202可係(例如)上文所提及之用作第一半導體基板102之製造基板中之一者。在一項實施例中,前驅體半導體基板202係一矽基板,諸如一結晶矽基板。
前驅體半導體基板202可經摻雜或未經摻雜。導電材料204可係一低電阻率材料,其包括但不限於一相變材料、鈦、矽化鈦、氧化鈦、氮化鈦、坦、矽化坦、氧化坦、氮化坦、鎢、矽化鎢、氧化鎢、氮化鎢、其他金屬、金屬矽化物、金屬氧化物或金屬氮化物材料或其等之組合,包括多個不同的導電材料。在一項實施例中,導電材料204可係由氮化鈦形成,此乃因氮化鈦對許多材料(諸如用作前驅體半導體基板202之材料)具有良好黏附或黏附性。氮化鈦亦具有使其不受高處理溫度影響之一高熔點(約3000℃)。氮化鈦亦與其他導電材料具有極佳的歐姆接觸。氮化鈦亦通用於半導體製造中,且因此可易於併入至習用製造製程中。在一項實施例中,導電材料204係一富含鈦之氮化鈦,諸如氮化鈦金屬模式(MMTiN)。導電材料204亦可係由多種導電材料形成。在一項實施例中,導電材料204係前驅體半導體基板202上方之一MMTiN材料及MMTiN材料上方之矽化鎢材料。在另一實施例中,導電材料204可係由一金屬(諸如,鈦、鎢或鋁)形成,其中其上形成鈦材料層。可端視於該材料來最佳化導電材料204之厚度以在導電材料204與前驅體半導體基板202之間提供一低歐姆接觸。舉例而言,若導電材料204係氮化鈦(諸如MMTiN),則導電材料204可具有自約10 nm至約50 nm之一厚度。可藉助此項技術中習知之一沈積技術(諸如,例如原子層沈積(ALD)、化學氣相沈積(CVD)或電漿氣相沈積(PVD))來形成導電材料204。
可藉助此項技術中習知之一沈積技術(諸如,例如ALD、CVD或PVD)在導電材料204上方形成非晶矽材料206。在一項實施例中,可藉助PVD後跟化學機械平坦化(CMP)在導電材料204上形成非晶矽材料206。非晶矽材料206可厚得足以黏附至受體晶圓10之絕緣體材料104上,如下文更詳細闡述。舉例而言,非晶矽材料206之厚度可係自約10 nm至約50 nm。非晶矽材料206包括一表面212。
如圖2中所繪示,施體晶圓20亦可包括藉由使一原子物質植入至前驅體半導體基板202中而形成之一裂開部分208。原子物質可係氫離子、稀有氣體離子(亦稱作惰性或不活躍氣體)或氟離子。原子物質可植入至施體晶圓20之前驅體半導體基板202中以形成一經植入區210。可在於該前驅體半導體基板上形成導電材料204之前、於其上形成導電材料204之後或於其上形成非晶矽材料206之後將原子物質植入至前驅體半導體基板202中。經植入區210可於一期望深度處形成於前驅體半導體基板202中,這相依於此項技術中習知之諸如原子物質之植入劑量及能量之參數。經植入區210之深度可對應於SMOI結構30(圖6)之一第二半導體基板202'之厚度。經植入區210可包括包括經植入原子物質之微泡或微腔,這在前驅體半導體基板202內提供一弱化區。可在植入受影響之溫度之上但在導電材料204之融化溫度之下的一溫度時對施體晶圓20進行熱處理以影響施體晶圓20中之結晶重排及微泡或微腔之聚結。如下文所闡述,施體晶圓20可在經植入區210處裂開從而形成SMOI結構30(圖6)上之第二半導體基板202'以及裂開部分208。為澄清起見,本文中使用術語「第二半導體基板」來指代在移除裂開部分208之後的半導體結構,而本文中使用術語「前驅體半導體基板」來指代移除裂開部分208之前的半導體結構。
如圖3及圖4中所展示,施體晶圓20可疊加至受體晶圓10上以使施體晶圓20之非晶矽材料206與受體晶圓10之絕緣體材料104接觸(圖4)。然後施體晶圓20之非晶矽材料206可藉由曝露至熱而接合至絕緣體材料104。在使施體晶圓20接合至受體晶圓10之前,可視需要處理非晶矽材料206之表面212及絕緣體材料104之上部表面106中之至少一者以改良非晶矽材料206與絕緣體材料104之間的接合強度。此等處理技術在此項技術中習知且包括化學、電漿或植入活化。舉例而言,可藉助一稀釋的氫氧化氨或氟化氫溶液來處理絕緣體材料104之上部表面106。非晶矽材料206之表面212亦可曝露至(例如)氬電漿以形成一電漿活性表面。非晶矽材料206之表面212及絕緣體材料104之上部表面中之至少一者活化可由於產生於非晶矽材料205之表面212及絕緣體材料104之上部表面106上之離子物質(例如,氫)之行動性增加而使其間之後續接合之動力增加。
如圖4中所展示,施體晶圓20之非晶矽材料206可與受體晶圓10之絕緣體材料104接觸並接合以形成SMOI結構30之一前驅體。可藉由(例如)將SMOI結構30加熱至小於約600℃(諸如自約300℃至約400℃)之一溫度而使非晶矽材料206接合至絕緣體材料104。若絕緣體材料104係由二氧化矽形成,則非晶矽材料206與絕緣體材料104之間可形成氧化矽接合。由於導電材料204可係由一金屬或且他熱敏材料形成,因此SMOI結構30曝露至的溫度可小於導電材料204之熔點。非晶矽材料206與絕緣體材料104亦可在沒有熱之情形下(諸如在室溫時(自約20℃至約25℃))接合。亦可對施體晶圓20及受體晶圓10施加壓力以使非晶矽材料206接合至絕緣體材料104。一旦施體晶圓20接合至受體晶圓10,來自施體晶圓20之導電材料204就可形成安置於絕緣體材料104與前驅體半導體基板202之間的一掩埋式導電材料。
為了形成SMOI結構30(圖6),可自前驅體半導體基板202移除裂開部分208,如圖5中所展示。可藉助此項技術中習知之技術來移除裂開部分208,諸如藉由對經植入區210施加一剪切力或藉由在經植入區210處施加熱或一噴氣流。植入於經植入區210中之氫或其他離子在前驅體半導體基板202中生成易受裂開影響之一弱化區。第二半導體基板202'之剩餘部分可具有(例如)自約50 nm至約500 nm(自約500至約5000)之一厚度。在移除裂開部分208之後曝露之SMOI結構30之一表面302可粗糙且參差不齊。可使SMOI結構30之曝露表面302平滑至一期望程度以促進對SMOI結構30進行進一步處理,如下文所闡述。可根據習用技術(諸如,例如研磨、濕式蝕刻、化學機械拋光(CMP)及平面反應離子蝕刻(RIE)中之一者或多者)使SMOI結構之曝露表面302平滑。
可藉助SMART-層轉移技術之修改形式來形成SMOI結構30及下文所闡述之其他結構。SMART-層轉移技術詳細闡述於(例如)頒予Bruel之美國專利第RE 39,484號、頒予Aspar等人之美國專利第6,303,468號、頒予Aspar等人之美國專利第6,335,258號、頒予Moriceau等人之美國專利第6,756,286號、頒予Aspar等人之美國專利第6,809,044號、頒予Aspar等人之美國專利第6,946,365號及頒予Dupont之美國專利申請公開案第2006/0099776號。然而,若維持足夠低的製程溫度,則亦可使用適用於製造一SMOI基板之其他製程。在SMART-層轉移技術之習用實施方案中,使用一高溫退火而將施體晶圓與受體晶圓接合在一起。用以接合施體晶圓與受體晶圓之溫度係自約1000℃至約1300℃。然而,由於在本文所闡述之SMOI結構中存在導電材料204,因此在某些情形下本發明之SMOI結構可不能承受曝露至此等溫度下而不受到熱損壞。因此如上文所闡述,可使用較低溫度來接合受體晶圓10與施體晶圓20。
圖6係對在曝露表面302已平滑之後的SMOI結構30之一圖解說明。一旦施體晶圓20接合至受體晶圓10且曝露表面302平滑,一半導體裝置(諸如一記憶體單元)就可形成於SMOI結構30之第二半導體基板202'上及/或內。如下文所闡述,SMOI結構30之導電材料204可用作(例如)一互連件(諸如一位元線或字線)、用作一閘極或用作一金屬條帶。
圖7到圖10係形成包括一掩埋式導電矽化物材料410之一SMOI結構50(圖10)之一實施例之一方法之部分剖視圖。圖7圖解說明用以形成SMOI結構50(圖10)之一受體晶圓11。除了非晶矽材料206可形成於受體晶圓10上之絕緣體材料上方之外,受體晶圓11可大致類似於上文所闡述之受體晶圓10且可如上文關於圖1所闡述而形成。如圖7中所展示,受體晶圓11可包括形成於絕緣體材料104上方之非晶矽材料206及形成於第一半導體基板102上方之絕緣體材料104。
圖8係用以形成SMOI結構50(圖10)之一施體晶圓40之一項實施例之一部分剖視圖。除了施體晶圓40可包括一可選性非反應性導電材料402及一反應性導電材料404而不是導電材料204(圖2)且非晶矽材料206(圖2)不形成於施體晶圓40上之外,施體晶圓40可大致類似於上文所闡述之施體晶圓20且可如上文關於圖2所闡述而形成。非反應性導電材料402可係由(例如)一金屬氮化物(諸如氮化鈦)形成。然而,可使用將不與反應性導電材料40或其一反應生成物發生化學反應之任一導電材料。與反應性導電材料404之厚度相比,非反應性導電材料402之厚度可相對薄。舉例而言,非反應性導電材料402可具有自約20Å至約200Å之一厚度。反應性導電材料404可係由能夠與非晶矽材料206發生反應之一金屬形成或充當用於使非晶矽材料206結晶之一觸媒。在一項實施例中,反應性導電材料404係鈦。反應性導電材料404可具有自約200Å至約500Å之一厚度。可藉助此項技術中習知之一沈積技術來形成非反應性導電材料402及反應性導電材料404,諸如,例如ALD、CVD或PVD。
如圖9中所展示,施體晶圓40可疊加至受體晶圓11上並
接合至其且裂開部分208(圖8)被移除,如前文關於圖3至圖6所闡述。所得的SMOI結構50可包括第一半導體基板102、絕緣體材料104、非晶矽材料206、反應性導電材料404、非反應性導電材料402及第二半導體基板202'。
如圖10中所展示,SMOI結構50可經退火以使反應性導電材料404與非晶矽材料206發生化學反應從而形成導電矽化物材料410,該導電矽化物材料掩埋於非反應性導電材料402下面。反應性導電材料404可係由鈦形成,其與非晶矽材料206發生反應以形成作為導電矽化物材料410之矽化鈦。反應性導電材料404及非反應性導電材料402亦可係一單個材料,諸如富含鈦之氮化鈦(MMTi)。該富含鈦之氮化鈦中之過量鈦可與非晶矽材料206發生反應從而形成導電矽化物材料410。對SMOI結構50進行退火以形成導電矽化物材料410可發生在(例如)自約600℃至約800℃之一溫度時。導電矽化物材料410與絕緣體材料104之間的接合強度可比非晶矽材料206與絕緣體材料104之間的接合強度大。與反應性導電材料404相比,導電矽化物材料410可對SMOI結構50提供一較低電阻。
圖11到圖14係形成包括掩埋於一經摻雜半導體基板下面之一導電材料之一SMOI結構70(圖14)之一實施例之一方法之部分剖視圖。圖11圖解說明係圖1之一大致複製品且可如上文關於圖1所闡述而形成之一受體晶圓10。如圖11中所展示,該受體晶圓可包括形成於第一半導體基板102上方之絕緣體材料104。
圖12係用以形成SMOI結構70(圖14)之一施體晶圓60之一項實施例之一部分剖視圖。施體晶圓60可類似於上文所闡述之施體晶圓20而包括一前驅體半導電基板202且可如上文關於圖2所闡述而形成。如此項技術中習知,前驅體半導電基板202可經摻雜且活化以形成一P+經摻雜區602、一N-經摻雜區604及一N+經摻雜區606。在一項實施例中,當該前驅體半導電基板還未包括可受此等高溫製程損壞之一MMTiN材料610時(圖13),可使用一高溫製程來摻雜前驅體半導電基板202。在另一實施例中,可在已使用用於達成較佳摻雜劑輪廓控制之一低溫製程形成了SMOI裝置70(圖14)之後形成P+經摻雜區602。儘管圖12繪示為包括P+經摻雜區602、N-經摻雜區604及N+經摻雜區606之一特定次序,但應理解熟習此項技術者可選擇經摻雜區之任一組合以達成SMOI結構70(圖14)之期望功能。由於施體晶圓60具有可自其植入期望摻雜劑之兩個曝露表面,因此與在施體晶圓60接合至受體晶圓10之後形成經摻雜區之情形相比,經摻雜區602、604、606之深度及濃度(亦即,高摻雜或輕摻雜)可更容易且更準確地得以控制。如圖12中所展示,一矽化物材料608可形成於前驅體半導體基板202上方,諸如N+經摻雜區606上方。可藉由在前驅體半導體基板202上方形成反應性導電材料以使該反應性導電材料與前驅體半導體基板202發生反應以形成矽化物材料608來形成矽化物材料608。矽化物材料608可與前驅體半導體基板202具有一低歐姆接觸。可在矽化物材料608上方形成氮化鈦金屬模式(MMTiN)材料。可藉助此項技術中習知之一沈積技術(諸如,例如ALD、CVD或PVD)來形成MMTiN材料610及矽化鎢材料612。與MMTiN材料610之厚度相比,矽化物材料608之厚度可相對薄。舉例而言,矽化物材料608可具有自約50至約500之一厚度。MMTiN材料610可具有自約500至約1000之一厚度。而且如圖12中所繪示,可藉由將一原子物質植入至前驅體半導體基板202中來形成裂開部分208,從而如前文關於圖2所闡述而形成經植入區210。如圖12中所展示,可在前驅體半導體基板202之P+經摻雜區602內形成經植入區210。在形成經植入區210時矽化物材料608及MMTiN材料610可對原子物質之植入具有一大致最小影響。
如圖13中所展示,矽化鎢材料612及一非晶矽材料206可形成於矽化物材料608上方。可藉助此項技術中習知之一沈積技術(諸如,例如ALD、CVD或PVD)來形成矽化鎢材料612。矽化鎢材料612可係比MMTiN氮化物材料610更佳之一導體。在一些實施例中,可在形成經植入區210之後在矽化鈦材料612及MMTiN材料610上方形成矽化鎢材料612。
如圖14中所展示,施體晶圓60可疊加至受體晶圓10上並接合至其且裂開部分208(圖13)被移除,如前文關於圖3至圖6所闡述。所得的SMOI結構70可包括第一半導體基板102、絕緣體材料104、非晶矽材料206、矽化鎢材料612、MMTiN材料610、矽化物材料608及包括N+經摻雜區606、N-經摻雜區604及P+經摻雜區602之第二半導體基板202'。在一些實施例中,可在P+經摻雜區602上方形成一第二導電材料(未展示)以形成可用以形成如下文更詳細闡述之一半導體裝置之一頂部電極。
圖15到圖18係形成包括一經摻雜半導體材料之一SMOI結構90(圖18)之一實施例之另一方法之部分剖視圖。圖15係圖1之一大致複製品且可如上文關於圖1所闡述而形成。如圖15中所展示,受體晶圓10包括形成於第一半導體基板102上方之絕緣體材料104。
圖16係用以形成SMOI結構90(圖18)之一施體晶圓80之一項實施例之一部分剖視圖。除了施體晶圓80可包括安置於前驅體半導體基板202與導電材料204之間的一經摻雜半導電材料802之外,施體晶圓80可大致類似於上文關於圖2所闡述之施體晶圓20且可如上文關於圖2所闡述而形成。經摻雜半導電材料802可係由(例如)鍺(Ge)、碳化矽(SiC)及氮化鎵(GaN)中之至少一者形成。前驅體半導體基板202可經摻雜以形成至少一個P+或N+經摻雜區804。經摻雜半導電材料802亦可經摻雜以形成一P經摻雜區806及一N經摻雜區808。在一個實例中,P經摻雜區806可包括毗鄰前驅體半導體基板202之P+或N+經摻雜區804之一P經摻雜碳化矽材料且N-經摻雜區808可包括毗鄰P經摻雜區806之一N經摻雜碳化矽材料。可使用習用沈積或原位生長技術(且其可包括(例如)化學氣相沈積(CVD)(諸如低壓CVD或電漿增強CVD)、原子層沈積(ALD)、旋塗沈積、熱分解或熱生長)在前驅體半導體基板202上形成經摻雜半導電材料802。可在經摻雜半導電材料802上方沈積導電材料204及非晶矽材料206,且可藉助一原子物質植入前驅體半導體基板202形成經植入區210及裂開部分208,如上文關於圖2所闡述。
如圖17中所展示,施體晶圓80可疊加至受體晶圓10上並接合至其且裂開部分208被移除,如前文關於圖3至圖6所闡述。所得的SMOI結構90包括第一半導體基板102、絕緣體材料104、非晶矽材料206、導電材料204、包括N經摻雜區808及P經摻雜區806之經摻雜半導電材料802及包括P+或N+經摻雜區804之第二半導體基板202'。如圖18中所展示,可使用此項技術中習知之技術(諸如CMP)來拋光第二半導體基板202'。
圖19到圖21係形成包括絕緣體材料104及一高k介電材料112之一SMOI結構120(圖21)之一實施例之另一方法之部分剖視圖。圖19係圖1之一大致複製品且可如上文關於圖1所闡述而形成。如圖19中所展示,受體晶圓10包括形成於第一半導體基板102上方之絕緣體材料104。
圖20係用以形成SMOI結構120(圖21)之一施體晶圓110之一項實施例之一部分剖視圖。除了施體晶圓110包括安置於前驅體半導體基板202與導電材料204之間的一高k介電材料112之外,施體晶圓110可大致類似於上文關於圖2所闡述之施體晶圓20且可如上文關於圖2所闡述而形成。高k介電材料112可係由(例如)二氧化矽、氧化鉿及鋯、鋁、鑭、鍶、鈦或其組合之其他氧化物、矽酸鹽或鋁酸鹽(其包括但不限於Ta2
O5
、ZrO2
、HfO2
、TiO2
、Al2
O3
、Y2
O3
、La2
O3
、HfSiOx
、ZrSiOx
、LaSiOx
、YSiOx
、ScSiOx
、CeSiOx
、HfLaSiOx
、HfAlOx
、ZrAlOx
及LaAlOx
)。另外,可在單層或複合層中使用多金屬氧化物,諸如氮氧化鉿、氮氧化銥及其他高k介電材料。可使用習用沈積或原位生長技術(且其可包括(例如)化學氣相沈積(CVD)(諸如低壓CVD或電漿增強CVD)、原子層沈積(ALD)、旋塗沈積、熱分解或熱生長)在前驅體半導體基板202上形成高k介電材料112。視需要,施體晶圓110亦可包括一金屬113及一經摻雜區115。金屬113可包括諸如鈦金屬模式(MMTi)、鈦(Ti)、坦(Ta)、鈷(Co)及鎳(Ni)之(例如)一反應性導體。可在高k介電材料112上方沈積導電材料204及非晶矽材料206,且可藉助一原子物質植入前驅體半導體基板202形成經植入區210及裂開部分208,如上文關於圖2所闡述。
如圖21中所展示,施體晶圓110可疊加至受體晶圓10上並接合至其且裂開部分208(圖20)被移除,如前文關於圖3至圖6所闡述。所得的SMOI結構120包括基板102、絕緣體材料104、非晶矽材料206、導電材料204、高k介電材料112及第二半導體基板202'。
圖22到圖28係形成包括一經圖案化導電材料204'之一SMOI結構140(圖28)之另一實施例之一方法之剖視圖。圖22係圖1之一大致複製品且可如上文關於圖1所闡述而形成。如圖22中所展示,受體晶圓10包括形成於第一半導體基板102上方之絕緣體材料104。
圖23係用以形成SMOI結構140(圖28)之一施體晶圓130之一項實施例之一部分剖視圖。施體晶圓130包括其上形成有導電材料204及一蓋帽材料132之前驅體半導體基板202。蓋帽材料132可係由一介電材料(諸如氮化物材料或氧化物材料)形成。可藉助此項技術中習知之沈積技術(包括但不限於ALD、CVD或PVD)來形成蓋帽材料132。
如圖24中所展示,蓋帽材料132及導電材料204可經圖案化以形成包括經圖案化蓋帽材料132'及經圖案化導電材料204'之至少一個結構134。可使用此項技術中習知之技術(諸如光阻劑遮蔽及各向異性蝕刻)來圖案化蓋帽材料132及導電材料204。另一選擇為,在一些實施例中,可使用一鑲嵌流程(其在此項技術中習知且因此本文未詳細闡述)使經圖案化蓋帽材料132'及經圖案化導電材料204'形成為至少一個結構134。如圖25中所展示,可在具有經圖案化蓋帽材料132'及經圖案化導電材料204'之至少一個結構134上方沈積一層間介電材料136。層間介電材料136可用以使至少一個結構134與一毗鄰結構134隔離。如圖26中所展示,可(諸如)藉助此項技術中習知之CMP來移除層間介電材料136以曝露經圖案化蓋帽材料132'之一上部表面。經圖案化蓋帽材料132'可充當一CMP終止層。
如圖27中所展示,可在層間介電材料136及經圖案化蓋帽材料132'上方形成非晶矽材料206。亦可藉助一原子物質來植入施體晶圓130從而形成經植入區210及裂開部分208,如前文關於圖2所闡述。如圖28中所展示,施體晶圓130可疊加至受體晶圓10並接合至其且裂開部分208被移除,如前文關於圖3至圖6所闡述。所得的SMOI結構140包括第一半導體基板102、絕緣體材料104、非晶矽材料206、具有經圖案化蓋帽材料132'及導電材料204'之至少一個結構134及第二半導體基板202',該至少一個結構134係由層間介電材料136電隔離。由於包括導電材料204'之柱134經圖案化且由層間介電材料136分離,因此導電材料204'可在無進一步處理之情形下用作一互連件(諸如一字線或一位元線),如下文更詳細闡述。
在額外實施例中,導電材料204可形成於一受體晶圓而非一施體晶圓上。舉例而言,圖29至圖31圖解說明形成包括導電材料204之一SMOI結構170(圖31)之一實施例之另一方法之部分剖視圖。如圖29中所展示,一受體晶圓150包括第一半導體基板102、絕緣體材料104及導電材料204。受體晶圓150可視需要包括一接合材料152。接合材料152(若存在)可如前文所闡述係一非晶矽材料,或接合材料152可係氧化物材料,諸如二氧化矽。在一些實施例中,可圖案化並用一層間介電材料(未展示)填充導電材料204,如上文關於圖22至圖28所闡述。
圖30係用以形成SMOI結構170(圖31)之一施體晶圓160之一項實施例之一部分剖視圖。施體晶圓160可包括前驅體半導體基板202及非晶矽材料206。可藉助一原子物質來植入施體晶圓160從而形成經植入區210及裂開部分208,如前文關於圖2所闡述。
如圖31中所展示,施體晶圓160可疊加至受體晶圓150上並接合至其且裂開部分208可被移除,如前文關於圖3至圖6所闡述。所得的SMOI結構170包括第一半導體基板102、絕緣體材料104、導電材料204、接合至非晶矽材料206之接合材料152(若存在)及第二半導體基板202'。
在額外實施例中,可藉由在一施體晶圓上產生多個矽材料層來形成多個SMOI結構。舉例而言,圖32至圖34圖解說明形成包括一導電材料204之一SMOI結構200(圖32)之一實施例之另一方法之部分剖視圖。如圖32中所展示,一受體晶圓180包括第一半導體基板102、絕緣體材料104及導電材料204。
圖33係用以形成SMOI結構200(圖34)之一施體晶圓190之一項實施例之一部分剖視圖。施體晶圓190可包括前驅體半導體基板202、鍺化矽(SiGe)材料192之至少一個部分及一磊晶(EPI)矽材料194之至少一個部分。可藉助此項技術中習知之方法且以任一期望厚度形成SiGe材料192及EPI矽材料194。另外,SiGe材料192及EPI矽材料194可經摻雜或未經摻雜。儘管圖33展示SiGe材料192之一個部分及EPI矽材料194之一個部分,但可藉由形成SiGe材料192及EPI矽材料194之交替部分而存在多個部分。在一些實施例中,可視需要在EPI矽材料194或SiGe材料192之最上部分上方形成以虛線圖解說明之非晶矽材料206。在一些實施例中,可省略非晶矽材料206且可使EPI矽材料194或SiGe材料192之最上部分接合至受體晶圓180。亦可藉助一原子物質來植入施體晶圓190從而形成經植入區210及裂開部分208,如前文關於圖2所闡述。
如圖34中所展示,施體晶圓190可疊加至受體晶圓180上並接合至其且裂開部分208可被移除,如前文關於圖3至圖6所闡述。所得的SMOI結構200包括第一半導體基板102、絕緣體材料104、導電材料204、非晶矽材料206(若存在)、EPI矽材料194之至少一個部分、SiGe材料192之至少一個部分及第二半導體基板202'。儘管將圖33繪示為使非晶矽材料206接合至導電材料204,但EPI矽材料194、SiGe材料192或非晶矽材料206(若存在)中之任一者可用以使施體晶圓190接合至受體晶圓180。一旦形成SMOI結構200,就可(諸如,例如)利用一濕式底切蝕刻來移除SiGe材料192之部分。然後可藉助一介電材料(未展示)(諸如氧化物材料)重新填充SiGe材料192之經移除部分或可留下該經移除部分未填充從而形成一氣隙(未展示)。藉助一介電材料或一氣隙來替代SiGe材料192之部分可用以在基板102上形成多個SMOI結構。在又另外實施例中,可在沒有導電材料204之情形下形成SMOI結構200,因而在沒有導電材料204之情形下在基板102上形成多個SMOI結構。
在額外實施例中,可藉助多部分掩埋式介電材料來形成SMOI結構。舉例而言,圖35至圖38圖解說明形成包括多部分掩埋式介電材料之一SMOI結構250(圖38)之一實施例之另一方法之部分剖視圖。如圖35中所展示,一受體晶圓220包括第一半導體基板102、絕緣體材料104、氧化物材料222之至少一個部分及氮化物材料224之至少一個部分。在一些實施例中,可視需要省略絕緣體材料104。可在交替部分中形成氧化物材料222及氮化物材料224。可藉助此項技術中習知之方法且以任一期望厚度形成氧化物材料222及氮化物材料224。儘管將圖35圖解說明為包括與兩個部分之氮化物材料224交替之兩個部分之氧化物材料222,但應理解可存在任一數目個氧化物材料222及氮化物材料224部分。
圖36係用以形成SMOI結構250(圖38)之一施體晶圓230之一項實施例之一部分剖視圖。施體晶圓230可大致類似於上文在圖2中所闡述之施體晶圓20且可如上文關於圖2所闡述而形成。如圖36中所展示,施體晶圓230可包括前驅體半導體基板202及非晶矽材料206。亦可藉助一原子物質來植入施體晶圓230從而形成經植入區210及裂開部分208。
如圖37中所展示,施體晶圓230可疊加至受體晶圓220上並接合至其且裂開部分208可被移除,如前文關於圖3至圖6所闡述。一所得的SMOI結構240包括第一半導體基板102、絕緣體材料104、氧化物材料222之至少一個部分、氮化物材料224之至少一個部分、非晶矽材料206及第二半導體基板202'。儘管將圖37繪示為使非晶矽材料206接合至氧化物材料222之至少一個部分,但氮化物材料224之至少一個部分、氧化物材料222之至少一個部分或一額外非晶矽材料(未展示)中之任一者可用以使施體晶圓230接合至受體晶圓220。一旦形成SMOI結構240,就可(諸如,例如)藉由利用一濕式蝕刻之一選擇性底切來選擇性地移除氮化物材料224之部分。然後可藉助一導電材料226重新填充氮化物材料224之經移除部分,從而形成圖38中所展示之SMOI結構250。藉助導電材料226替代氮化物材料224可用以形成具有多個掩埋式導電材料層226之一SMOI結構250。儘管展示導電材料層226具有相等厚度,但應理解不同的導電材料層226可端視於SMOI結構250之期望用途而具有變化的厚度。該多個導電材料層226可用以形成多個互連件,諸如字線及位元線。在額外實施例中,當在第二半導體基板202'上/中形成一半導體裝置時,僅可利用導電材料226之最上部分來形成如下文更詳細闡述之一半導體裝置,且導電材料226之下部部分可保持完好無損。導電材料226之保持完好無損之下部部分可幫助改良SMOI結構250之接合強度及穩定性。
可利用本文所闡述之SMOI結構30、50、70、90、120、140、170、200、250來形成此項技術中習知之若干個半導體裝置,其包括在Tang等人之題目為One-transistor Memory Cell with Bias Gate之美國專利第7,589,995號、Ananthan等人之題目為Dual Work Function Recessed Access Device and Methods of Forming之美國專利申請公開案第2007/0264771號、Tang等人之題目為Methods,Devices,and Systems Relating to Memory Cells Having a Floating Body之美國專利申請案第12/410,207號、Tang之題目為Methods,Devices,and Systems Relating to Memory Cells Having a Floating Body之美國專利申請案第12/419,658號中所闡述之彼等半導體裝置。前述文件中之每一者之揭示內容以全文引用之方式併入本文中。SMOI結構30、50、70、90、120、140、170、200、250可用以形成具有兩個或多個端子之任一半導體裝置。舉例而言,SMOI結構30、50、70、90、120、140、170、200、250可用以形成動態隨機存取記憶體(DRAM)、電阻式非揮發性RAM(ReRAM)、相變RAM(PCRAM)、一次可程式化唯讀記憶體(OTP ROM)或快取記憶體裝置。
圖39圖解說明一半導體裝置300之一實施例之一個實例,該半導體裝置包括具有掩埋於一第二半導體基板312下面之一導電材料304之一SMOI結構301。SMOI結構301可包括(例如)一第一半導體基板306、一絕緣體材料308、一非晶矽材料310、導電材料304及第二半導體基板312。可以類同於上文相關於圖1至6、7至10、11至14、15至18、19至21、22至28、32至34或35至38所闡述之方式之一方式來形成SMOI結構301。
可藉助習用技術在一第一方向上圖案化非晶矽材料310、導電材料304及第二半導體基板312以形成位元線314。另一選擇為,若以類同於上文相關於圖22至圖28所闡述之方式之一方式形成SMOI結構301,則可已在該第一方向上圖案化了導電材料304。可藉助習用技術在垂直於該第一方向之一第二方向上圖案化第二半導體基板312以在位元線314之上形成柱316。如此項技術中所習知,柱316可經摻雜以形成一汲極區318、一源極區320及一通道區322。另一選擇為,第二半導體基板312可已經經摻雜,如前文關於圖11至圖14及圖15至圖18所闡述。由於汲極區318、源極區320及通道區322自柱316之本體垂直形成且柱316直接在位元線314之頂部,因此與一習用平面配置之情形相比可達成一較高裝置密度。可在毗鄰通道區322之柱316之側壁上形成一閘極電介質324。亦可在毗鄰閘極電介質324之柱316之側壁上形成一閘極326。可使用包括習用間隔件蝕刻技術(本文未詳細闡述)之習用技術來形成閘極電介質324及閘極326。
藉由利用SMOI結構301來形成半導體裝置300,可在少至三個圖案化動作中形成半導體裝置300。如前文所闡述,可在一第一方向上圖案化第二半導體基板312以形成位元線314,可在一第二方向上圖案化第二半導體基板312以在該等位元線之上形成柱316,且可圖案化閘極326及閘極電介質324以在柱316之側壁上形成閘極326及閘極電介質324。另外,由於汲極區318、源極區320及通道區322係由位元線314之上的柱316形成,因此不需要單獨接觸件而使位元線314與汲極區318電連接。此外,由於可在形成半導體裝置300之前在第一半導體基板306上形成一邏輯裝置(未展示)及後段工藝製程(BEOL)元件(未展示),因此半導體裝置300不曝露至用於形成邏輯裝置及BEOL元件之處理條件。避免曝露至此等處理條件可改良半導體裝置300之可靠性。
圖40圖解說明一半導體裝置400之另一實施例,該半導體裝置包括具有掩埋於一第二半導體基板412下面之一導電材料403之一SMOI結構401。半導體裝置400可包括耦合至一存取裝置(諸如二極體422)之一記憶體單元。SMOI結構401可包括(例如)一第一半導體基板406、一介電材料408、一非晶矽材料409、導電材料403及第二半導體基板412。可以類同於上文相關於圖1至6、7至10、11至14、15至18、19至21、22至28、32至34或35至38所闡述之方式之一方式來形成SMOI結構401。
可藉助習用技術在一第一方向上圖案化非晶矽材料409、導電材料403及第二半導體基板412以形成字線415。另一選擇為,若以類同於上文相關於圖22至圖28所闡述之方式之一方式形成SMOI結構401,則可已在該第一方向上圖案化了導電材料403。可在一第二方向上藉助習用技術來圖案化第二半導體基板412之一部分以形成一柱423。可藉助習用技術來摻雜第二半導體基板412以在字線415上方形成二極體422。舉例而言,第二半導體基板412可係由一單晶矽材料形成且可經摻雜以形成一N經摻雜矽材料414及一P經摻雜矽材料416。N經摻雜矽材料414可包括在字線415上方延伸之第二半導體基板412之未在該第二方向上經蝕刻之一部分。P經摻雜矽材料416可包括第二半導體基板412之在該第二方向上經蝕刻之部分以形成柱423。另一選擇為,第二半導體基板可已經摻雜,如前文關於圖11至14及圖15至18所闡述。可使用習用技術在二極體412上方形成記憶體裝置400之一底部電極418。舉例而言,在一項實施例中,可在圖案化第二半導體基板412之前在第二半導體基板412上方沈積底部電極418之材料。然後可使用習用技術圖案化且蝕刻底部電極418之材料,與此同時圖案化且蝕刻第二半導體基板412。使用本文未詳細闡述之習用技術,可在二極體422上方形成一記憶體媒體420及一端電極或位元線424且使其與該二極體電通信。
藉由利用SMOI結構401來形成半導體裝置400,可在少至三個圖案化動作中形成半導體裝置400。如前文所闡述,可在一第一方向上圖案化非晶矽材料409、導電材料403及第二半導體基板412以形成字線415;可在一第二方向上圖案化第二半導體基板412及底部電極418以形成二極體422及底部電極418;及可圖案化記憶體媒體420及位元線424以在二極體422之上形成記憶體媒體420及位元線424。由於記憶體媒體420係欲最後沈積之材料中之一者,因此由於記憶體媒體420可不曝露至高處理溫度且不受高處理溫度改變,因此相變或抗變材料可用作記憶體媒體420。
圖41圖解說明一半導體裝置500之另一實施例,該半導體裝置包括具有掩埋於一第二半導體基板514下面之一導電材料504之一SMOI結構502。半導體裝置500可包括形成於SMOI結構502上方及/或內之一浮體記憶體單元501。SMOI結構502可包括(例如)一第一半導體基板506、一絕緣體材料508、一非晶矽材料510、導電材料504、一高k閘極介電材料512及第二半導體基板514。可以類同於上文相關於圖29至圖31所闡述之方式之一方式形成SMOI結構502。
浮體記憶體單元501包括在側上由一額外絕緣體材料518環繞之一主動區516。主動區516可係由第二矽基板514之單晶矽形成。第二矽基板514之總厚度可用以形成浮體記憶體單元501、形成一背閘極-電介質之下伏之高k閘極介電材料512及形成一金屬背閘極之導電材料504。可藉由摻雜主動區516之部分來形成源極及汲極區526。可將與主動區516不同地摻雜源極及汲極區526。舉例而言,主動區516可包括P經摻雜矽而源極及汲極區526包括N經摻雜矽。
如圖41中所展示,用於一閘極電介質520之一第二高k材料形成於主動區516上。用於高k閘極電介質520之材料具有大於二氧化矽之介電常數之一介電常數。用於高k閘極電介質520之一適合材料之實例包括矽酸鉿、矽酸鋯、二氧化鉿或二氧化鋯。在高k閘極電介質520上形成一場效電晶體(FET)閘極522。如在此項技術中習知,然後可使用習用光微影技術並組合適合的蝕刻製程來界定FET閘極522及下伏之高k閘極電介質520。可使用本文未詳細闡述之習用技術形成間隔件524從而側接FET閘極522之側。
藉由利用SMOI結構502來形成半導體裝置500,可與導電材料504電通信地形成浮體記憶體單元501,因而消除對浮體記憶體單元501與導電材料504之間的一額外電接觸件之需要。另外,由於可在形成浮體記憶體單元501之前在第一半導體基板506上形成一邏輯裝置(未展示)及後段工藝過程(BEOL)元件(未展示),因此浮體記憶體單元501不曝露至用以形成該邏輯裝置及該等BEOL元件之處理條件。避免曝露至此等處理條件可改良半導體裝置500之可靠性。
圖42圖解說明一半導體裝置600之另一實施例,該半導體裝置包括具有掩埋於一第二半導體基板614下面之一導電材料603之一SMOI結構601。SMOI結構601可包括(例如)一第一半導體基板605、一絕緣體材料607、一非晶矽材料609、導電材料603、一介電材料611及一第二半導體基板614。可以類同於上文相關於圖29至31所闡述之方式之一方式來形成SMOI結構601。
可如此項技術中所習知來圖案化且摻雜第二半導體基板614以形成一浮體區616、一汲極區618及一源極區609。可進一步圖案化第二半導體基板614以在汲極區618與源極區619之間於浮體區616中形成一凹部。可在該凹部中形成一字線620。可在字線620與浮體區616之間形成一介電材料622。掩埋式導電材料603充當用於記憶體單元之一掩埋式閘極。可在汲極區618之上形成一接觸件624從而導引至一位元線626。接觸件624可包含(例如)一N+經摻雜多晶矽插塞或一金屬插塞。可在源極區619之上形成一共同源極628。
圖43圖解說明包括複數個半導體裝置600(圖42)之一半導體裝置700。如圖43中所圖解說明,亦可蝕刻非晶矽材料609、導電材料603及介電材料611以形成平行於位元線626之列。類似地,在額外實施例中,可蝕刻非晶矽材料609、導電材料603及介電材料611以形成平行於位元線626之列(未展示)。
藉由利用SMOI結構601來形成半導體裝置700,可在導電材料603之頂部上形成浮體區616,因而消除對浮體區616與導電材料603之間的一額外電接觸件之需要。另外,由於可在形成浮體區616之前在第一半導體基板605上形成一邏輯裝置(未展示)及後段工藝過程(BEOL)元件(未展示),因此浮體區616不曝露至用於形成該邏輯裝置及該等BEOL元件之處理條件。避免使浮體區616曝露至此等處理條件可改良半導體裝置600之可靠性。
諸如在本文中前文所闡述之彼等半導體裝置之半導體裝置可用於本發明之電子系統之實施例中。舉例而言,圖44係根據本發明之一說明性電子系統800之一示意性方塊圖。電子系統800可包含(例如)一電腦或電腦硬體組件、一伺服器或其他聯網硬件組件、一蜂巢式電話、一數位相機、一個人數位助理(PDA)、便攜式媒體(例如,音樂)播放器等。電子系統800包括至少一個記憶體裝置801。電子系統800可進一步包括至少一個電子信號處理器裝置802(其通常稱作一「微處理器」)。電子信號處理器裝置802及至少一個記憶體裝置801中之至少一者可包含(例如)上文所闡述之半導體裝置300、400、500、600、700之一實施例。換言之,電子信號處理器裝置802及至少一個記憶體裝置801中之至少一者可包含包括具有一掩埋式導電材料之一SMOI結構之一半導體裝置之一實施例,如前文關於圖39至43中所展示之半導體裝置300、400、500、600、700。電子系統800可進一步包括一使用者用於輸入資訊至電子系統800中之一個或多個輸入裝置804,諸如,例如一滑鼠或其他指示裝置、一鍵盤、一觸控板、一按鈕或一控制面板。電子系統800可進一步包括用於輸出資訊(例如,視訊或音訊輸出)至一使用者之一個或多個輸出裝置806,諸如,例如一監測器、一顯示器、一列印機、一音訊輸出插孔、一揚聲器等。在一些實施例中,輸入裝置804及輸出裝置806可包含可用以輸入資訊至電子系統800及輸出視訊資訊至一使用者兩者之一單個觸摸螢幕裝置。一個或多個輸入裝置804及輸出裝置806可與記憶體裝置801及電子信號處理器裝置802中之至少一者電通信。
在一些實施例中,本發明包括絕緣體上半導體金屬(SMOI)結構、包括此等結構之裝置及用於形成此等結構之方法。該等SMOI結構可包括一第一半導體基板上之一絕緣體材料、接合至該絕緣體材料之一非晶矽材料、該非晶矽材料上方之一導電材料及該導電材料上方之一第二半導體基板。一介電材料亦可安置於該導電材料與該第二半導體基板之間。在其他實施例中,可圖案化該導電材料且可藉由一介電材料使經圖案化之導電材料之毗鄰部分彼此分離。
在額外實施例中,本發明包括一SMOI,該SMOI包括一第一半導體基板上之一絕緣體材料、接合至該絕緣體材料之一非晶鍺材料、該非晶鍺材料上方之一導電材料及該導電材料上方之一第二半導體基板。
在額外實施例中,本發明包括一SMOI結構,該SMOI結構包括一第一半導體基板上之一絕緣體材料、該絕緣體材料上方之一導電材料、一磊晶矽材料之至少一個部分及矽-鍺材料之至少一個部分、接合至該絕緣體材料之該磊晶矽材料之該至少一個部分或該矽-鍺材料之該至少一個部分及該導電材料上方之一第二半導體基板。該絕緣體材料可係由其上形成有一非晶矽材料之氧化物材料形成。
在額外實施例中,本發明包括一SMOI結構,該SMOI結構包括一第一半導體基板、形成於該第一半導體基板上方之氧化物材料之至少一個部分及一導電材料之至少一個部分以及形成於該導電材料上方之一第二半導體基板。
在又另外實施例中,本發明包括一半導體裝置,該半導體裝置包括一第一半導體基板上之一絕緣體材料、接合至該絕緣體材料之一非晶矽材料、該非晶矽材料上方之一導電材料、該導電材料上方之一第二半導體基板及該第二矽基板上之一記憶體單元。該導電材料可形成一互連件。一邏輯裝置亦可形成於該第一半導體基板上。在一些實施例中,一介電材料可安置於該導電材料與該第二半導體基板之間。該半導體裝置之記憶體單元可包括一浮體記憶體單元,其包括由一絕緣材料大致實體隔離之一主動區域、形成於該主動區域內之一汲極區及一源極區、在一主動區域上形成於該汲極區與該源極區之間的一高k介電材料及形成於該高k電介質上之一金屬閘極。
在又另外之實施例中,本發明包括形成一SMOI結構之方法,其包括形成包含形成於一第一半導體基板上方之一絕緣體材料之一受體晶圓,形成包含一前驅體半導體基板上方之一導電材料、該導電材料上方之一非晶矽材料及該前驅體半導體基板內之一經植入區之一施體晶圓,使該施體晶圓之該非晶矽材料接合至該受體晶圓之該絕緣體材料及移除靠近該前驅體半導體基板內之該經植入區之該前驅體半導體基板之一部分。在一些實施例中,在使該施體晶圓之該非晶矽材料接合至該絕緣體材料之前可藉助一化學、一電漿或一植入活化對非晶矽材料之至少一個表面及該絕緣體材料之一表面進行處理。
在又另外之實施例中,本發明包括製造一半導體裝置之一方法,其包括形成包含形成於一第一半導體基板上方之一絕緣體材料之一受體晶圓,形成包含一前驅體半導體基板上方之一導電材料、該導電材料上方之一非晶矽材料及該前驅體半導體基板內之一經植入區之一施體晶圓,使該施體晶圓之該非晶矽材料接合至該受體晶圓之該絕緣體材料,移除靠近該經植入區之該前驅體半導體基板之一部分以形成一第二半導體基板及在該第二半導體基板上製造至少一個記憶體單元。
在又另外之實施例中,本發明包括形成一SMOI結構之方法,其包括形成包含形成於一第一半導體基板上方之一絕緣體材料之一受體晶圓,形成包含一前驅體半導體基板上方之一導電材料、該導電材料上方之一非晶鍺材料及該前驅體半導體基板內之一經植入區之一施體晶圓,使該施體晶圓之該非晶鍺材料接合至該受體晶圓之該絕緣體材料及移除靠近該前驅體半導體基板內之該經植入區之該前驅體半導體基板之一部分。
儘管易於對本發明做出各種修改及替代形式,但已在圖式中以實例方式顯示了具體實施例且在本文中對該等具體實施例進行了詳細闡述。然而,本發明並不意欲限定於所揭示之特定形式。相反,本發明將涵蓋屬於以下隨附申請專利範圍及其法定等效物所界定之本發明之範圍內之所有修改形式、等效形式及替代方案。
10...受體晶圓
20...施體晶圓
30...絕緣體上半導體金屬(SMOI)結構
40...施體晶圓
50...絕緣體上半導體金屬(SMOI)結構
60...施體晶圓
70...絕緣體上半導體金屬(SMOI)結構
80...施體晶圓
90...絕緣體上半導體金屬(SMOI)結構
102...第一半導體基板
104...絕緣體材料
106...上部表面
110...施體晶圓
112...高k介電材料
113...金屬
115...經摻雜區
120...絕緣體上半導體金屬(SMOI)結構
130...施體晶圓
132...蓋帽材料
132'...圖案化蓋帽材料
134...結構
136...層間介電材料
140...絕緣體上半導體金屬(SMOI)結構
150...受體晶圓
152...接合材料
160...施體晶圓
170...絕緣體上半導體金屬(SMOI)結構
180...受體晶圓
190...施體晶圓
192...鍺化矽(SiGe)材料
194...磊晶(EPI)矽材料
200...絕緣體上半導體金屬(SMOI)結構
202...前驅體半導體基板
202'...第二半導體基板
204...導電材料
204'...經圖案化導電材料
206...非晶矽材料
208...裂開部分
210...經植入區
212...表面
220...受體晶圓
222...氧化物材料
224...氮化物材料
226...導電材料
230...施體晶圓
240...絕緣體上半導體金屬(SMOI)結構
250...絕緣體上半導體金屬(SMOI)結構
300...半導體裝置
301...絕緣體上半導體金屬(SMOI)結構
302...表面
304...導電材料
306...第一半導體基板
308...絕緣體材料
310...非晶矽材料
312...第二半導體基板
314...位元線
316...柱
318...汲極區
320...源極區
322...通道區
324...閘極電介質
326...閘極
400...半導體裝置
401...絕緣體上半導體金屬(SMOI)結構
402...非反應性導電材料
403...導電材料
404...反應性導電材料
406...第一半導體基板
408...介電材料
409...非晶矽材料
410...導電矽化物材料
412...第二半導體基板
414...N經摻雜矽材料
415...字線
416...P經摻雜矽材料
418...底部電極
420...記憶體媒體
422...二極體
423...柱
424...位元線
500...半導體裝置
501...浮體記憶體單元
502...絕緣體上半導體金屬(SMOI)結構
504...導電材料
506...第一半導體基板
508...絕緣體材料
510...非晶矽材料
512...高k閘極介電材料
514...第二矽基板
516...主動區
518...額外絕緣體材料
520...高k閘極電介質
522...場效電晶體(FET)閘極
524...間隔件
526...源極及汲極區
600...半導體裝置
601...絕緣體上半導體金屬(SMOI)結構
602...P+經摻雜區
603...導電材料
604...N-經摻雜區
605...第一半導體基板
606...浮體區
607...絕緣體材料
608...矽化物材料
609...非晶矽材料
610...氮化鈦金屬模式材料
611...介電材料
612...矽化鎢材料
614...第二半導體基板
616...浮體區
618...汲極區
619...源極區
620...字線
622...介電材料
624...接觸件
626...位元線
628...共同源極
700...半導體裝置
800...電子系統
801...記憶體裝置
802...電子信號處理器裝置
804...輸入裝置
806...輸出裝置
808...N-經摻雜區
圖1至圖6係根據本發明之一項實施例之各種處理動作期間之一SMOI結構之剖視圖;
圖7至圖10係根據本發明之另一實施例之各種處理動作期間之一SMOI結構之剖視圖;
圖11至圖14係根據本發明之另一實施例之各種處理動作期間之一SMOI結構之剖視圖;
圖15至圖18係根據本發明之另一實施例之各種處理動作期間之一SMOI結構之剖視圖;
圖19至圖21係根據本發明之另一實施例之各種處理動作期間之一SMOI結構之剖視圖;
圖22至圖28係根據本發明之另一實施例之各種處理動作期間之一SMOI結構之剖視圖;
圖29至圖31係根據本發明之另一實施例之各種處理動作期間之一SMOI結構之剖視圖;
圖32至圖34係根據本發明之另一實施例之各種處理動作期間之一SMOI結構之剖視圖;
圖35至圖38係根據本發明之另一實施例之各種處理動作期間之一SMOI結構之剖視圖;
圖39係包括本發明之一SMOI結構之一半導體裝置之一項實施例之一各別視圖;
圖40係包括本發明之一SMOI結構之一半導體裝置之另一實施例之一各別視圖;
圖41係包括本發明之一SMOI結構之一半導體裝置之另一實施例之一剖視圖;
圖42係包括本發明之一SMOI結構之一半導體裝置之另一實施例之一各別視圖;
圖43係包括本發明之一SMOI結構之一半導體裝置之另一實施例之一各別視圖;及
圖44係圖解說明包括包括本發明之一SMOI結構之一半導體裝置之一電子系統之一項實施例之一示意性方塊圖。
30...絕緣體上半導體金屬(SMOI)結構
102...第一半導體基板
104...絕緣體材料
202'...第二半導體基板
204...導電材料
206...非晶矽材料
302...表面
Claims (19)
- 一種絕緣體上半導體金屬結構,其包含:一絕緣體材料,其接觸一第一半導體基板之半導體材料;一導電材料,其接觸該絕緣體材料,該絕緣體材料被架高(elevated)於該第一半導體基板之該半導體材料及該導電材料之間;一非晶矽材料,其接觸該導電材料,該導電材料被架高於該絕緣體材料及該非晶矽材料之間;及一第二半導體基板之半導體材料,其接觸該非晶矽材料,該非晶矽材料被架高於該導電材料及該第二半導體基板之該半導體材料之間。
- 一種絕緣體上半導體金屬結構,其包含:一絕緣體材料,其接觸一第一半導體基板之半導體材料;一導電材料,其接觸該絕緣體材料,該絕緣體材料被架高於該第一半導體基板之該半導體材料及該導電材料之間;一磊晶矽材料之至少一個部分及矽-鍺材料之至少一個部分,該磊晶矽材料之該至少一個部分或該矽-鍺材料之該至少一個部分接觸該導電材料,該導電材料被架高於該絕緣體材料及接觸該導電材料之該磊晶矽材料之該至少一個部分或該矽-鍺材料之該至少一個部分之間;及一第二半導體基板之半導體材料,其接觸與該導電材 料接觸之該磊晶矽材料之該至少一個部分或該矽-鍺材料之該至少一個部分,接觸該導電材料之該磊晶矽材料之該至少一個部分或該矽-鍺材料之該至少一個部分被架高於該導電材料及該第二半導體基板之該半導體材料之間。
- 一種用於製造一絕緣體上半導體金屬結構之方法,其包含:形成包含形成於一第一半導體基板上方之一絕緣體材料之一受體晶圓;形成包含一前驅體半導體基板上方之一導電材料、該導電材料上方之一非晶矽材料及該前驅體半導體基板內之一經植入區之一施體晶圓;使將該施體晶圓之該非晶矽材料接合至該受體晶圓之該絕緣體材料;及移除靠近該前驅體半導體基板內之該經植入區之該前驅體半導體基板之一部分。
- 如請求項3之方法,其進一步包含在將該施體晶圓之該非晶矽材料接合至該受體晶圓之該絕緣體材料之前藉助一化學、一電漿或一植入活化來處理該非晶矽材料之一表面及該絕緣體材料之一表面中之至少一者。
- 如請求項3之方法,其中形成包含形成於一第一半導體基板上方之一絕緣體材料之一受體晶圓包含在包含結晶矽之一第一半導體基板上方形成氧化物材料。
- 如請求項3之方法,其中形成包含一前驅體半導體基板 上方之一導電材料、該導電材料上方之一非晶矽材料及該前驅體半導體基板內之一經植入區之一施體晶圓包含在一結晶矽基板上方形成一導電材料、在該導電材料上方形成一非晶矽材料及在該結晶矽基板內形成氫經植入區。
- 如請求項3之方法,其中形成一施體晶圓進一步包含在該導電材料與該前驅體半導體基板之間形成一介電材料。
- 如請求項3之方法,其中形成包含一前驅體半導體基板上方之一導電材料之一施體晶圓包含在該前驅體半導體基板上方形成一非反應性導電材料且在該非反應性導電材料上方形成一反應性導電材料及使該反應性導電材料與該施體晶圓之該非晶矽材料發生反應以形成一導電矽化物材料。
- 如請求項3之方法,其中在該前驅體半導體基板上方形成該導電材料包含:在該前驅體半導體基板上方沈積該導電材料;在該導電材料上方形成一蓋帽材料;圖案化該蓋帽材料及該導電材料;及在該經圖案化蓋帽材料與經圖案化導電材料之毗鄰部分之間形成一介電材料。
- 如請求項3之方法,其中形成該施體晶圓進一步包含在該導電材料與該非晶矽材料之間形成一磊晶矽材料之至少一個部分及矽-鍺材料之至少一個部分。
- 如請求項3之方法,其中形成該施體晶圓進一步包含在該導電材料與該非晶矽材料之間形成氧化物材料之至少一個部分及氮化物材料之至少一個部分。
- 一種製造一半導體裝置之方法,其包含:形成包含形成於一第一半導體基板上方之一絕緣體材料之一受體晶圓;形成包含一前驅體半導體基板上方之一導電材料、該導電材料上方之一非晶矽材料及該前驅體半導體基板內之一經植入區之一施體晶圓;將該施體晶圓之該非晶矽材料接合至該受體晶圓之該絕緣體材料;移除靠近該經植入區之該前驅體半導體基板之一部分以形成一第二半導體基板;及在該第二半導體基板上製造至少一個記憶體單元。
- 如請求項12之方法,其進一步包含圖案化該導電材料以形成一掩埋式字線及一掩埋式位元線中之至少一者。
- 如請求項12之方法,其中在該第二半導體基板上製造至少一個記憶體單元包含:由在若干個側及底部上由一額外絕緣體材料大致環繞之該第二半導體基板之一部分形成一主動區域;在該主動區域上形成一高k閘極電介質及一金屬閘極;及在該主動區域中形成一源極區及一汲極區。
- 如請求項12之方法,其中在該第二半導體基板上製造至 少一個記憶體單元包含:蝕刻該第二半導體基板以形成至少一個柱;在該至少一個柱中形成一源極區、一主動區域及一汲極區;及在該主動區域上形成一閘極電介質及一閘極。
- 如請求項12之方法,其中在該第二半導體基板上製造至少一個記憶體單元包含:在該第二半導體基板中形成二極體;及在該二極體上形成一底部電極、一記憶體媒體及一頂部電極。
- 一種用於製造一絕緣體上半導體金屬結構之方法,其包含:形成包含形成於一第一半導體基板上方之一絕緣體材料之一受體晶圓;形成包含一前驅體半導體基板上方之一導電材料、該導電材料上方之一非晶鍺材料及該前驅體半導體基板內之一經植入區之一施體晶圓;將該施體晶圓之該非晶鍺材料接合至該受體晶圓之該絕緣體材料;及移除靠近該前驅體半導體基板內之該經植入區之該前驅體半導體基板之一部分。
- 一種半導體裝置,其包含:一絕緣體材料,其向第一半導體材料外被架高且接觸該第一半導體材料; 一非晶矽材料,其向該絕緣體材料外被架高且接觸該絕緣體材料;一導電材料,其向該非晶矽材料外被架高且接觸該非晶矽材料;第二半導體材料,其向該導電材料外被架高;及一浮體記憶體單元,其包含:一主動區,其包含在該主動區之相對側之該第二半導體材料及絕緣材料;一汲極區及一源極區,其位於該主動區之該第二半導體材料內;一第一高k介電材料,其在該汲極區及該源極區之間向該主動區之該第二半導體材料外被架高且接觸該主動區之該第二半導體材料;一電晶體閘極,其向該第一高k介電材料外被架高且接觸該第一高k介電材料;及一第二高k介電材料,其被架高於該導電材料及該第二半導體材料之間且接觸該導電材料及該第二半導體材料,該第二高k介電材料接觸該汲極區及該源極區之底部表面及該汲極區及該源極區之間的該第二半導體材料之底部表面。
- 一種絕緣體上半導體金屬結構,其包含:一第一晶圓,其包含接觸半導體材料之一絕緣體材料;一第二晶圓,其包含一非晶矽材料及半導體材料,該 第二晶圓包含被架高於該第二晶圓之該非晶矽材料及該半導體材料之間且接觸該第二晶圓之該非晶矽材料及該半導體材料的導電材料;且該第一晶圓及該第二晶圓與互相接觸之該第二晶圓之該非晶矽材料及該第一晶圓之該絕緣體材料互相黏附,該非晶矽材料被架高於該導電材料及該絕緣體材料之間,該絕緣體材料被架高於該第一晶圓之該半導體材料與該非晶矽材料之間。
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EP2543069A2 (en) | 2013-01-09 |
US20170194351A1 (en) | 2017-07-06 |
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CN102782850B (zh) | 2015-07-15 |
TW201145487A (en) | 2011-12-16 |
US10325926B2 (en) | 2019-06-18 |
EP2543069A4 (en) | 2015-04-08 |
JP5671070B2 (ja) | 2015-02-18 |
JP2013521648A (ja) | 2013-06-10 |
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US9608119B2 (en) | 2017-03-28 |
US20110215407A1 (en) | 2011-09-08 |
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