TWI278020B - Method for integrated circuit fabrication using pitch multiplication - Google Patents

Method for integrated circuit fabrication using pitch multiplication Download PDF

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TWI278020B
TWI278020B TW094130195A TW94130195A TWI278020B TW I278020 B TWI278020 B TW I278020B TW 094130195 A TW094130195 A TW 094130195A TW 94130195 A TW94130195 A TW 94130195A TW I278020 B TWI278020 B TW I278020B
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layer
pattern
forming
photoresist
integrated circuit
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TW094130195A
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TW200620408A (en
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Mirzafer K Abatchev
Gurtej Sandhu
Luan Tran
William T Rericha
Mark D Durcan
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Micron Technology Inc
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    • H—ELECTRICITY
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    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
    • H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
    • H01J37/3174—Particle-beam lithography, e.g. electron beam lithography
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    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/95—Multilayer mask including nonradiation sensitive layer

Description

1278020 九、發明說明： 【發明所屬之技術領域】 術 本發明一般相關於積體電路製造，尤其相關於光罩技 【先前技術】 許多因素，包括現代電子設備中對可攜性、計算能力、 ^隐谷$及能量效率的需求增加，造成積體電路的尺寸相 績減小。為促進此尺寸減小，組成特徵，如形成積體電蹲 的電氣裝置及互連線寬度，亦持續地減低。
例如在記憶體電路中，或如動態隨機存取記憶體 (dram)、靜態隨機存取記憶體（SR 趙等裝置+，降低特徵尺寸的趨勢是明顯的。料丨而)= 纟㈣㈣以彳，習知為記 :、：早70。在其最普通形式中，-記憶體單元通常由二電 矹衣置、、且成·一儲存電容器及一存取場效電晶 :單元係：可定址位置，其可儲存-位元(二進位數字： ml立70可通過該電晶體而寫至一單元，及藉由自參考 电極側感應該儲存電極上的帝 ……的’何而讀取。藉由降低組成的 二?：置及存取該等裝置的導線的尺寸，可降低用以合併 此寻特徵的記憬體梦番 r單元壯：、、、。此外’可藉由將更多記憶 亥4記憶體裝置中而增加儲存容量。 的Π尺:Γ持續減低對用以形成該等特徵的技術有更大 =門例如’通常使用微影將導線等特徵在-基板上定 圖案。間距的觀念可用以說明此等特徵的尺寸。間距定義 104585.doc 1278020 為一鄰接特徵中的-完全相同點間的距離。此等特徵通常 :::特徵間的間隔加以界定，該等間隔通常由絕緣體等 材料來填補。結果，間距可視為-特徵的寬度及用以分開 該特徵與一鄰接特徵的間隔寬度的總和 '然而，由二 及光或輕射波長等因素，微影技術各具有一最小間距，低 於孩間距，一特定微影技術無法可靠地形成特徵。因此， -微影技術的最小間距可限制特徵尺寸的減小。 門距加七係為使微影技術的性能延伸以超出其最小間 距而提出的-方法。此-方法在圖1A至1F中說明，且揭示 在頒予Lowfey等人的美國專利號5,328,81()中。參照至圖 1A，首先使用微影在用以覆蓋一耗材層2〇及一基板3、〇的二 ‘光阻層中形成數條線1〇構成的一圖案。如圖ΐβ所示，接著 猎由一蝕刻步驟（較佳為各向異性）將該圖案轉移到層Μ， 用以形成數個位置支架或心軸4〇。如圖lc所示，可剝除該 等光阻線1〇，且各向同性地餘刻該等心軸40,以增加鄰接 Φ 。軸4〇間的距離。如圖1D所示，一材料層50後續地在該等 心軸40之上沈積。如圖1E所示，接著藉由在一方向性間隔 層蝕刻中自該等水平表面70及80優先地蝕刻該間隔層^ 料，而在該等心軸4〇的數個侧邊上形成數個間隔層，即 延伸自數個另一材料側邊而延伸或原始形成的材料。如圖 1 F所示，接著移除其餘的心軸40，僅留下該等間隔層60， ”之作為疋圖案用的一光罩。因此，一已知間距先前包 括用以界定一特徵及一間隔的一圖案之處，今相同的寬度 包括由該等間隔層60界定的二特徵及二間隔。結果，有效 I04585.doc 1278020 降低-微影技術能達成的最小特徵尺寸。 應了解，雖然在上述範例中該間 間距減低傳統上稱為門跖处 、不、疋減丰，但此 大,,#得為間距力口倍"，或更普遍稱為間距”增 ⑤即，傳統上間距，，增大”某倍數 距減低該倍數。本文中保留傳統的術語。、間 因為間隔層材料層5〇通常具有—單—厚度㈣參看⑸D 及叫，及因為間隔層6〇形成的數個特 到該厚度9〇,因此間距加倍通常僅產生卜办^吊對應 徵。然而，電路常利用不同尺寸的特徵：：度的數個特 記憶體電路通常包含數個機存取 口己U體單7〇陣列及所謂”周邊，，中 的數個邏輯電路。在兮望涵& I路纟4陣列中’該等記憶體單元通常由 接，及在㈣邊中’該科線通常接觸相連接陣 列至！輯的數個緩衝塾。然而，如緩衝塾等周邊特徵可大 於5亥寻導線。此外’如電晶體等周邊電子裝置可大於該陣 J中的电子U。此外，即若周邊特徵可以該陣列相同的 =距形成’使用-單—光罩通常將不可能做到界定電路所 而的撓性’尤其若該等圖案侷限為可沿著圖案化光阻劑的 數個側壁形成的圖案。 為在周邊及在陣列形成圖案所建議的一些方法涉及，將 一圖案分開地|虫刻到一基板的陣列區域中及到該基板的周 邊中。因此，首先形成該陣列中的—圖案且使用—光罩將 該圖案轉移到該基板，及接著形成該周邊中的另一圖案且 使用另-光罩將該另-圖案分開地轉移至該基板。因為此 射法使用不同光罩在_基板上的不同位置形成數個圖 ^4585^00 1278020 η其能力！限’無法形成需要重疊圖案的特徵，諸 、田緩衝1*重豐-互連線時，且又必須用到—第三 以互連來”縫接”二個分開的圖案。此外，此一第三 於間距增大技術界定的精細特徵，相對於光罩對；二 甚至更大的挑戰。 早“將面臨 =此，需要形成不同尺寸特徵的方法，尤其在該等特徵 而要不同重疊圖案且特別配合間距增大之處。 ， 【發明内容】 根據本發明的一槪冬，姐- ^ _ 心揭不一種用於半導體製程的方 的該方法包括提供-基板，其具有用以覆蓋在該基板上 的主光罩層，用以覆芸在兮主杏署思L 用LV卜 在°亥主先罩層上的-暫時層，及. 用以後盍在該暫時層上的一第一光 中开…丄 π ¥ 1阻層。在該第-光阻層 4-先阻圖案。在該暫時層中形成—第一圖案，盆且 有數個特徵，其衍生自該光阻圖案的數個特徵。在該第2 圖案的位準上方後續地形成一第二光阻層，及在該 =中形成另一光阻圖案。轉移該另一光阻圖案及該第— ::到該，光罩層’用以在該主光罩層中形成一混合圖 茶 通過该主光罩層中的混人ΒΙ安，、，占 U案以處理該基板。應了 L該基板可包括將通過該主光罩層處理的任一或任何材 根據本發明的另一概念，揭示_種形成積體電路的方 t。該方法包括提供—基板，及在該基板之上形成-非晶 奴層。在該第一非晶碳層之上形成—第—硬式光罩層。在 ㈣-硬式光罩層之上形成一暫時層’及在該暫時層之上 104585.doc 1278020 形成一第二硬式光罩層。 根據本發明的另一概念，揭示一種用於半導體製造的方 法。該方法包括，藉由間距增大而形成一第一圖案，及藉 由無間距增大的微影而分開地形成一第二圖案。轉移該等 第一及第二圖案到一光罩層，及通過該光罩層蝕刻一基 板。 根據本發明再一概念’揭示一種形成積體電路的方法。
該方法包括形成一光罩圖案，其中該光罩圖案的一第一部 分具有一第一間距，及該光罩圖案的一第二部分具有一第 二間距。該第一間距低於界定該第二圖案所用微影技術的 一最小間距。該方法亦包括通過該光罩圖案以蝕刻一基 板0 很像本發明的另一概念，揭示一種形成記憶體裝置的： 法。該方法包括在-第-碳層上方的-層中形成數個暫t 位置支架構成的一圖案。一層光罩材料在該等暫時位置 架的表面之上沈積，及接著自該記憶體裝置的數個水平| 面&擇性地移除該層光罩材料。相對於該光罩材料而選_ 性地移除該等暫時位置支架，以形成—光罩材料圖案，、： 對應到該記憶體裝置的一陣列區域中的數個特徵。’ 、根據本發明的再一概念’揭示—種製造積體電路的- :::該方法包括形成複數個心軸條。在各心轴條的數個; …成-間隔層。移除該等心轴條以形成數 間隔層構成的—圖案。在該等間隔層上方的 y 一光罩層，及在該光罩層中形成— 形』 ^ 轉移该圖案到: 104585.doc 1278020 該等間隔層相同的平面。 根據本發明的另—概念， 法。該方法包括在一基板 ;造積體電路的方 隔線，其中該光罩材料不门 光罩材料的複數個分 T /亢卓材枓不同於光阻 在該基板上方的—光可 影技術， 等分隔線下方的一非曰二：科中界定複數個特徵。在該 特徵。 非一”複製該等分隔線及該複數個 根據本發明的另一概念，揭示一 積體電路的方法。該方法包括提罩圖案以製造 條線。由—第—暫4罩材料的複數 -暫時材料。"二暫時二 ==一刻該第 擇性地蝕刻該第二暫時材 間的間隔。選 過該等間隔的選擇性㈣，而間隔。接著藉由通 、伴！·玍蝕亥J，而在該複數條 罩材料層中形成一圖案。 ”方的另-先 根據本發明的另-概念，揭示-種製造積體電路的方 的一第一及、 罩層，其在-部分製造積體電路 的弟及—乐二區域之上延伸。在+ 案。該圖案中的一部分的一最小特f二罩層中形成-圖 W j繁一 j特斂尺寸，該部分係對應 到该弟^域，約等於或小於該圖宰中另^ v Θ汁&少 Λ 口木中另一部分的一最小 特试尺寸的―丰’該另-部分係對應到該第二區域。 根據本發明的另—概念，揭示一 次 路。該部分形成積體電路包括 //成的積體電 該碳層的一位準上。該等間隔層具有約 1 00 nm或更小的一間距。 104585.doc •12- Ϊ278020 本^月的再一概念’揭示一種部分形成的積體電 #忒邛刀形成積體電路包括一基板，及一主光罩層，其 设意在基板上。該主光罩層由不同於光阻劑的一材料形 成。用以界定 弟一圖案的一光罩材料位於覆蓋該主光罩 白勺^^繁 、, 平面中。用以界定一第二圖案的一光可限定材 料位於覆盍該光罩材料的一第二平面中。 【實施方式】 〜、了形成不同尺寸特徵的問題之外，已發現間距加倍技 付在轉私間圖案到一基板時會有困難。尤其地，在轉移 圖案的-般方法中，間隔層及下基板兩者皆曝露 ::::先_卓基板材料。然而，應了解，儘管是以 餘刻劑亦會崎間隔層。因此，在轉移一圖 :的期間’間隔層可在完成圖案轉移前便由钱刻 3。此等困難因降低特徵尺寸的趨勢而加深，例如降低特 :尺寸在此等渠溝的寬度降低時越來越導致較高的縱橫 t 。加上製造不同特徵尺寸結構遭遇的困難，此轉 移限制使間距加倍原則庫用 、·案轉 有鑑於此等困難’本發明的 ：困難 :私改善，及用於配合間距加倍以形成不同 = 该方法的一第一階段中，較佳 、铽。在 使用i放影及間距加ρ -:ι隔層圖案。此通常在該晶片的—區域中，例二= 體曰曰片的陣列中’形成同—尺寸的數個特徵。在一乂己： 段中，再執行微影，而在覆# 弟一階 隹设盍该間隔層圖案的— 該晶片的另一區域中’例如 θ中’在 體日日片的周邊中，形成 104585.doc 1278020 第一圖案。接I轉移該間隔層丨該第二圖案兩者到一下 主光罩層，其較佳可相對於一下基板優先地加以蝕刻。接 著在-單-步驟中，將該間隔層及第二圖案自該主光罩層 轉移到該下基板。因此，可形成用以形成不同尺寸特㈣ 數個圖案，该等特徵中有些低於定圖案所用微影技術的最 丨間距&此等圖案可成功地轉移到該下基板。 此外’因為該第二圖案原初在覆蓋該間隔層圖案的一層 上形成，因此該第二圖案可重疊該間隔層圖案。結果，可 有利地形成不同尺寸的番晶^ 電晶體等。 的重里特破，如導線及緩衝塾或周邊 較佳地，該主光罩層係直接覆蓋在上方的光罩層，且由 w③主要心通過該主光罩層在該基板一 例如餘刻)。尤其地’該主光罩層較佳由相對於間隔 層材料及基板材料兩者容許良好_選擇性的= 成，令間隔層圖案可有效地轉移到該材料上；令星 層在處理後可選擇性地移除，而不損害到基板；及使= 光罩以蝕刻該基板時，令該光罩 該基板。由^ 圖案可有效地轉移到 由於層㈣於各式各樣㈣，包 :、氮化㈣，具有絕佳敍刻選擇性， 較佳由碳形成，更佳是非晶碳。 先罩層 應了解，-基板可包括將通過該主光罩層處理的任 任何材料。因此，一基板可包括一單^ 或 _層，及層中具數個不心 或數層等。此等材料可包括半導體、絕緣體λ;體= I04585.doc 1278020 部:基板包括將製造的積體電路的數個結構或 亦應了解，將一圖宰白 及在該第二位準中形成位::r-第二位準涉 準上的數個特徵。例如，在第吊對應到邊弟-位 將遵循第-位準上數個線:::位:;數:^:徑通常 的位置將對應到第一位 +八他特欲 -位準到第二位準，特:::τ的… 如，錢刻化學及停件而精4形狀及尺寸可不同。例 .ρ '、牛疋，形成該轉移圖案的該等特徵 :尺寸及該等特徵間的相對間隔可相對於第一位準上的圖 案而增大或減小’但仍很像相同的初始"圖案"。 八：下將參照至附圖’其中從頭到尾相同數字表示相同部 刀應了解，圖2至16不必然按比例繪製。 雖然該等較佳實施例可在不同尺寸特徵在一基板上形成 的任何情況中發現靡用 兄應用在特別有利的數個實施例中，將 轉移到-基板的圖案的一部分藉由間距增大而形成，且該 =刀圖木具有-間距’其低於處理該基板所賴影技術的 最J間距。此外，雖然該等較佳實施例可用以形成任何積 體電路’但其特別有利地適於形成具電子裝置陣列的裝 置’'亥等陣列包括邏輯或閘極陣列及DRAM、ROM或快閃 $己憶體等揮發性及非揮發性記憶體裝置。在此類裳置中， 例如間距增大可用以在該等晶片的陣列區域中形成電晶體 閘，及導線，而傳統微影可用以在該等晶片的周邊形成接 點等較大特徵。附圖中說明製造一記憶體晶片期間的數個 I04585.doc 1278020 示範光罩步驟。 圖2 A以上視圖說明一部分製造的積體電路，或記憶體晶 片100。一中央區域1〇2(”陣列”）由一周邊區域1〇4(，，周邊，，〕 環繞。應了解，完成積體電路100的製造後，陣列1〇2通常 將稠密地佈滿導線及電晶體與電容器等電氣裝置。期望的 是，可使用間距增大在陣列102中形成數個特徵，將詳述 如下。另一方面，周邊1〇4可具有數個特徵，其大於陣列 1〇2中者。通常使用傳統微影，而非間距增大，以定出此 等特徵的w案，原因是位於周邊丨咐的邏輯電路的幾何 複雜度難以使用間距增大。此外，周邊中的一些裝置由於
電氣限制而需要較大的幾何圖案，因此用於此類裝置n 距增大比傳統微影不利。 參如至圖2B，提供_部分形成的積體電路⑽。在各種 層120至16G下方設置—基板m。將使基板U0定圖案以形 成各種特徵’及隸刻該等層12()至⑽以形成—光罩以用 於5亥圖案，將詳述如下。較佳根據本文中論及的各種圖案 形成及圖案轉移步驟的化學及製程條件要求的考量，而選 雜覆蓋基板m的數層的材料。因一最上層可選擇性 限定層120(其較佳可ώ w呈/ 从衫方法限定）與基板110間的數 層用以轉移衍生自哕可 T生自柯4擇性限定層120的-圖案到基板 @，’八因Λ較佳選擇可選擇性限定層120與基板110間的數 :7 °亥寻層在其钱刻期間可相對於其他曝露材料而選擇 '應了解’當—材料的㈣速率比周圍材料者至 …5倍’較佳約大10倍，更佳約大2〇倍，及最佳至少 104585.doc 1278020 、、勺大40仏時，即認為是選擇性地或優先地餘刻該材料。 在所示實施例中，可選擇性限定層12〇覆蓋在一第一硬 式光罩（或蝕刻停止）層13〇上，該蝕刻停止層覆蓋在一暫時 層140上，該暫時層覆蓋在一第二硬式光罩（或蝕刻停止）層 150上’该第二硬式光罩層覆蓋在一主光罩層160上，該主 光罩層覆盍在將通過一光罩處理（例如蝕刻）的基板11 〇上。 較佳依本文中所述蝕刻化學及製程條件的相容性而定，選 擇該等層的厚度。例如，當藉由選擇性地蝕刻該下層而將 一圖案從一上層轉移到一下層時，來自該兩層的材料皆移 除到某些程度。因此，該上層較佳夠厚，令其在蝕刻期間 不致蝕刻掉。 在所示實施例中，第一硬式光罩層13〇的厚度較佳在約 10至50 nm之間，更佳在約1〇至30 nm之間。暫時層14〇的 厚度較佳在約100至300 nm之間，更佳在約1〇〇至2〇〇 ^^之 間。第二硬式光罩層150的厚度較佳在約1〇至5〇 nm之間， 更佳在約20至40 nm之間，及主光罩層16〇的厚度較佳在約 100至lOOOnm之間，更佳在約1〇〇至5〇()11111之間。 參妝至圖2，可選擇性限定層120較佳由一光阻劑形成， 包括此蟄中習用的任何光阻劑。例如，該光阻劑可為與下 列系統相容的任何光阻劑·· 13.7 nm、157 nm、193 nm、 248 nm或3 65 nm波長系統、193 nm波長浸潤式系統，或電 子束微影系統。較佳光阻材料的範例包括，氟化氬（ArF) 感光阻劑，即適合與一 ArF光源配合使用的光阻劑，及氟 化氪（KrF)感光阻劑，即適合與一 KrF光源配合使用的光阻 104585.doc 17 1278020 劑。ArF光阻劑較佳與利用較短波長光（例如193則的微 影糸統配合使用。KrF光阻劑較佳與248⑽系統等較長波 長微影系統配合使用。在其他實施例中，層12G及任何後 縯抗敍層可由―抗！虫劑形成’該抗钱劑可藉由奈米轉印微 影以定圖f ’例如藉由使用一模型或機械作用力而 蝕劑定圖案。
第一硬式光罩層130的材料較佳包括氧化矽(Si〇2)、矽， 或一介電質抗反射塗層（DARC)，如—飽切的氮氧化 矽口 DARC可藉由使光反射減到最小而增強解析度，因 此其可特別有利於形成圖案，其具有接近微影技術的解析 度極限的間距。應了解，光反射可降低微影可用以界定一 圖案邊緣的精確度。㉟了第一硬式光罩層130之外，可視 需要同樣地使用-底部抗反射塗層（B A R c)(未顯示）以控制 光反射。 暫時層140較佳由非晶碳形成，其相對於該等較佳硬式 光罩材料而提供極高的蝕刻選擇性。更佳地，該非晶碳係 问度透光的一透明碳形式，及其藉由可穿透用於此類對齊 的光波長而對光學對齊提供進一步改善。用以形成一高度 透月石反的沈積技術可參看Α· Helmb〇ld、D· 的著 作，薄固態膜283(1996)，第196至203頁。 如同第一硬式光罩層130，第二硬式光罩層150較佳包括 一介電質抗反射塗層（DARC)(例如氮氧化矽）、氧化矽 (Sl〇2)或石夕。此外，可視需要使用一底部抗反射塗層 (BARC)(未顯示）以控制光反射。雖然該等第一及第二硬式 104585.doc -18· 1278020 光罩層130及150可由不同姑祖 '斗幵^成，但此等層較佳由相同 才料形成，以易於處理且使利用的不同蝕刻化學減至最 少：：詳述如下。與暫時層14〇 一樣，主光罩層灣佳由 非晶妷形成，更佳是透明碳。 應了解’本文中論及的各種層可由熟諳此藝者習用的各 ^方法形成。例如’可制化學汽相沈積等各種汽相沈積 方法以形成該等硬式来置爲 ^ . 罩3。較仏地，一低溫化學汽相沈 積方法用以在光|e L i 罩層160之上沈積該等硬式光罩層或其他 任何材料，例如間隔層★ 層材枓（圖7)，其中光罩層16〇由非晶 石夕形成。此類低溫沈積方法有利地防止該非晶碳層的化學 或物理性破裂。 可使用旋塗方法以形成該等光可限定層。此外，可藉由 使用氫碳化合物或此類化合物的混合物作為碳先質的化學 汽相沈積以形成數個非晶碳層。示範先質包括丙稀: 丁二稀及乙块。形成非晶碳層的 合適方法揭示在2003年6月3日頒予娜如等人的美國 專利號6,573,030 B1中。 '在根據該等較佳實施例及參照至圖3至9的方法的第一階 1又中，執行部分形成積體電路1〇〇的陣列中的間距增大。 在光可限定層120上形成一圖案，如圖3所示。例如可藉由 微：將光可限定層120定圖案…通過一±光罩將層： 曝路至輻射’及接著加以顯影。顯影後，彡留的光可限定 材料，即此例中的光阻劑，包括數條24， 間隔丨22。 ，、界疋數個 104585.doc -19· 1278020 如圖4所示，該等間隔ι22及光阻線124的寬度可改變成 一期望尺寸。例如，可藉由蝕刻該等光阻線124而使該等 間隔122加寬。較佳使用一各向同性蝕刻以蝕刻該等光阻 線124，如氧化硫電漿等，例如包括s〇2、〇2、乂及斛的一 電漿。較佳選擇該蝕刻的程度，令一最終形成的線具
有一寬度’其對應到將形成的該等間隔層的期望間隔，如 以下參照至圖8至16的討論所了解。有利地，&了形成該 等線124a之外，該等線比用以定出光可限定層12〇圖案的 微影技術所界定的特徵窄’此姓刻尚可使該等線124的邊 緣平順’目此提高該等線124的一致性。最終形成的光阻 線124及124a因此構成該等位置支架或心軸，其上將形成 數個間隔層175構成的一圖案(圖9)。在其他實施例中，可 藉由膨服該等線12 4到—期望尺寸而使該等間隔12 2間的間 隔變窄。例如’可在該等線124之上沈積額外材料，或使 該等線124起化學反應以形成具較大體積的—材料以增加 其尺寸。 較佳轉移（改良）光可限定層120的圖案到一材料層14〇， 其可耐得住間隔層材料沈積的製程條件，將詳述如下。除 了具有比光阻劑高的抗熱性夕卜，較佳選擇形成暫時層140 的材料？其可相對於該間隔層材料及下層而選擇性地移 除。如上述114〇較佳由非晶碳形成。因為用以蝕刻光 阻劑的較佳化學通常亦_當數量的非晶 學能夠相對於各式各揭从上丨 局 '各樣材料而以絕佳選擇性蝕刻非晶碳，
因此較佳選自此類姑M 、材枓的一硬式光罩層130分開該等層12〇 104585.doc -20- 1278020 人140。適合用於硬式光罩層n〇的材料例如包括daRc、 氣化石夕或氮化石夕，及石夕。 較佳轉移光可限定層120中的圖案到硬式光罩層13〇，如 圖5所示。雖然若硬式光罩層13〇是薄的，一濕蝕（各向同 ^生蝕刻）亦適合，但較佳使用如一使用氟碳電漿的蝕刻等 各向異性蝕刻以達成此轉移。較佳的氟碳電漿蝕刻化學可 包括 cf4、cfh3、CF2H2、CF3H等。 接著轉移該圖案到暫時層14〇，如圖6所示，較佳使用一 含s〇2電漿，例如—含8〇2、〇2及沿的電浆。有利地，該含 s〇2電漿可比蝕刻硬式光罩層13〇大2〇倍的速率，更佳是大 40倍的速率，蝕刻較佳暫時層140的碳。一合適含s〇2電漿 揭不在Abatchev等人的美國專利申請號1〇/931，772中，申 =日2004年8月31日，名稱為臨界尺寸控制。應了解，該 含s〇2電漿同時蝕刻暫時層14〇及移除光可限定層丨2〇。 如圖7所示，接下來較佳在硬式光罩層130及暫時層14〇 =上沈積—層間隔層材料17〇。較佳藉由化學汽相沈積或 私子層&積以沈積該間隔層材料。該間隔層材料可為能作 為光罩使用以轉移一圖案到下主光罩層16〇的任何材 料。該間隔層材料較佳：D可以良好階梯涵蓋範圍沈積； 2)可以暫日寸層14G相容的—低溫沈積；3)可相對於暫時層 刚及暫時層14GT方的任何層而選擇性餘刻。較佳材料包 括氮化矽及氧化石夕。 如圖8所不，接著間隔層170受到-各向異性蝕刻，用以 將間隔層材料自部分形成的積體電路1〇〇的數個水平表面 104585.doc 21 1278020 180移除。可使用氟碳電漿以執行此一蝕刻，其亦習知為 間隔層蝕刻，該氟碳電漿亦可有利地蝕刻硬式光罩層 130。接下來，例如可使用一含s〇2的電漿選擇性地移除非 晶碳層140。圖9顯示該非晶碳蝕刻後所留下數個間隔層 175構成的一圖案。因此，已達成部分形成積體電路1〇〇的 陣列中的間距增大，及在所示實施例中，該等間隔層的間 距為微影原初所形成光阻線124(圖3)的一半間距。應了
解，該等間隔層175通常遵循光可限定層120中原初形成的 圖案或線124的輪廓。 接下來，在根據該等較佳實施例的方法的一第二階段 中，在周邊104形成一第二圖案。為形成此第二圖案，如 圖10所不，該等間隔層175受到保護及形成另一光可限定 層220，以谷許第二圖案在周邊1〇4定圖案。藉由在該等間 隔層175之上形成一保護層2〇〇而保護該等間隔層。該 保護層200較佳至少與該等間隔層175—樣高，且厚度較佳 約100至500 nm，更佳約1〇〇至3〇〇 nm。接下來較佳在保^ 層200之上形成一硬式光罩層21〇，以協助將一圖案自光可 限定層220轉移到保護層2〇〇。較佳地，硬式光罩層21〇的 厚度約40至80nm，更佳約5〇至6〇11111。 、較佳由可相對於間隔層175而輕易選擇性移除的材料形 成保護層200。例如，保護層2〇〇可由一光阻劑形成，且可 與形成光可限定層12〇(圖2至5)所用者相同或不同的光阻 劑’光可限定層120可與形成*可限定層220(圖10)所用者 相同或不同的材料。更佳地，保護層2〇〇由非晶碳形成， 104585.doc -22- 1278020 非曰曰奴可相對於間隔層1 75以絕佳選擇性加以敍刻 在其他實施例中 及光可限定層220兩 略硬式光罩層21〇。 ’其中保護層200由可相對於間隔層175 者而選擇性钱刻的一材料形成，可省 例如’保護層2 0 0可由一底部抗反射塗 層（ ）开/成且直接在該B ARC上方形成一光阻劑。間 ^ 可由此對该BARC有良好蝕刻選擇性的一材料形 成’包括氮化矽或氧化石夕。
雖然可使用任何微影技術定圖案，但較佳使用與光可限 定層120定圖案所用相同的微影技術將光可限定層220定圖 案因此參知至圖i i，在光可限定層22〇中形成一圖案 230。雖然圖案177較佳具有一間距或解析度，其小於該微 影技術的最小間距或解析度，但圖案23〇較佳具有一間距 或解析度’其等於或大於該微影技術的最小間距或解析 度。應了解，在周邊1〇4的圖案23〇可用以形成數個緩衝 墊包日日體、區域互連等。亦應了解，雖然圖中繪成與圖 案177橫向地分開，但圖案⑽亦可重疊圖案177。因此， 此等圖案使用不同參考數字〇77及23〇)表示其原初在不同 步驟中形成。 接著轉移圖案230到數個間隔層175構成的圖案177相同 的位準。&圖12所示，相對於光可限定層22q而選擇性地 钱刻硬式光罩層210，較佳使用i碳電_刻等各向異性 蝕刻。或者，一濕蝕（各向同性蝕刻）亦可適用於適當薄的 硬式光罩層210。接著藉由如含s〇2電漿的蝕刻等另一各向 異性蝕刻將圖案230轉移到保護層2〇〇,如圖13所示。: 為 104585.doc -23 - 1278020 先則已移除覆蓋在間隔層175上的硬式光罩層21〇，因此此 蝕刻亦移除間隔層1 75周圍的保護層2〇〇，因此留下該等曝 露的間隔層175。 參妝至圖14及1 5，接著將圖案1 77及23 0向下轉移到主光 罩層1 60，其較佳包括對基板丨丨〇具良好蝕刻選擇性的一材 料，且反之亦然，以容許圖案177及23〇同時轉移到基板 110。因此，圖案丨77及230在主光軍層16〇中形成一混合圖 案。 為轉移到圖案177及230，首先蝕刻覆蓋在主光罩層16〇 上的硬式光罩層150(圖14)。較佳各向異性地蝕刻硬式光罩 層150，較佳使用氟碳電漿。或者，若硬式光罩層15〇較 薄’則可使用一各向同性钱刻。 接著各向異性地蝕刻主光罩層160，較佳使用一含s〇2電 漿，其可同時移除光可限定層200(圖15)。如上述，含s〇2 電漿相對於硬式光罩層150對主光罩層16〇的非晶碳具有絕 佳選擇性。因此，可在主光罩層160中形成一夠厚光罩， 用以稍後使用傳統蝕刻化學有效地轉移該光罩圖案到基板 110,且在完成該圖案轉移前不蝕刻掉主光罩層160。 既已轉移圖案177及230兩者到主光罩層16〇，接著可使 用層1 6 0作為一光罩以轉移該等圖案到基板丨丨〇，如圖16所 不。已知用於主光罩層160及基板11〇通常為全異材料（例 如分別是非晶碳及矽或矽化合物），可使用適合包括基板 "Ο的该-(或該等)材料的傳統蝕刻以輕易達成該圖案轉 私。例如，一包括含CF4、⑶^及/或_電㈣I碳㈣ 104585.doc -24- 1278020 可用以蝕刻氮化矽，— NF”SF6及/或CF4的電㈣=切，及—含驗、〜 技術者可輕易判定盆減枯了用㈣刻石夕。此外，熟習 板材料如導體等… 枓的適用蝕刻化學’該等基 例 " 匕舌鋁、過渡金屬及過渡金屬氮化物。 ’可使用說碳蝕刻以蝕刻一鋁基板。
―::解’基板11。包括數個不同材料層的地方，可使用 二=同化學’較佳是乾餘化學，以通過此等不同層連 :飯刻。亦應了解’依使用的一個或數個化學而定，可 刻该寺間隔層175及硬式光罩層15〇。然而，主光罩層 :〇的非晶碳可對傳統的敍刻化學有利地提供絕佳阻抗. '，，’尤其是用以姓刻含石夕材料的傳統钱刻化學。因此，主 光罩層160可有效地作為一光罩使用以通過複數個基板層 餘刻’或形成數個高縱橫比的渠溝。此外，間距加倍圖案 m及傳統微影技術形成的圖案23〇可在—單一㈣步驟中 同時轉移到基板110,或基板110的各個別層。 圖17A及17B顯不最終形成的結構。圖17A顯示積體電路 100的陣列部分’而圖17B顯示積體電路1〇〇的周邊（圖2至 16)。如上述，基板UG可為—材料或數個材料構成的任何 層，其中蝕刻有圖案177及23〇。基板11〇的組成例如可依 將形成的電氣裝置而定。因此，在圖17A及17B中，基板 110包括一 Si3N』li〇a、一多晶矽層 u〇b、一 8〇2層 ， 及一矽層110d。數層構成的此一配置例如可有利地用於電 晶體的形成。 104585.doc -25- 1278020 請注意，該等㈣表面呈現特低的邊緣粗^此外，甚 至是以100 nm低間距拍到的圖片，陣列中形成的數個渠溝 亦顯示絕佳的一致性。有利地，達成此等結果時亦在周邊 中形成界定完善且平順的線，如圖17B所示。 應了解’根據㈣較佳實施例形成圖案提供許多優點。 2如’因為具不同尺寸特徵的多個圖案可在轉移到一基板 T先在-單一最後光罩層上合併，因此可輕易轉移數個重 疊圖案到該基板。因此，可輕易形成數個間距加倍特徵及 傳統微影技術形成的數個特徵以互相連接。此外，如圖 ΠΑ及17B中明顯看出，在同時達成特別且意料外地低的 線邊緣粗糙時，亦可形成數個特小的特徵。雖然不受理論 限制’ ^相信此類低線邊緣粗链係使用層140及⑽的結 果。相信是形成該等間隔層175及執行多個各向異性蝕 刻，將該等圖案177及230自暫時層⑽的位準轉移到主光 罩層160’接著轉移到基板11〇’有利地使形成圖案m及 230的該等特徵的表面平順。此外，本文中揭示的較佳非 晶碳㈣化學容許’相對於似彳層1似160等下層非晶碳 層的深度而使用薄的硬式光罩層，如層130及150。此有利 地減低對覆蓋在該等硬式光罩層上的數個層（例如數個光 阻層）完全相同的要求，且在同時確保主光罩層形成夠厚 先罩以耐得住後續基板敍刻時’亦減低對用以姓刻該等硬 式光罩層的化學過程的要求。 亦應了解，所示方法流程可有多種不同修改。例如，由 於數個間距增大圖奢· +丨 Ο水由％、，堯一心軸的數個間隔層形成，因 104585.doc -26- 1278020 此該等圖案通常形成封閉迴路。因此’使用該間距增大圖 本以开/成數個導線之處，較佳使用數個額外處理步驟以切 斷此等迴路的末端，令各迴路形成兩條個别、非連接的 線。 而且，雖然本文中討論的多種層的組合係_刻化學 條件的考量而選擇，但該多種不同硬式光罩層較佳 由相同的材料形成，如同該等主光罩層。有利地’此- 配置減低處理複雜度。 5』必此 此外’圖案1 7 7的間距可多於 , 了夕於兩倍。例如，藉由在間隔 g 75周圍形成數個間隔 基户土、， 接者私除該等間隔層1 75，接 者在先丽環繞該等間隔芦 侵 岸箄，^心在 的間隔層周圍形成數個間隔 層寻，尚可使圖案177的間距掸 示筘古土祖-; 曰大進一步間距增大的一 ”耗方法揭不在LoWery等人 外，錄炒可亡心L 國專利就5,328,810中。此 # % fί ^ ^ κ - 仏只靶例以形成間距增大及 得、、死U衫兩者界定的數個特徵 兩者皆間距增大，或可 、、，互圖案177及230可 ,.k 一有不同程度的間距增大。 此外，視需要可在主氺 ^ 230 运160上合併多於二的圖荦177 及230。在此類例子中 閒茶177 個額外光罩層。例如 ：寺層140與160之間沈積數 硬式光罩層150上的_額夕;等圖案Μ及咖到覆蓋在 1 6所示的、香虫止 層’及接著可執行圖1 〇至 所不的一連串步驟以保 口芏 光可限定岸中形占缸回”荨層177及230，用以在一 π疋層中形成新圖案， 該額外光罩層較佳包括，_轉移该等圖案到基板110。 擇性钱刻的材料相對於硬式光罩層⑼而選 g，其在轉移到該額外光罩層 104585.doc -27- 1278020 後環繞該等圖案1 77及230。 而且，雖然通過多種不同光罩層”處理，，較佳涉及蝕剡一 下層，但通過該等光罩層處理可涉及使該等光罩層下方的 數層X到任何半導體製程。例如，處理可涉及通過該等光 罩層且在數個下層上執行離子植入、擴散摻雜、沈積或濕 蝕等。此外’言亥等光罩層可作為化學機械研磨(cM。的— 停止層或障壁層使用，或在該等光罩層上執行CMP以容許 該等光罩層的平面化及該等下層的蝕刻兩者。 因此，熟諳此藝者應了解，不背離本發明的範圍，上述 方法及、π構可作出其他多種省略、添加及修改。所有此類 你改及、交動思欲涵括在本發明如後附請求項界定的範 内。 【圖式簡單說明】 由較佳實施例的詳細說明及附圖應更了解本發明，該等 說明及附圖係用以說明，而非用以侷限本發明，及其中： 圖1A至1F以示意剖面側視圖說明數個部分形成導線， 其係根據一先前技藝間距加倍方法形成； 圖2A及2B根據本發明數個較佳實施例，以示意剖面上 視圖及側視圖說明一部分形成的記憶體裝置； 圖3根據本發明數個較佳實施例，說明圖2的部分形成纪 fe體裝置在該記憶體裝置的陣列中的一可選擇性限定層中 幵乂成數條線後的示意剖面側視圖； 圖4根據本發明數個較佳實施例，說明圖3的部分形成記 憶體裝置在加寬光阻線間的間隔後的示意剖面側視圖； 104585.doc -28- 1278020 圖5根據本發明數個較佳實施例，說明圖4的部分形成記 憶體裝置在通過-硬式光罩層蝕刻後的示意剖面側視圖； 圖6根據本發明數個較佳實施例，說明圖5的部分形成記 憶體裝置在自該光阻層轉移—圖案到—暫時層後的示意剖 面側視圖； 圖7根據本發明數個較佳實施例，說明圖6的部分形成記 憶體裝置在沈積-層間隔層材料後的示意剖面侧視圖；
圖8根據本發明數個較佳實施例，說明圖7的部分形成記 憶體裝置在-間隔層蝕刻後的示意剖面側視圖； 圖9根據本發明數個較佳實施例，說明，的部分形成記 憶體裝置在移除該暫時層的殘留部分而在該記憶體裝置的 陣列中留τ — Pa1隔層目案後的示意剖面側視圖； 圖10根據本發明數個較佳實施例，說明圖9的部分形成 記憶體裝置在以一可移除材料環繞該等間隔層，及在該等 間隔層之上形成—硬式光罩層及-可選擇性限定層後的示 意剖面側視圖； 圖11根據本發明數個較佳實施例，說明圖10的部分形成 記憶體裝置在該記憶體裝置的周邊中的該 定 中形成-圖案後的示意剖面側視圖； -層 圖12根據本發明數個較佳實施例，說明圖11的部分形成 記憶體裝置在通過該上硬式光罩層㈣後㈣意剖面側視 圖13根據本發明數個較佳 記憶體裝置在自該可選擇性 實施例，說明圖12的部分形成 限定層轉移該圖案到該等間隔 104585-doc •29- 1278020 層的相同位準後的示意剖面側視圖； 圖14根據本發明數個較佳實施例，說明圖丨3的部分形成 記憶體裝置在蝕刻該周邊中的圖案及該陣列中的間隔層圖 案到一下硬式光罩層後的示意剖面側視圖； 圖1 5根據本發明數個較佳實施例，說明圖14的部分形成 記憶體裝置在蝕刻該周邊中的圖案及該陣列中的間隔層圖 案到一主光罩層後的示意剖面側視圖； 圖16根據本發明數個較佳實施例，說明圖。的部分形成 記憶體裝置在#刻該周邊圖案及料列圖案到該基板後的 示意剖面側視圖；及 圖17A及17B以透過一掃描電子顯微鏡看到的顯微照 片°兒明一圖案分別蝕刻到根據本發明數個較佳實施例形 成的一部分形成記憶體裝置中的陣列及周邊中。 【主要元件符號說明】 10 線圖案 20 耗材層 30, 110 基板 40 心軸（位置支架） 50 間隔材料層 60 間隔層 70, 80，180 水平表面 100 積體電路 102 陣列 104 周邊 104585.doc -30- 1278020 110a Si3N4^ 110b 多晶矽層 110c Si02 層 llOd 矽層 120, 220 光可限定層 122 間隔 124, 124a 光阻線 130, 150, 210 硬式光罩層 140 暫時層 160 主光罩層 170 間隔層材料層 175 間隔層 177, 230 光罩圖案 200 保護材料 104585.doc -31 -

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1278020 十、申請專利範圍： 1 . 一種半V體製程之方法，包括·· 提供基板，其中一主光罩層覆蓋在該基板 -暫時層覆蓋在該主光罩層上，一/ 〜、寸 在該暫時層上，· 一 ^ 一弟一光阻層覆羞 在該第一光阻層中形成一光阻圖案；
在該暫時層中形成一第一圖案 個特徵係衍生自該光阻圖案之數個特徵f 一圖案之1 在該第一圖案之-位準上方形成-第丄光阻層； 在忒第二光阻層中形成另一光阻圖案，· /轉移該另-光阻圖案及該第一圖案至該主光罩 係用以在該主光罩層中形成—混合圖案；及 通過該主光罩層中之混合圖案以製程該基板。 2. 如請求们之方法，其中製程該基板包括藉由钱刻該遵 板而轉移該混合圖案至該基板。 3. 如請求項丨之方法，其中形成一光阻圖案及/或形成另一 光阻圖案包括執行電子束微影。 4·如印求項丨之方法，其中形成一光阻圖案及形成另一夭 阻圖案包括以具一波長之光執行微影，該波長光選自逢 13-7 nm、157 _、193 nm、248 nm或 365 nm波長光所翻 成之群組。 5·如請求項4之方法，其中該第一及該第二光阻層包括相 同光阻材料。 6*如請求項4之方法，其中形成該第一圖案尚包括藉由各 104585.doc 1278020 向同性地蝕刻該光阻劑 之寬度減至一期望寬度 將執行微影後殘留 <該光阻劑
如請求項6之方法，其中該第一 後殘留之數個光阻線之輪廓， 括： 圖案遵循各向 其中形成該第 同性餘刻 一圖案包 通過該光阻層蝕刻該暫時層； 之數個侧壁
蝕刻該暫時層後，在該暫時層之殘留部分 上形成數個間隔層；及 μ相對於該等間隔層而優先地移除暫時層材料，其中該 等間隔層形成該第一圖案。 ^ ^ 8·如明求項丨之方法，其中該暫時層包括非晶碳。 士明求項8之方法，其中該主光罩層包括非晶碳。 1〇·如明求項9之方法，其中數個硬式光罩層直接覆蓋在該 暫時層及該主光罩層上。 11.
如請求項10之方法，其中該等硬式光罩層包括一材料， 其選自由矽、二氧化矽，或一抗反射塗層材料所組成之 群組。 12·如請求項丨丨之方法，其中該抗反射塗層材料係一介電質 抗反射塗層。 女3求項1之方法，其中該暫時層包括一底部抗反射塗 層。 14·如睛求項丨3之方法，其中該第二光阻層直接接觸該底部 抗反射塗層，且覆蓋在該塗層上。 1 5 ·如晴求項1之方法，其中該基板係一絕緣體。 104585.doc 1278020 °月求項1 5之方法’其中製程該基板界定一記憶體裝置 陣列之數個導線。 I7· 一種形成一積體電路之方法，包括： 提供一基板； 在忒基板之上形成一非晶碳層； 在该第一非晶碳層之上形成一第一硬式光罩層； 在该第一硬式光罩層之上形成一暫時層；及 ^ ι 在該暫時層之上形成一第二硬式光罩層。 、明求項17之方法，其中形成—非晶碳層包括化學汽相 沈積。 如：求項17之方法’其中該暫時層包括非晶碳。 、—明求項19之方法’其中形成一第二非晶碳層包括化學 汽相沈積。 j长項17之方法，其中形成—第—硬式光罩層及形成 第一硬式光罩層包括化學汽相沈積。 • 米明:項17之方法’其中該第-硬式光罩層包括-材 枓’其選自由氧切、碎，或一介電質抗反射塗層所組 成之群組。 23·::明求項22之方法，其中該第二硬式光罩層包括一材 料其遠自由氧化石夕、石夕，或一介電質抗反射塗層所組 成之群組。 24·如明求項17之方法，其中該非晶碳層之厚度約100至 1 000 nm。 25· 士#求項17之方法，其中該第一硬式光罩層之厚度約w 104585.doc 1278020 至 5 0 nm 〇 之厚度約100至300 26.如請求項17之方法，其中該暫時層 nm 約10 27·如請求項17之方法’其中該 至50_。 冑式先罩層之厚度 28:=:17之方：’尚包括藉由奈米轉印而在該第二硬 3上方之-抗蝕層中沈積及形成_圖案。 29·如铂求項17之方法，尚 積-光阻層。 ^在以二硬式光罩層之上沈 定圖案以形成 3〇·如請求項29之方法，尚包括將該光阻層 光阻圖案。 改變該光阻圖案中之數 31.如請求項30之方法，其中尚包括 個開口之尺寸。 改變該等開口之尺寸包括使該 32_如請求項31之方法，其中 等開口之尺寸變窄。 33·如請求項3 1之方法，其中玢料私 〆、甲改變數個開口 同性地蝕刻該光阻圖案 寸匕括各向 34 5 乂形成一加寬光阻圖案。 •士明求項33之方法，尚包括 ^ . 轉私5亥加覓光阻圖牵5兮筮 二硬式光罩層。 口茶至，亥弟 35·如請求項34之方法，尚句杠純 〇包括轉移該加寬光阻R安=# ^ 時層。 見％ 1且圖案至該暫 36·如請求項35之方法，尚句杠备 ,括在該暫時層之數個側辟上形 成數個間隔層，該暫時層 土上形 成。 …轉移該加寬光阻圖案而形 104585.doc 1278020 37. 38. 如請求項36之方法，尚包括相對於該等 移除該暫時層，以形成一間隔層圖案。 間隔層而優先地 39. 如請求項3 7之方法 硬式光罩層。 如請求項3 8之方法 碳層。 尚包括轉移該間隔層圖案至該第一 尚包括轉移該間隔層圖案至該非晶 尚包括轉移該間隔層圖案至該基 40·如請求項39之方法 板0
41 ·如請求項17之方法層0 其中该基板包括複數個不同材料 、數 42·如明求項41之方法，其中該複數層包括數個半導體 個絶緣體及/或數個導體。 43· —種半導體製造之方法，包括： 藉由間距增大而形成一第一圖案；
藉由無間距增大之微影而分開地形成一第二圖案； 轉移該等第一及第二圖案至一光罩層；及 通過該光罩層以蝕刻一基板。 44·如明求項43之方法，其中形成該第一圖案包括： 形成複數個心軸，其係由非晶碳所構成； 在该等心軸之上沈積一含矽材料之毯狀層；及 各向異性地蝕刻該毯狀層。 45·如請求項43之方法，其中藉由間距加倍而達成一第〜 也 π 圖 案之形成。 46·如請求項43之方法，其中分開地形成一第二圖案包括使 104585.doc 1278020 該第二圖案與該第—圖案重疊。 47·如請求項43之方法，1 中α亥基板包括複數個不同材 層。 4 8 ·如請求項4 7之方法，盆由 丨, /、中#刻一基板包括利用一不同钱 刻化學用於各該複數層。 49· 一種形成一積體電路之方法，包括： 形成一光罩圖案，其中該光罩圖案之一第一部分具有 一第一間距，及其中該光罩圖案之一第二部分具有一第 二間距’其中該第—間距低於界定該第二圖案之微影技 術之一最小間距；及 通過該光罩圖案以蝕刻一基板。 月长員49之方法，其中形成一光罩圖案包括將對應至 該第二部分之一區定圖案，及將對應至該第一部分之一 區分開地定圖案。
月求員5 〇之方法，其中使用一利用248 nm光之微影技 術以執行對應至該第二部分之一區之定圖案。 如巧求項50之方法，其中形成一光罩圖案包括蝕刻一非 晶碳層。 5 3 ·如請求工苜ς π 、之方法’其中餘刻一非晶碳層包括曝露該非 晶碳層至含S02電漿。 5 4 ·如請求jg c 、5 〇之方法，其中該基板包括數個絕緣及導電 層。 55.種形成一記憶體裝置之方法，包括·· 在· 山 兔層上方之一層中形成含數個暫時位置支架之一 104585.doc 1278020 圖案； 在該等暫時位置支牟 文木之數個表面之上沈積一層光罩材 料， 自數個水平表面選擇性地移除該光罩材料；及 才，寸於。亥光罩材料而選擇性地移除該等暫時位置支 架’以形成—光罩材料圖案，其對應至該記憶體裝置之 一陣列區域中之數個特徵。 、:长員55之方去’其中沈積-層光罩材料包括藉由一 低溫化學汽相沈積方法以沈積該光罩材料。 57.如請求項56之方法，苴中 ，、肀4先罩材料包括氮化矽或氧化 石夕。 5 8·如請求項57之方法，苴中 ，、中k擇性地移除該光罩材料包括 以一氟碳電漿蝕刻。 5 9 ·如請求項5 5之方法，其中 ^ ϋ亥寺暫時位置支架包括非晶 石厌° 60=請求項59之方法，其中選擇性地移除該等暫時位置支 木包括以一含二氧化硫之電漿蝕刻。 61·如請求項55之方法，其中— 要士+ 更式先罩層分開該等暫時位 置支架與該碳層。 Μ:請求項Μ之方法’尚包括轉移該光罩材料圖案至該碳 63. =: 62之方法，其中轉移該光罩材料圖案至該碳層 I括曝露該硬式光罩層至一說碳電漿中。 64. 如請求項63之方法，其中轉 邊^罩材料圖案至該碳層 1〇4585.d〇c 1278020 匕括後、、⑦地曝露該第二碳層至_含二氧化硫之電裝中。 65. 士明求項55之方法，其中該光罩材料圖案之一光罩材料 位置對應至該陣列中之數個導線之位置。 66· —種製造一積體電路之方法，包括·· 形成複數個心軸條； 在各心軸條之數個側壁上形成一間隔層； 移除°亥等心軸條以形成一圖案，其含有數個隔開之間 隔層；
67. 在該等間隔層上方之一平面中形成一光罩層； 在該光罩層中形成一圖案；及 轉移該圖案至與該等間隔層才目同之水平面。 如明求項66之方法’其中該等間隔層至少在垂直於該等 間隔層延伸之第-及第二分隔平面之間，W互相分隔 開、大致平行之關係延伸。 68. 如請求項66之方法’尚包括轉移該等間隔層形成之該 案及另圖案至該水平面下方之另一光罩層。 69. 如請求項66之Μ，其中該等心轴條具有L體上垂直 數個侧壁。 70.如π月求項69之方法，其中形成一間隔層包括在該等心 條之數個曝露表面上沈積一間隔層材料，及後續地自 等心轴條之該等側壁以外之數個表面選擇性地移除該 隔層材料。 71·如請求項7〇之方法’其中沈積-間隔層材料包括執行 化學汽相沈積或一原子層沈積方法。 I04585.doc 1278020 Μ::求項7°之方法，其中該間隔層材料包括氮切或氧 73. 如請亡項66之方法’其中形成-光罩層包括： 等移除材料環繞該等間隔層，其中可相對於該 ^ 4而選擇性蝕刻該可移除材料； f接,該層可移除材料上方形成一硬式光罩層；及 該等間隔層上方之該平面中开一 74. 如請求項73 先阻層。 執行微影。中在該光罩層中形成一圖案包括 76, 同之：二6:方法’其中轉移該圖案至與該等間隔層相 门之良千面包括各向異性地蝕刻非晶碳。 一種製造-積體電路之方法，包括： 反it提供一光罩材料製成之複數個分隔線， ^亥先罩材料不同於光阻劑； 中二㈣，在該基板上方之-光可限定層材料 肀將歿數個特徵定圖案；及 在該等分隔線下一曰 該複數個特徵。非日日敌層中複製該等分隔線及 77.如請求項76之方法， 伸之第-Μία 讀至少在以於該等線延 行之關係延伸。 互相刀“開、大致平 78·如請求項76之方法，苴 徵定圖案_之^、= Γ間距小於複數個特 用您械衫技術之一最小間距。 79·如請求項78夕tu 、之方法，其中將複數個特徵定圖案包括曝露 I04585.doc 1278020 光阻劑至具248 nm波長之光中。 80·如凊求項76之方法，其中該 二 之一陣列區域中，及j： n 上δ己憶體電路 體電路之一周邊中…數個特徵大體上在該記憶 81·如請求項76之方法’其中該等線由 而選擇性移除之一㈣◎ ^亥專先罩線 於哕福砉“丄 ’、匕衣’及其中該光可限定材料位 於&數個光罩線及該可移除材料上方。 82·如請求項76之方法， 括猎由各向異性地蝕刻該可移 除材枓而複製該可移除材料中之開口。 了移 8 3 ·如請求項7 6之方、、表 、 法，其中該等線包括氮化矽戋氧^# 84·—::成-光罩圖案以製造-積體電路之方法:：： 棱供一第一光罩材料穿成之滿叙&^ 匕栝· 一暫時材料分開； 旻數條線’該等線由-第 選擇性地蝕刻該第一暫時材料； 以-第二暫時材料填滿該等線間之間隔； :擇性地敍刻該第二暫時材料以打開該等間隔.及 k過該等間隔以選擇性地蝕刻，其係 材料層中形成一圖案。 在另一光罩 85.如請求項84之方法，1 包括餘刻非晶碳。〃 t 银刻該第—暫時材料 求項85之方法，其中餘刻非晶 料至—含二氧化硫之電装中。 』、路及弟一材 87.如請求項85之方法，其中填滿 非晶碳。 、Λ、、” θ1之間隔包括沈積 104585.doc •10- !278〇2〇 如請求項85之方法 下層光阻劑。 89·如請求項88之方法 劑0 其中填滿該等線間之間隔包括沈積 其中該下層抗蝕劑係氟化氪光阻 90· 91. 如請求項85之方法，其中選擇性地㈣該第二材料包括 使用一含二氧化硫之電漿以執行一蝕刻。
°月求項85之方法’其中通過該間隔以選擇性地蝕刻 括執行一硬式光罩蝕刻，及接著使用一含二氧化硫之 漿以蝕刻一非晶碳層。 包 電 92. 93. 94. °月求項9 1之方法，尚包括通過該間隔蝕刻， 厌層下方之一基板中形成數個開口。 明求項92之方法，其中通過該間隔蝕刻以在 形成數個開口包括在一絕緣層中形成該等開口 種製造一積體電路之方法，包括： 用以在該 一基板上
提供一光罩層，其在一部分製造積體電路之—第—及 苐一區域之上延伸；及 ^在該光罩層中形成一圖案，其中該圖案之一部分之一 最小特徵尺寸，該部分對應至該第—區域，約等於或小 於該圖案中另一部分之一最小特徵尺寸之一半，該另— 部分對應至該第二區域。 95. 如請求項94之方法，其中該光罩層包括非晶碳。 96. 如請求項94之方法，其中該積體電路係一記憶體裝置， 其中該第一區域對應至該記憶體裝置之陣列，及其中节 第二區域對應至該記憶體裝置之周邊。 104585.doc -11 - 1278020 97·如請求項94之方法，其中在該光罩層中形成-圖案包括 執打間距增大以用於該第一區域上方之該圖案之數個部 分’及執行無間距增大之微影以用於該第二區域上方之 該圖案之數個部分。 98. —種部分形成之積體電路，包括·· 一碳層；及 複數個間距增大間隔層，其係用以覆蓋該碳層之一位 準 八中°亥荨間隔層具有約100 nm或更小之一間距。 99. 如請求項98之部分形成積體電路，其中該等間隔層至少 在垂直於該等條狀物而延伸之第一與第二分隔平面之 間，以互相分隔開、大致平行之關係延伸。 100. 如請求項98之部分形成積體電路，其中該碳層包括非晶 碳。 101·如請求項98之部分形成積體電路，其中各該複數個間隔 層包括氮化矽或氧化矽。 肌如請求項98之部分形成積體電路，其中該非晶碳層之厚 度約在1〇〇至1000 nm之間。 103. 如請求項98之部分形成積體電路，其中一硬式光罩層分 開该非晶碳層與該複數個間隔層。 104. 如睛求項103之部分形成積體電路，其中該硬式光罩層 之厚度約在1 〇至5 0 nm之間。 105. 如請求項103之部分形成積體電路，其中該等間隔層大 體上位在該部分形成積體電路之一陣列區域。 106·如請求項105之部分形成積體電路，尚包括一圖案，其 104585.doc 12 1278020 由覆蓋在該硬式光罩層上之碳材料所界定。 項106之部分形成積體電路，其中由碳材料所界 案大體上位在該部分形成積體電路之-周邊。 種°卩分形成之積體電路，包括·· 一基板； ::光罩層’其覆蓋在該基板上，該主光罩層 於先阻劑之一材料所形成； 先罩材料，其界定覆蓋在該主光罩層上之—第 面中之一第一圖案；及 -光可限定材料，其界定覆蓋在該光 二平面中之一第二圖案。 之—弟 败如請求物之部分形成積體電路… ⑽二二於該光罩材料而選擇性移除之材料環繞；抖由 r項1〇9之部分形成積體電路 除材料包括一下層抗等 U選擇性移 其中該下層抗蝕劑 其中該可選擇性移 其中該主光罩層係 其中一硬式光罩層 女°月求項110之部分形成積體電路 包括氟化氪光阻劑。 女°月求項109之部分形成積體電路 除材料包括非晶碳。 士明求項108之部分形成積體電路 一非晶碳層。 ％求項11 3之部分形成積體電路 77開该非晶碳層與該光罩材料。 115·如請求項m “形成積體電路’其中該先罩材料包 川4585.doc -13- 1278020 括一含矽材料。 ιΐ6·如請求項115之部分形成積體電路，其中該光罩材 氮化石夕或氧化石夕。 口人 117·如請求項115之部分形成積體電路，其中該光可限定材 料係一光阻劑。 118·如請求項117之部分形成積體電路，其中該光阻劑係與 氟化鼠、II化氬，或157 nm波長微影系統或19 3 nm波長 浸潤式系統相容之一光阻劑。 119•如請求項108之部分形成積體電路，其中一基板位於該 主光罩層之下。 120·如晴求項1〇8之部分形成積體電路，其中該基板係可導 電。 121·如睛求項1〇8之部分形成積體電路，其中該基板包括複 數個不同材料層。
104585.doc 14-
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US20060262511A1 (en) 2006-11-23
US7115525B2 (en) 2006-10-03
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US20100203727A1 (en) 2010-08-12
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US20070148984A1 (en) 2007-06-28
US7629693B2 (en) 2009-12-08

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