CN114068408A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN114068408A
CN114068408A CN202010756098.9A CN202010756098A CN114068408A CN 114068408 A CN114068408 A CN 114068408A CN 202010756098 A CN202010756098 A CN 202010756098A CN 114068408 A CN114068408 A CN 114068408A
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semiconductor device
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陈冠廷
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United Microelectronics Corp
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Priority to US17/001,697 priority patent/US11610777B2/en
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Priority to US18/109,864 priority patent/US20230197451A1/en
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Abstract

本发明公开一种半导体元件及其制作方法，其中制作半导体元件的方法为，首先形成一硬掩模于基底上，然后形成第一轴心体以及第二轴心体于硬掩模上，形成第一间隙壁及第二间隙壁环绕第一轴心体以及第三间隙壁及第四间隙壁环绕第二轴心体，去除第二轴心体，形成一图案化掩模于第一轴心体、第一间隙壁、第二间隙壁、第三间隙壁及第四间隙壁上，再利用图案化掩模去除第三间隙壁以及硬掩模。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作场效晶体管的方法，尤其是涉及一种利用图案转移制作工艺于基底上形成鳍状场效晶体管的方法。
背景技术
随着半导体元件尺寸的缩小，维持小尺寸半导体元件的效能是目前业界的主要目标。然而，随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。非平面(non-planar)式场效晶体管元件，例如鳍状场效晶体管(fin field effect transistor,FinFET)元件，具有立体结构可增加与栅极之间接触面积，进而提升栅极对于通道区域的控制，俨然已取代平面式场效晶体管成为目前的主流发展趋势。
现有鳍状场效晶体管的制作工艺是先将鳍状结构形成于基底上，再将栅极形成于鳍状结构上。鳍状结构一般为蚀刻基底所形成的条状鳍片，但在尺寸微缩的要求下，各鳍片宽度渐窄，而鳍片之间的间距也渐缩小。因此，其制作工艺也面临许多限制与挑战，例如现有掩模及光刻蚀刻技术受限于微小尺寸的限制，无法准确定义鳍状结构的位置而造成鳍片倒塌，或是无法准确控制蚀刻时间而导致过度蚀刻等问题，连带影响鳍状结构的作用效能。
发明内容
本发明一实施例揭露一种制作半导体元件的方法。首先形成一硬掩模于基底上，然后形成第一轴心体以及第二轴心体于硬掩模上，形成第一间隙壁及第二间隙壁环绕第一轴心体以及第三间隙壁及第四间隙壁环绕第二轴心体，去除第二轴心体，形成一图案化掩模于第一轴心体、第一间隙壁、第二间隙壁、第三间隙壁及第四间隙壁上，再利用图案化掩模去除第三间隙壁以及硬掩模。
本发明另一实施例揭露一种半导体元件，其主要包含一基座设于基底上、一第一鳍状结构设于基座旁以及一第二鳍状结构设于第一鳍状结构旁，其中设于基座以及第一鳍状结构间的基底表面包含一第一上凹曲面，基座顶部切齐鳍状结构顶部，以及第一鳍状结构及第二鳍状结构间的基底表面包含一第二上凹曲面。
附图说明
图1至图6为本发明第一实施例制作一半导体元件的方法示意图；
图7为本发明一实施例的半导体元件的结构示意图。
主要元件符号说明
12:基底
14:第一区域
16:第二区域
18:衬垫层
20:衬垫层
22:硬掩模
24:轴心体
26:间隙壁
28:间隙壁
30:间隙壁
32:间隙壁
34:间隙壁
36:间隙壁
38:间隙壁
40:间隙壁
42:间隙壁
44:图案化掩模
46:开口
48:基座
50:鳍状结构
52:鳍状结构
54:鳍状结构
56:鳍状结构
58:鳍状结构
60:浅沟隔离
62:栅极结构
64:上凹曲面
66:下凹曲面
具体实施方式
请参照图1至图6，图1至图6为本发明第一实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，例如一硅基底，且基底12上具有一第一区域14以及第二区域16。其中第一区域14、第二区域16与第三区域18较佳于后续制作工艺中依据产品的需求来制作不同型态的半导体元件，例如在本实施例中，第一区域14可用来制作平面型金属氧化物半导体元件，第二区域16则可为逻辑区用来制作鳍状结构晶体管或为存储器区且用来制作静态随机存取存储器(SRAM)。
然后依序形成一衬垫层18、一衬垫层20以及一硬掩模22于基底12上，其中衬垫层18较佳包含氧化硅，衬垫层20较佳包含氮化硅，硬掩模22较佳包含氧化硅，但均不局限于此。接着形成多个轴心体(mandrel)24于硬掩模22上。在本实施例中，制作轴心体24的方式可先全面性形成至少一材料层(图未示)于基底12或硬掩模22上，然后进行一图案转移制作工艺，例如利用蚀刻去除部分材料层，以形成多个图案化材料层作为轴心体24于基底12上。其中轴心体24可选自由非晶硅(amorphous silicon)、多晶硅(polysilicon)、氧化硅以及氮化硅所构成的群组，但并不局限于此。另外在本实施例中，第一区域14中的轴心体24宽度较佳大于第二区域16中的各轴心体24宽度，且各轴心体24之间可具有相同或不同间距与线宽。
随后如图2所示，先形成一遮盖层(图未示)并覆盖于轴心体24与硬掩模22，再利用回蚀刻去除部分遮盖层，以形成间隙壁26、28、30、32、34、36、38、40、42于各轴心体24旁。然后可进行形成一图案化掩模(图未示)并覆盖第一区域14，再利用蚀刻去除第二区域16上的所有轴心体24。去除图案化掩模后第一区域14上仍设有轴心体24以及间隙壁26而第二区域16上则仅留下间隙壁28、30、32、34、36、38、40、42。
如图3所示，接着形成一图案化掩模44例如一图案化光致抗蚀剂于硬掩模22上并覆盖第一区域14的轴心体24及间隙壁26以及第二区域16的部分间隙壁包括间隙壁30、34、36、40、42，其中图案化掩模44具有多个开口46暴露出剩余的部分间隙壁28、32、38。
然后如图4所示，利用图案化掩模44为掩模去除第二区域16的间隙壁28、32、38及部分硬掩模22后再去除图案化掩模44并暴露出第一区域14的轴心体24与间隙壁26及第二区域16的间隙壁30、34、36、40、42，其中第一区域14的轴心体24与间隙壁26及第二区域16的间隙壁30、34、36、40、42均设于被图案化的硬掩模22上。
接着于去除图案化掩模44后选择性进行一鳍状结构切割制作工艺例如去除第二区域16的部分间隙壁40、42并使剩余的间隙壁40、42仍设于图案化的硬掩模22上。需注意的是，若以上视角度来看间隙壁例如间隙壁40、42在进行鳍状结构切割制作工艺之前较佳呈现一约略环形设于图案化的硬掩模22上，且由于各间隙壁的图案较佳对应后续所形成鳍状结构的图案，因此本阶段所进行的所谓鳍状结构切割制作工艺主要依据制作工艺需求利用蚀刻去除部分间隙壁40、42并将环形的间隙壁40、42转换为长条形的间隙壁40、42于硬掩模22上。若以剖面角度来看间隙壁40、42在鳍状结构切割制作工艺后仍呈现独立的个体状设于硬掩模22上。
如图5所示，随后利用第一区域14的轴心体24与间隙壁26及第二区域16的间隙壁30、34、36、40、42为掩模去除下方的硬掩模22、衬垫层20、衬垫层18以及基底12以形成一基座48于第一区域14以及多个鳍状结构50、52、54、56、58于第二区域16。之后再去除第一区域14的轴心体24与间隙壁26及第二区域16的间隙壁30、34、36、40、42。
然后如图6所示，形成一浅沟隔离(shallow trench isolation,STI)60环绕基座48以及鳍状结构50、52、54、56、58。在本实施例中，形成浅沟隔离52的方式可先利用一可流动式化学气相沉积(flowable chemical vapor deposition,FCVD)制作工艺形成一氧化硅层(图未示)于基底12上并完全覆盖基座48及鳍状结构50、52、54、56、58。接着利用蚀刻或平坦化制作工艺如化学机械研磨(chemical mechanical polishing,CMP)制作工艺去除部分氧化硅层、硬掩模22、衬垫层20以及衬垫层18，使剩余的氧化硅层切齐或略高于鳍状结构50、52、54、56、58表面以形成浅沟隔离60。
接着可进行一离子注入，将所需的N型或P型掺质注入基座48及鳍状结构50、52、54、56、58中，并伴随进行一热处理制作工艺，使所注入的掺质扩散以形成后续所制备半导体元件所需的阱区(图未示)。之后可依据制作工艺需求进行后续晶体管元件的制作工艺，例如可先去除部分浅隔离60并使其上表面略低于鳍状结构50、52、54、56、58，再形成由例如多晶硅材料所构成的栅极结构62于基座48与鳍状结构50、52、54、56、58上、形成间隙壁于栅极结构62侧壁以及形成源极/漏极区域于间隙壁两侧的鳍状结构内等标准晶体管制作工艺步骤，在此不另加赘述。
请继续参照图6及图7，图6及图7分别为本发明不同实施例的半导体元件的结构示意图。如图6及图7所示，本发明依据前述制作工艺利用第一区域14的轴心体24与间隙壁26及第二区域16的间隙壁30、34、36、40、42为掩模去除下方的硬掩模22、衬垫层20、衬垫层18以及基底12以形成基座48及鳍状结构50、52、54、56、58时可同时调整蚀刻所使用的配方使鳍状结构50、52、54、56、58之间的基底12表面形成不同曲面。
在本实施例中，形成基座48以及鳍状结构50、52、54、56、58所使用的蚀刻配方可包含溴化氢(hydrogen bromide,HBr)以及/或四氟化碳(carbon tetrafluoride,CF4)，其中溴化氢以及四氟化碳的流量可介于0至500每分钟标准毫升(standard cubic centimeterper minute,sccm)。更具体而言，本发明于蚀刻制作工艺时可调升溴化氢的比例来形成图6中所示于基座48以及鳍状结构50、52、54、56、58之间具有上凹弧度的上凹曲面64，其中基座48与鳍状结构50之间的上凹曲面64以及鳍状结构50、52、54、56、58之间的上凹曲面64即使因距离或线宽的不同又可依据制作工艺需求具有相同曲率或不同曲率。在本实施例中，鳍状结构例如鳍状结构52、54之间的线宽较佳小于鳍状结构50、52之间的线宽，鳍状结构50、52之间的线宽较佳小于基座48与鳍状结构50之间的线宽且鳍状结构52、54或鳍状结构50、52之间的上凹曲面64曲率也等同于基座48与鳍状结构50之间的上凹曲面64曲率，但均不局限于此。
除了依序上述手段调升溴化氢的比例来形成如图6中的上凹曲面64外，本发明也可选择于蚀刻制作工艺时调升四氟化碳的比例来形成如图7中所示基座48以及鳍状结构50、52、54、56、58之间具有下凹弧度的下凹曲面66。如同图6的实施例，图7中基座48与鳍状结构50之间的下凹曲面66以及鳍状结构50、52、54、56、58之间的下凹曲面66即使因距离或线宽的不同又可依据制作工艺需求具有相同曲率或不同曲率。在本实施例中，鳍状结构例如鳍状结构52、54之间的线宽较佳小于鳍状结构50、52之间的线宽，鳍状结构50、52之间的线宽较佳小于基座48与鳍状结构50之间的线宽且鳍状结构52、54或鳍状结构50、52之间的下凹曲面66曲率也等同于基座48与鳍状结构50之间的下凹曲面曲率，但均不局限于此。
此外除了上述实施例中利用调整蚀刻制作工艺中的气体流量来分别形成具有上凹曲面64或下凹曲面66的基底12表面，依据本发明又一实施例又可选择调整上下电极的电位差来得到类似效果。例如本发明可利用较小的电位差来得到如图6中所示的上凹曲面64，中等电位差来使基座48与鳍状结构50或鳍状结构50、52、54、56、58之间的基底12表面形成完全平整的表面(未示于图5或图6)，或利用较大的电位差来得到如图7中所示的下凹曲面66，这些实施例均属本发明所涵盖的范围。
综上所述，相较于现有制作鳍状结构时以多次图案转移制作工艺将所制备的鳍状结构分别转移至硬掩模或衬垫层，本发明较佳先利用一道图案化掩模44去除轴心体旁的部分间隙壁并由此定义出欲形成的鳍状结构图案于硬掩模22上，接着进行鳍状结构切割制作工艺后再以一道蚀刻制作工艺同时利用被轴心体以及剩余的间隙壁直接形成具有较大线宽的基座48以及鳍状结构50、52、54、56、58。由于本发明较佳将鳍状结构切割制作工艺的步骤移到利用间隙壁来图案化形成鳍状结构的阶段如此即可避免鳍状结构之间的基底底部不至因鳍状结构切割制作工艺产生多余的凹洞并确保鳍状结构在深度及底部具有均一的轮廓。
另外本发明另一实施例又可利用蚀刻制作工艺去除部分基底形成鳍状结构时调整蚀刻剂例如溴化氢以及四氟化碳的流量使基座以及/或鳍状结构之间的基底表面形成图6中具有连续性的上凹曲面或图7中的下凹曲面，其中鳍状结构之间的上凹曲面或下凹曲面可用来调整基底12表面与浅沟隔离60之间的应力表现。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种制作半导体元件的方法，其特征在于，包含：
形成硬掩模于基底上；
形成第一轴心体以及第二轴心体于该硬掩模上；
形成第一间隙壁以及第二间隙壁环绕该第一轴心体以及第三间隙壁以及第四间隙壁环绕该第二轴心体；
去除该第二轴心体；
形成图案化掩模于该第一轴心体、该第一间隙壁、该第二间隙壁、该第三间隙壁以及该第四间隙壁上；以及
利用该图案化掩模去除该第三间隙壁以及该硬掩模。
2.如权利要求1所述的方法，另包含：
形成第一衬垫层于该基底上；
形成第二衬垫层于该第一衬垫层上；以及
在形成该第二衬垫层后形成该硬掩模。
3.如权利要求2所述的方法，其中该第一衬垫层以及该第二衬垫层包含不同材料。
4.如权利要求2所述的方法，还包含：
去除该图案化掩模；以及
利用该第一轴心体、该第一间隙壁、该第二间隙壁以及该第四间隙壁去除该硬掩模、该第二衬垫层、该第一衬垫层以及该基底以形成基座以及鳍状结构。
5.如权利要求4所述的方法，另包含于去除该图案化掩模后进行鳍状结构切割制作工艺。
6.如权利要求5所述的方法，另包含于进行该鳍状结构切割制作工艺后去除该硬掩模、该第二衬垫层、该第一衬垫层以及该基底。
7.如权利要求4所述的方法，其中该基座以及该鳍状结构间的基底表面包含上凹曲面。
8.如权利要求4所述的方法，其中该基座以及该鳍状结构间的基底表面包含下凹曲面。
9.一种半导体元件，其特征在于，包含：
基座，设于基底上；以及
第一鳍状结构，设于该基座旁，其中设于该基座以及该第一鳍状结构间的基底表面包含第一上凹曲面。
10.如权利要求9所述的半导体元件，其中该基座顶部切齐该鳍状结构顶部。
11.如权利要求9所述的半导体元件，另包含第二鳍状结构设于该第一鳍状结构旁，其中该第一鳍状结构以及该第二鳍状结构间的基底表面包含第二上凹曲面。
12.如权利要求11所述的半导体元件，其中该第一上凹曲面以及该第二上凹曲面包含相同曲率。
13.如权利要求11所述的半导体元件，其中该第一上凹曲面以及该第二上凹曲面包含不同曲率。
14.如权利要求11所述的半导体元件，其中该第一鳍状结构以及该第二鳍状结构间的线宽小于该基座以及该第一鳍状结构间的线宽。
15.一种半导体元件，其特征在于，包含：
基座，设于基底上；以及
第一鳍状结构，设于该基座旁，其中设于该基座以及该第一鳍状结构间的基底表面包含第一下凹曲面。
16.如权利要求15所述的半导体元件，其中该基座顶部切齐该鳍状结构顶部。
17.如权利要求15所述的半导体元件，另包含第二鳍状结构于该第一鳍状结构旁，其中该第一鳍状结构以及该第二鳍状结构间的基底表面包含第二下凹曲面。
18.如权利要求15所述的半导体元件，其中该第一下凹曲面以及该第二下凹曲面包含相同曲率。
19.如权利要求15所述的半导体元件，其中该第一下凹曲面以及该第二下凹曲面包含不同曲率。
20.如权利要求15所述的半导体元件，其中该第一鳍状结构以及该第二鳍状结构间的线宽小于该基座以及该第一鳍状结构间的线宽。
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