KR970054487A - Mos 트랜지스터 및 그의 제조방법 - Google Patents

Mos 트랜지스터 및 그의 제조방법 Download PDF

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KR970054487A
KR970054487A KR1019960041523A KR19960041523A KR970054487A KR 970054487 A KR970054487 A KR 970054487A KR 1019960041523 A KR1019960041523 A KR 1019960041523A KR 19960041523 A KR19960041523 A KR 19960041523A KR 970054487 A KR970054487 A KR 970054487A
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insulating film
film
sidewall
silicon oxide
gate electrode
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KR100221063B1 (ko
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가츠지 이구치
겐이치 아주마
아키오 가와무라
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쯔지 하루오
샤프 가부시끼가이샤
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Abstract

필드영역을 가진 반도체기판; 게이트절연막을 통해 반도체기판상에 형성된 게이트전극; 및 상기 반도체기판내에 형성된 소스/드레인영역을 포함하며; 상기 필드영역이 적어도 하나의 하층절연막 및 그 하층절연막에 대해 선택적으로 에칭가능한 재료로 형성된 상층절연막을 포함하며; 상기 게이트전극은 상기 소스/드레인영역들 사이에 배치된 채널영역과 대향하는 하부면의 게이트 길이보다 상부면의 게이트 길이가 더 길게 된 형상으로 되며; 상기 게이트전극은 그의 측벽과 접촉하여 채널영역의 외주를 피복하며, 상기 하층절연막, 및 상기 상층절연막에 대해 선택적으로 에칭가능한 재료로 형성된 측벽절연층으로 된 사이드월 스페이서를 가지며; 상기 채널영역은 소스/드레인영역에 대해 거의 평탄하게 되어있는 MOS 트랜지스터가 개시된다.

Description

MOS 트랜지스터 및 그의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1(a)도 및 제1(b)도는 본 발명의 일실시예에 따른 MOS 트랜지스터의 개략횡단면도 및 종단면도.

Claims (10)

  1. 필드영역을 가진 반도체기판; 게이트절연막을 통해 반도체기판상에 형성된 게이트전극; 및 상기 반도체기판내에 형성된 소스/드레인영역을 포함하며; 상기 필드영역이 적어도 하나의 하층절연막 및 그 하층절연막에 대해 선택적으로 에칭가능한 재료로 형성된 상층절연막을 포함하며; 상기 게이트전극은 상기 소스/드레인영역들 사이에 배치된 채널영역과 대향하는 하부면의 게이트 길이보다 상부면의 게이트 길이가 더 길게 된 형상으로 되며; 상기 게이트전극은 그의 측벽과 접촉하여 채널영역의 외주를 피복하며, 상기 하층절연막, 및 상기 상층절연막에 대해 선택적으로 에칭가능한 재료로 형성된 측벽절연층으로 된 사이드월 스페이서를 가지며; 상기 채널영역은 소스/드레인영역에 대해 거의 평탄하게 되어있는 MOS 트랜지스터.
  2. 제1항에 있어서, 상기 상층절연막이 하층절연막의 재료보다 5-30배 더 빠른 속도로 에칭될 수 있는 재료로 형성되는 MOS 트랜지스터.
  3. 제1항에 있어서, 상기 상층절연막이 실리콘산화막으로 형성되고, 상기 하층절연막이 실리콘질화막/실리콘산화막으로 된 2층막으로 형성되는 MOS 트랜지스터.
  4. 제1항에 있어서, 상기 측벽절연층이 실리콘산화막 및 그 실리콘산화막을 피복하는 실리콘질화막을 포함하는 MOS 트랜지스터.
  5. 제1항에 있어서, 상기 상층절연막이 실리콘산화막으로 형성되고, 상기 하층절연막이 실리콘질화막/실리콘산화막으로 된 2층막으로 형성되며, 상기 측벽절연층이 실리콘산화막 및 그 실리콘산화막을 피복하는 실리콘질화막을 포함하는 MOS 트랜지스터.
  6. (i) 반도체기판의 전면에 하층절연막과 상층절연막을 형성하고, 채널영역 및 그 채널영역의 외주상의 상층절연막에 하층절연막으로 연장하는 구멍부를 형성하는 공정; (ii) 상기 상층절연막에 형성된 구멍부의 측벽상의 상층절연막에 대해 선택적으로 에칭가능한 재료로 된 측벽절연층을 형성하고, 상기 측벽절연층 아래를 제외한 구멍부의 하부에 존재하는 하층절연막의 부분을 제거하여 상기 반도체기판을 노출시키는 공정; (iii) 노출된 반도체기판상에 게이트절연막을 형성하는 공정; (iv) 상기 게이트절연막상에 상기 측벽절연층의 적어도 일부를 피복하도록 게이트전극을 형성하는 공정; 및 (v) 소스/드레인영역이 형성될 영역들상의 상층절연막의 일부를 제거하여 게이트전극의 측벽과 접촉하는 사이드월 스페이서를 형성하는 공저응로 구성되는 MOS 트랜지스터 제조방법.
  7. 제6항에 있어서, 상기 공정(i)에서, 상기 하층절연막이 제1절연막 및 그 제1절연막에 대해 선택적으로 에칭가능한 재료로 된 제2절연막으로 형성되는 MOS 트랜지스터 제조방법.
  8. 제6항에 있어서, 상기 공정(i)에서, 상기 하층절연막이 실리콘질화막/실리콘산화막으로 형성되고, 상기 상층절연막이 실리콘산화막으로 형성되는 MOS 트랜지스터 제조방법.
  9. 제6항에 있어서, 상기 공정(ii)에서 상기 측벽절연층은, 구멍부를 포함하는 상층절연막상에 실리콘질화막과 실리콘산화막을 그 순서대로 형성하여서 된 MOS 트랜지스터 제조방법.
  10. 제6항에 있어서, (vi) 게이트전극 및 사이드월 스페이서를 마스크로 이용하여 1(tan 1=사이드월 스페이서 단부에서 게이트전극 단부까지의 거리 SG/ 사이드월 스페이서의 높이 Sh) 이상의 주입각도로 제1이온을 주입하고, 이어서 2(tan 2=채널영역에 대향하는 게이트전극의 하부면의 단부에서 게이트전극의 상부면의 단부까지의 거리 BS/ 사이드월 스페이서의 높이 Sh) 이상의 주입각도로 제2이온을 주입함에 의해 소스/드레인영역을 형성하는 공정을 더 포함하는 MOS 트랜지스터 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960041523A 1995-12-01 1996-09-19 Mos 트랜지스터 및 그의 제조방법 KR100221063B1 (ko)

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