KR840005933A - 전계효과 트랜지스터의 제조방법 - Google Patents
전계효과 트랜지스터의 제조방법 Download PDFInfo
- Publication number
- KR840005933A KR840005933A KR1019830004240A KR830004240A KR840005933A KR 840005933 A KR840005933 A KR 840005933A KR 1019830004240 A KR1019830004240 A KR 1019830004240A KR 830004240 A KR830004240 A KR 830004240A KR 840005933 A KR840005933 A KR 840005933A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- gate electrode
- mask
- etching
- mask member
- Prior art date
Links
- 230000005669 field effect Effects 0.000 title claims description 3
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 239000012535 impurity Substances 0.000 claims 5
- 238000005530 etching Methods 0.000 claims 4
- 239000004065 semiconductor Substances 0.000 claims 4
- 239000007769 metal material Substances 0.000 claims 3
- 239000012212 insulator Substances 0.000 claims 2
- 238000000034 method Methods 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 2
- 239000000463 material Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
- H01L21/26546—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
- H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
- H01L29/66863—Lateral single gate transistors
- H01L29/66878—Processes wherein the final gate is made before the formation, e.g. activation anneal, of the source and drain regions in the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/083—Ion implantation, general
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/143—Shadow masking
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 전계효과 트랜지스터(PET)를 설명하는 단면도.
제4도는 본 발명을 설명하는 단면도.
제5도는 본 발명의 실시예외 PET 소자의 제작 순서를 도시한 장치의 단면도이다.
Claims (2)
- 반도체 기판위에 그 반도체 쇼트키이 접촉을 형성하는 금속 재료로 형성된 게이트 전극과 이 게이트 전극위에 게이트 전극의 주변에서 오오버 행하는 마스크 부재를 형성하는 공정. 상기 마스크 부재를 마스크로하여 반도체 기판에 불순물을 이온 입주해서 제1의 불순물 영역과 제1의 불순물 영역을 형성하는 공정. 상기 마스크 부재의 아래의 게이트전극의 측면을 포함한 이 중간 구조체 표면에 절연물층을 형성하는 공정. 적어도 상기 마스크 부재절연물층을 적어도 게이트 전극 측면부를 남겨서 엣칭하고상기 제1및 제2의 불순물 영역을 노출하는 공정. 노출된 제1및 제2의 불순물 영역에 각각 전극을 형성하는 공정이 있는 것을 특징으로 하는 상기 사항을 포함하는 전계효과 트랜지스터의 제조방법.
- 상기 마스트 부재는 상기 반도체와 쇼트키이 접촉을 형성하는 금속재료를 엣칭하는 엣칭법에서 엣칭되지 않는 재료로 형성되어 그 마스크 부재를 마스크로 하여 그 금속재료를 엣칭하는 것에 의해서 게이트 전극 맞마스크 부재를 형성하는 것을 특징으로 하는 특허청구의 범위 제1항의 기재의 전계효과 트랜지스터의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP159611 | 1982-09-16 | ||
JP57-159611 | 1982-09-16 | ||
JP57159611A JPS5950567A (ja) | 1982-09-16 | 1982-09-16 | 電界効果トランジスタの製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR840005933A true KR840005933A (ko) | 1984-11-19 |
KR920002090B1 KR920002090B1 (ko) | 1992-03-10 |
Family
ID=15697490
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019830004240A KR920002090B1 (ko) | 1982-09-16 | 1983-09-09 | 전계효과 트랜지스터의 제조방법 |
Country Status (6)
Country | Link |
---|---|
US (1) | US4546540A (ko) |
EP (1) | EP0106174B1 (ko) |
JP (1) | JPS5950567A (ko) |
KR (1) | KR920002090B1 (ko) |
CA (1) | CA1205922A (ko) |
DE (1) | DE3379296D1 (ko) |
Families Citing this family (47)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5536967A (en) * | 1980-12-30 | 1996-07-16 | Fujitsu Limited | Semiconductor device including Schottky gate of silicide and method for the manufacture of the same |
US4694563A (en) * | 1981-01-29 | 1987-09-22 | Sumitomo Electric Industries, Ltd. | Process for making Schottky-barrier gate FET |
JPS60137070A (ja) * | 1983-12-26 | 1985-07-20 | Toshiba Corp | 半導体装置の製造方法 |
GB2156579B (en) * | 1984-03-15 | 1987-05-07 | Standard Telephones Cables Ltd | Field effect transistors |
JPH0713978B2 (ja) * | 1984-05-17 | 1995-02-15 | ソニー株式会社 | 半導体装置の製造方法 |
JPS61108175A (ja) * | 1984-11-01 | 1986-05-26 | Toshiba Corp | 半導体装置及び製造方法 |
JPS61117868A (ja) * | 1984-11-14 | 1986-06-05 | Toshiba Corp | 半導体装置及びその製造方法 |
US5187111A (en) * | 1985-09-27 | 1993-02-16 | Kabushiki Kaisha Toshiba | Method of manufacturing Schottky barrier gate FET |
US4847212A (en) * | 1987-01-12 | 1989-07-11 | Itt Gallium Arsenide Technology Center | Self-aligned gate FET process using undercut etch mask |
US4782032A (en) * | 1987-01-12 | 1988-11-01 | Itt Gallium Arsenide Technology Center, A Division Of Itt Corporation | Method of making self-aligned GaAs devices having TiWNx gate/interconnect |
US5140387A (en) * | 1985-11-08 | 1992-08-18 | Lockheed Missiles & Space Company, Inc. | Semiconductor device in which gate region is precisely aligned with source and drain regions |
DE3576610D1 (de) * | 1985-12-06 | 1990-04-19 | Ibm | Verfahren zum herstellen eines voellig selbstjustierten feldeffekttransistors. |
US4673446A (en) * | 1985-12-12 | 1987-06-16 | The United States Of America As Represented By The Secretary Of The Navy | Method of forming thermally stable high resistivity regions in n-type indium phosphide by oxygen implantation |
US4670090A (en) * | 1986-01-23 | 1987-06-02 | Rockwell International Corporation | Method for producing a field effect transistor |
JPS62199068A (ja) * | 1986-02-27 | 1987-09-02 | Toshiba Corp | 半導体装置及びその製造方法 |
JPH07120673B2 (ja) * | 1986-03-06 | 1995-12-20 | 住友電気工業株式会社 | ショットキゲート電界効果トランジスタの製造方法 |
US4735913A (en) * | 1986-05-06 | 1988-04-05 | Bell Communications Research, Inc. | Self-aligned fabrication process for GaAs MESFET devices |
JPS62262466A (ja) * | 1986-05-09 | 1987-11-14 | Toshiba Corp | Mes fetの製造方法 |
US4738934A (en) * | 1986-05-16 | 1988-04-19 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method of making indium phosphide devices |
US4745082A (en) * | 1986-06-12 | 1988-05-17 | Ford Microelectronics, Inc. | Method of making a self-aligned MESFET using a substitutional gate with side walls |
US4731339A (en) * | 1986-08-25 | 1988-03-15 | Rockwell International Corporation | Process for manufacturing metal-semiconductor field-effect transistors |
JPS63155671A (ja) * | 1986-12-18 | 1988-06-28 | Nec Corp | 半導体装置の製造方法 |
US4849376A (en) * | 1987-01-12 | 1989-07-18 | Itt A Division Of Itt Corporation Gallium Arsenide Technology Center | Self-aligned refractory gate process with self-limiting undercut of an implant mask |
FR2613134B1 (fr) * | 1987-03-24 | 1990-03-09 | Labo Electronique Physique | Dispositif semiconducteur du type transistor a effet de champ |
US4808545A (en) * | 1987-04-20 | 1989-02-28 | International Business Machines Corporation | High speed GaAs MESFET having refractory contacts and a self-aligned cold gate fabrication process |
US5229323A (en) * | 1987-08-21 | 1993-07-20 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor device with Schottky electrodes |
US4792531A (en) * | 1987-10-05 | 1988-12-20 | Menlo Industries, Inc. | Self-aligned gate process |
US5093280A (en) * | 1987-10-13 | 1992-03-03 | Northrop Corporation | Refractory metal ohmic contacts and method |
JPH01161773A (ja) * | 1987-12-18 | 1989-06-26 | Agency Of Ind Science & Technol | 化合物半導体装置の製造方法 |
NL8801772A (nl) * | 1988-07-13 | 1990-02-01 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij op een oppervlak van een halfgeleiderlichaam geisoleerde geleidersporen worden aangebracht. |
JPH02138750A (ja) * | 1988-08-24 | 1990-05-28 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JPH02103939A (ja) * | 1988-10-12 | 1990-04-17 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
US5237192A (en) * | 1988-10-12 | 1993-08-17 | Mitsubishi Denki Kabushiki Kaisha | MESFET semiconductor device having a T-shaped gate electrode |
EP0406434B1 (en) * | 1988-11-18 | 1996-07-17 | Kabushiki Kaisha Shibaura Seisakusho | Dry-etching method |
JPH02271537A (ja) * | 1989-04-12 | 1990-11-06 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US4874713A (en) * | 1989-05-01 | 1989-10-17 | Ncr Corporation | Method of making asymmetrically optimized CMOS field effect transistors |
US5053348A (en) * | 1989-12-01 | 1991-10-01 | Hughes Aircraft Company | Fabrication of self-aligned, t-gate hemt |
KR920007357B1 (ko) * | 1990-03-12 | 1992-08-31 | 재단법인 한국전자통신연구소 | 내열성 게이트를 이용한 갈륨비소 반도체 소자의 제조방법 |
US5158896A (en) * | 1991-07-03 | 1992-10-27 | International Business Machines Corporation | Method for fabricating group III-V heterostructure devices having self-aligned graded contact diffusion regions |
JP2702338B2 (ja) * | 1991-10-14 | 1998-01-21 | 三菱電機株式会社 | 半導体装置、及びその製造方法 |
JPH05291307A (ja) * | 1991-12-05 | 1993-11-05 | Samsung Electron Co Ltd | 化合物半導体装置及びその製造方法 |
US5468689A (en) * | 1993-11-16 | 1995-11-21 | At&T Corp. | Method for preparation of silicon nitride gallium diffusion barrier for use in molecular beam epitaxial growth of gallium arsenide |
US5505816A (en) * | 1993-12-16 | 1996-04-09 | International Business Machines Corporation | Etching of silicon dioxide selectively to silicon nitride and polysilicon |
US5482872A (en) * | 1994-01-31 | 1996-01-09 | Motorola, Inc. | Method of forming isolation region in a compound semiconductor substrate |
KR950034830A (ko) * | 1994-04-29 | 1995-12-28 | 빈센트 비. 인그라시아 | 전계 효과 트랜지스터 및 이 트랜지스터의 제조 방법 |
JP3734586B2 (ja) * | 1997-03-05 | 2006-01-11 | 富士通株式会社 | 半導体装置及びその製造方法 |
US6319742B1 (en) * | 1998-07-29 | 2001-11-20 | Sanyo Electric Co., Ltd. | Method of forming nitride based semiconductor layer |
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US3994758A (en) * | 1973-03-19 | 1976-11-30 | Nippon Electric Company, Ltd. | Method of manufacturing a semiconductor device having closely spaced electrodes by perpendicular projection |
US3906541A (en) * | 1974-03-29 | 1975-09-16 | Gen Electric | Field effect transistor devices and methods of making same |
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JPS5928992B2 (ja) * | 1975-02-14 | 1984-07-17 | 日本電信電話株式会社 | Mosトランジスタおよびその製造方法 |
IT1041193B (it) * | 1975-08-08 | 1980-01-10 | Selenia Ind Elettroniche | Perfezionamenti nei procedimenti per la fabbricazione di dispositivi a semiconduttor |
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JPS57128071A (en) * | 1981-01-30 | 1982-08-09 | Fujitsu Ltd | Field-effect type semiconductor device and manufacture thereof |
US4414737A (en) * | 1981-01-30 | 1983-11-15 | Tokyo Shibaura Denki Kabushiki Kaisha | Production of Schottky barrier diode |
US4389768A (en) * | 1981-04-17 | 1983-06-28 | International Business Machines Corporation | Self-aligned process for fabricating gallium arsenide metal-semiconductor field effect transistors |
US4441931A (en) * | 1981-10-28 | 1984-04-10 | Bell Telephone Laboratories, Incorporated | Method of making self-aligned guard regions for semiconductor device elements |
-
1982
- 1982-09-16 JP JP57159611A patent/JPS5950567A/ja active Granted
-
1983
- 1983-09-09 KR KR1019830004240A patent/KR920002090B1/ko not_active IP Right Cessation
- 1983-09-13 US US06/531,709 patent/US4546540A/en not_active Expired - Fee Related
- 1983-09-14 CA CA000436664A patent/CA1205922A/en not_active Expired
- 1983-09-15 DE DE8383109138T patent/DE3379296D1/de not_active Expired
- 1983-09-15 EP EP83109138A patent/EP0106174B1/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
US4546540A (en) | 1985-10-15 |
EP0106174B1 (en) | 1989-03-01 |
JPS5950567A (ja) | 1984-03-23 |
CA1205922A (en) | 1986-06-10 |
EP0106174A2 (en) | 1984-04-25 |
DE3379296D1 (en) | 1989-04-06 |
JPH0354464B2 (ko) | 1991-08-20 |
EP0106174A3 (en) | 1986-07-23 |
KR920002090B1 (ko) | 1992-03-10 |
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