KR970072205A - 에스. 오. 아이(soi)형 트랜지스터 및 그 제조방법 - Google Patents

에스. 오. 아이(soi)형 트랜지스터 및 그 제조방법 Download PDF

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KR970072205A
KR970072205A KR1019960010604A KR19960010604A KR970072205A KR 970072205 A KR970072205 A KR 970072205A KR 1019960010604 A KR1019960010604 A KR 1019960010604A KR 19960010604 A KR19960010604 A KR 19960010604A KR 970072205 A KR970072205 A KR 970072205A
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insulating film
conductive layer
transistor
semiconductor substrate
entire surface
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KR1019960010604A
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KR0176202B1 (ko
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유선일
강우탁
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김광호
삼성전자 주식회사
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Priority to KR1019960010604A priority Critical patent/KR0176202B1/ko
Priority to US08/835,605 priority patent/US5877046A/en
Priority to JP09061397A priority patent/JP3854363B2/ja
Publication of KR970072205A publication Critical patent/KR970072205A/ko
Priority to US09/192,125 priority patent/US6130457A/en
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Publication of KR0176202B1 publication Critical patent/KR0176202B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76272—Vertical isolation by lateral overgrowth techniques, i.e. ELO techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Abstract

본 발명은 에스.오.아이(SOI)형 트랜지스터 및 그 제조방법에 관해 개시한다. 본 발명에 의한 SOI형 트랜지스터는 웨이퍼 상에 형성된 절연막 및 상기 절연막 상에 트랜지스터와 같은 반도체소자가 직접 형성되는 도전층을 구비하는 SOI형 트랜지스터에 있어서, 상기 도전층의 반도체소자가 형성되는 부분, 즉 활성영역의 채널 영역이 고 농도의 도전성불순물이 도핑된 다른 도전층과 접촉된 것을 특징으로 한다.
본 발명에 의한 트랜지스터를 사용하면, 상기 트랜지스터의 소오스 영역으로 홀 이동이 쉬워 채널영역에 지나치게 많은 홀이 축적되지 않으므로 상기 트랜지스터의 문턱전압의 변동이 거의 없다. 따라서 트랜지스터의 FBE를 감소시킬 수 있다. 상기 도전층은 고 농도 불순물이 도핑되어 있으므로 사이 소오스와 드레인간의 펀치쓰루의 스톱퍼역할을 할 수 있다. 따라서 트랜지스터의 SCE를 개선시킬 수 있다.

Description

에스. 오. 아이(SOI)형 트랜지스터 및 그 제조장법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5도는 본 발명에 의한 SOI형 트랜지스터의 단면도이다.

Claims (4)

  1. 제2반도체기판; 상기 제2반도체기판 전면에 형성된 제2절연막; 상기 제2절연막 전면에 형성된 전체면중 일부분에 단차를 갖는 고농도의 불순물이 도핑된 도전층; 상기 도전층의 단차의 높은 부분과 동일한 높이로 상기 단차의 낮은 부분을 채운 제1절연막; 상기 제1절연막과 도전층으로 이루어지는 표면상에 형성된 상기 제1절연막 상에 형성된 필드산화막과 상기 제1절연막 및 도전층의 일부면과 접하는 채널영역 그리고 상기 채널영역을 중심으로 상기 제1절연막 및 제1도전층의 일부 또는 상기 제2절연막과 접하는 소오스영역 및 드레인 영역으로 구분되는 제1반도체기판; 및 상기 채널영역의 상에 형성된 게이트전극을 구비하는 것을 특징으로 SOI형 트랜지스터.
  2. 제1반도체 기판 상에 일정간격 이격된 제1절연막을 형성하는 단계; 상기 제1절연막사이와 상기 제1절연막 전면에 제1도전층을 형성하는 단계; 상기 제1도전층 전면에 제2절연막을 형성하는 단계; 상기 제2절연막 전면에 제2반도체 기판을 형성하는 단계; 상기 제1반도체 기판 전면을 일정두께 제거하는 단계; 및 상기 제1반도체 기판에 상기 제1도전층의 일부먼과 제1절연막의 일부면에 채널영역이 접촉되는 트랜지스터를 형성하는 단계를 포함하는 것을 특징으로 하는 SOI형 트랜지스터 제조방법.
  3. 제2항에 있어서, 상기 제1반도체 기판 전면을 일정두께 제거하는 수단으로 CMP방법을 이용하는 것을 특징으로 하는 SOI형 트랜지스터 제조방법.
  4. 제2항 또는 제3항에 있어서, 상기 제1절연막 또는 제2절연막은 산화막으로 형성하는 것을 특징으로 하는 SOI형 트랜지스터 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019960010604A 1996-04-09 1996-04-09 에스.오.아이형 트랜지스터 및 그 제조방법 KR0176202B1 (ko)

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Application Number Priority Date Filing Date Title
KR1019960010604A KR0176202B1 (ko) 1996-04-09 1996-04-09 에스.오.아이형 트랜지스터 및 그 제조방법
US08/835,605 US5877046A (en) 1996-04-09 1997-04-09 Methods of forming semiconductor-on-insulator substrates
JP09061397A JP3854363B2 (ja) 1996-04-09 1997-04-09 Ｓｏｉトランジスタの製造方法
US09/192,125 US6130457A (en) 1996-04-09 1998-11-13 Semiconductor-on-insulator devices having insulating layers therein with self-aligned openings

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KR1019960010604A KR0176202B1 (ko) 1996-04-09 1996-04-09 에스.오.아이형 트랜지스터 및 그 제조방법

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KR970072205A true KR970072205A (ko) 1997-11-07
KR0176202B1 KR0176202B1 (ko) 1999-04-15

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