KR940019013A - 고전압 트랜지스터 - Google Patents

고전압 트랜지스터 Download PDF

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KR940019013A
KR940019013A KR1019940000009A KR19940000009A KR940019013A KR 940019013 A KR940019013 A KR 940019013A KR 1019940000009 A KR1019940000009 A KR 1019940000009A KR 19940000009 A KR19940000009 A KR 19940000009A KR 940019013 A KR940019013 A KR 940019013A
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말리 새트윈더
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윌리엄 이. 힐러
텍사스 인스트루먼츠 인코포레이티드
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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Abstract

고전압 트랜지스터는 소스와 채널이 형성되는 반도체 온 절연체(SOI) 영역을 포함한다. 드레인 드리프트 영역은 SOI영역 및 벌크 실리콘 영역내에 SOI를 지나 부분적으로 형성되고, 게이트는 상기 SOI채널에 결합된다.

Description

고전압 트랜지스터
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 웨이퍼의 제1제조 단계를 도시한 단면도, 제2도는 웨이퍼의 다음 제조 단계를 도시한 단면도, 제3도는 웨이퍼의 그 다음 제조 단계를 도시한 단면도, 제6도는 본 발명의 양호한 실시예를 도시한 단면도.

Claims (16)

  1. 고전압 트랜지스터에 있어서, 반도체 온 절연체(SOI) 영역, 상기 SOI 영역 내에 형성된 소스, 상기 SOI영역 내에 부분적으로 형성되고 SOI 영역을 지나 벌크 실리콘 내에 부분적으로 형성된 드레인 드리프트 영역, 상기 벌크 실리콘 상의 상기 드레인 드리프트 영역 내에 형성된 드레인 영역, 상기 소스 영역과 드레인 드리프트 영역 사이의 SOI영역 내에 형성된 채널, 및 상기 SOI채널에 결합된 게이트를 포함하는 것을 특징으로 하는 고전압 트랜지스터.
  2. 제1항에 있어서, 상기 SOI영역이 선정된 깊이로 형성된 선정된 전장의 매몰된 산화물 층을 포함하는 것을 특징으로 하는 고전압 트랜지스터.
  3. 제2항에 있어서, 상기 벌크 반도체 드레인 드리프트 영역은 상기 매몰된 산화물 층의 상기 선정된 깊이보다 더 깊게 연장하는 것을 특징으로 하는 고전압 트랜지스터.
  4. 제1항에 있어서, 상기 소스가 상기 SOI영역 내의 P-형 채널 내에 형성되는 것을 특징으로 하는 고전압 트랜지스터.
  5. 제4항에 있어서, 상기 게이트가 상기 P-형 채널 상에 배치된 산화물 층, 및 상기 게이트 산화물 층 상에 배치된 n+도우프되고, 패턴화된 폴리실리콘 층을 포함하는 것을 특징으로 하는 고전압 트랜지스터.
  6. 제5항에 있어서, 상기 드레인 영역에서 상기 게이트 산화물 층까지 연장하는 필드 산화물 층을 더 포함하는 것을 특징으로 하는 고전압 트랜지스터.
  7. 제4항에 있어서, 상기 SOI영역 내에 형성되고 상기 n+도우프된 소스 영역에 인접한 p+도우프된 소스 영역을 더 포함하는 것을 특징으로 하는 고전압 트랜지스터.
  8. 고전력 고측 구동기 트랜지스터에 있어서, 반도체 기판 내에 형성된 반도체온 절연체(SOI) 영역, 상기 SOI영역 내에 형성된 소스 영역, 상기 SOI영역 내에 형성된 채널, 상기 SOI영역 외부의 상기 반도체 기판 내에 형성된 드레인 영역 및 드레인 드리프트 영역의 일부분, 및 상기 SOI채널에 결합된 게이트를 포함하는 것을 특징으로 하는 고전력 고측 구동기 트랜지스터.
  9. 제8항에 있어서, 상기 SOI채널이 단결정 실리콘인 것을 특징으로 하는 고전력 고측 구동기 트랜지스터.
  10. 제9항에 있어서, 상기 SOI영역내의 p+도우프된 영역을 더 포함하는 것을 특징으로 하는 고전력 고측 구동기 트랜지스터.
  11. 제8항에 있어서, 상기 드레인 드리프트 영역이 상기 게이트 하부에 배치되고, 상기 SOI영역까지 부분적으로 연장하는 것을 특징으로 하는 고전력 고측 구동기 트랜지스터.
  12. 제8항에 있어서, 상기 SOI채널 및 상기 드레인 드리프트 영역상에 배치된 제1절연층, 상기 제1절연층을 상기 SOI 채널 상에 배치하는 패턴 다결정 실리콘 게이트, 상기 다결정 실리콘 게이트 상에 배치된 제2절연층, 및 상기 제2절연층 상에 선택적으로 배치되고, 소스 및 드레인 영역상에 있는 패턴된 도전층을 더 포함하는 것을 특징으로 하는 고전력 고측 구동기 트랜지스터.
  13. 고전압 트랜지스터의 제조방법에 있어서, 반도체 온 절연체(SOI) 영역을 형성하는 단계, 상기 SOI영역으로 연장하는 드레인 드리프트 영역을 기판내에 형성하는 단계, 소스 영역을 상기 SOI영역 내에 형성하는 단계, 및 상기 SOI 영역 상에 상기 소스 영역과 드레인 드리프트 영역 사이에 게이트를 형성하는 단계를 포함하는 것을 특징으로 하는 고전압 트랜지스터 제조 방법.
  14. 제13항에 있어서, 상기 드레인 드리프트 영역상에 필드 산화물 층을 형성하는 단계, 및 상기 필드 산화물층에 결합된 상기 SOI영역 상에 게이트 산화물 층을 형성하고 SOI채널을 형성하는 단계를 포함하는 것을 특징으로 하는 고전압 트랜지스터 제조 방법.
  15. 제14항에 있어서, 상기 SOI영역 형성 단계가 선정된 깊이에서 단결정 반도체 내의 선정된 전장의 절연층을 형성하는 단계를 포함하는 것을 특징으로 하는 고전압 트랜지스터 제조 방법.
  16. 제15항에 있어서, 상기 드레인 드리프트 영역을 형성하는 단계가 상기 SOI영역의 선정된 깊이까지 후속적으로 연장하여 SOI 채널들 사이 및 상기 드레인 영역을 지나 확장하도록 상기 드레인 드리프트 영역을 형성하는 단계를 포함하는 것을 특징으로 하는 고전압 트랜지스터 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940000009A 1993-01-04 1994-01-03 고전압트랜지스터 KR100325559B1 (ko)

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US31793A 1993-01-04 1993-01-04
US08/000,317 1993-01-04

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KR100325559B1 KR100325559B1 (ko) 2002-07-27

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100436291B1 (ko) * 1999-11-09 2004-06-16 주식회사 하이닉스반도체 반도체 소자의 트랜지스터 제조방법

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US5382818A (en) * 1993-12-08 1995-01-17 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a buried diode
US6198136B1 (en) * 1996-03-19 2001-03-06 International Business Machines Corporation Support chips for buffer circuits
US5710451A (en) * 1996-04-10 1998-01-20 Philips Electronics North America Corporation High-voltage lateral MOSFET SOI device having a semiconductor linkup region
JP3638377B2 (ja) * 1996-06-07 2005-04-13 株式会社ルネサステクノロジ 半導体装置
US6093592A (en) * 1996-06-12 2000-07-25 Matsushita Electric Industrial Co., Ltd. Method of manufacturing a semiconductor apparatus having a silicon-on-insulator structure
US5854113A (en) * 1996-11-01 1998-12-29 Electronics And Telecommunications Research Institute Method for fabricating power transistor using silicon-on-insulator (SOI) wafer
US5894152A (en) * 1997-06-18 1999-04-13 International Business Machines Corporation SOI/bulk hybrid substrate and method of forming the same
JP3315356B2 (ja) 1997-10-15 2002-08-19 株式会社東芝 高耐圧半導体装置
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