CN114429954A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN114429954A
CN114429954A CN202011177946.7A CN202011177946A CN114429954A CN 114429954 A CN114429954 A CN 114429954A CN 202011177946 A CN202011177946 A CN 202011177946A CN 114429954 A CN114429954 A CN 114429954A
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substrate
oxygen
buried oxide
oxide layer
semiconductor device
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黄圣尧
陈昱瑞
蔡仁杰
林毓翔
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN202011177946.7A priority Critical patent/CN114429954A/zh
Priority to US17/109,153 priority patent/US11626515B2/en
Publication of CN114429954A publication Critical patent/CN114429954A/zh
Priority to US18/116,826 priority patent/US12040396B2/en
Priority to US18/736,560 priority patent/US20240322036A1/en
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Abstract

本发明公开一种半导体元件，包括一基底、一埋入氧化层位于该基底中，该埋入氧化层邻近该基底的一表面、一栅极介电层位于该基底上并且覆盖该埋入氧化层、一栅极结构位于该栅极介电层上，并且重叠该埋入氧化层，以及一源极区及一漏极区分别位于该栅极结构两侧的该基底中。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种半导体元件及其制作方法，特别是涉及一种包括埋入氧化层的半导体元件及其制作方法。
背景技术
先进半导体技术中，可将具有不同驱动电压的半导体元件制作在同一个芯片中，以降低生产成本、增加效能及降低功耗，满足各种产品的需求。
高压元件通常会具有厚度较厚的栅极介电层，以承受较高的操作电压。然而，较厚的栅极介电层会造成高压元件的栅极高度不同于其他元件，提高了制作工艺控制的困难。因此，本领域仍需一种改良的半导体元件及其制作方法，可成功地整合制作这些半导体元件。
发明内容
为达上述目的，本发明提供了一种半导体元件及其制作方法，其选择性地于高压元件区域利用氧注入制作工艺于基底中形成一埋入氧化层作为栅极介电层，不仅可简化制作步骤，还可使不同晶体管之间具有较一致的栅极高度，提高了制作工艺余裕度(processwindow)。
根据本发明一实施例提供的一种半导体元件，包括一基底、一埋入氧化层位于该基底中，该埋入氧化层邻近该基底的一表面、一栅极介电层位于该基底上并且覆盖该埋入氧化层、一栅极结构位于该栅极介电层上，并且重叠该埋入氧化层，以及一源极区及一漏极区分别位于该栅极结构两侧的该基底中。
根据本发明一实施例提供的一种制作半导体元件的方法，步骤包括提供一基底、对该基底进行一氧注入制作工艺，以于该基底的一表面形成一富氧层、进行一快速热处理制作工艺，以将该富氧层转化成一埋入氧化层、形成一栅极介电层位于该基底上并且覆盖该埋入氧化层，以及形成一栅极结构位于该栅极介电层上，并且重叠该埋入氧化层。
附图说明
图1至图9为本发明一实施例的半导体元件的制作方法的步骤剖面示意图，其中:
图1为提供用于制作半导体元件的基底的示意图；
图2为在半导体元件的基底中形成绝缘结构的示意图；
图3为在半导体元件的基底中形成阱区的示意图；
图4为在半导体元件的基底中形成富氧层的示意图；
图5为在半导体元件的基底中形成埋入氧化层的示意图；
图6为在半导体元件的基底上形成栅极介电层的示意图；
图7为移除部分半导体元件的栅极介电层的示意图；
图8为在半导体元件的基底上形成另一栅极介电层的示意图；以及
图9为在半导体元件的基底上形成栅极结构以及在基底中形成源极区、漏极区、漂移区、阱区拾起掺杂区的示意图。
图10为本发明一实施例的包括金属栅极结构的半导体元件的剖面示意图。
主要元件符号说明
100 基底
102 绝缘结构
110 第一阱区
120 第二阱区
130 第三阱区
140 第四阱区
200 第一图案化掩模层
205 含氧物质
210 富氧层
220 埋入氧化层
222 薄层
230 栅极介电层
240 第二图案化掩模层
250 栅极介电层
310 第一半导体元件
311 栅极结构
312 间隙壁
313 源极区
314 漏极区
320 第二半导体元件
321 栅极结构
322 间隙壁
323 源极区
324 漏极区
325 漂移区
326 阱区拾起掺杂区
330 第三半导体元件
331 栅极结构
332 间隙壁
333 源极区
334 漏极区
340 第四半导体元件
341 栅极结构
342 间隙壁
343 源极区
344 漏极区
410 第一半导体元件
411 低阻值金属层
412 功函数金属层
420 第二半导体元件
421 低阻值金属层
422 功函数金属层
430 第三半导体元件
431 低阻值金属层
432 功函数金属层
440 第四半导体元件
441 低阻值金属层
442 功函数金属层
500 层间介电层
100a 表面
100b 表面
100c 表面
220a 表面
220b 下缘
220c 侧缘
313a 侧缘
325a 下缘
D1 深度
P1 离子注入制作工艺
P2 氧注入制作工艺
P3 快速热处理制作工艺
P4 热氧化制作工艺
P4-1 蚀刻制作工艺
P5 热氧化制作工艺
R1 第一元件区
R2 第二元件区
R3 第三元件区
R4 第四元件区
具体实施方式
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施例并配合所附的附图作详细说明。所附的附图均为示意图，并未按比例绘制，且相同或类似的特征通常以相同的附图标记描述。文中所述实施例与附图仅供参考与说明用，并非用来对本发明加以限制。本发明涵盖的范围由权利要求界定。与本发明权利要求具同等意义者，也应属本发明涵盖的范围。
图1至图10为根据本发明一实施例的半导体元件的制作方法的步骤剖面示意图。
请参考图1。首先提供一基底100。基底100例如是硅基底、外延硅基底、硅锗半导体基底、碳化硅基底或硅覆绝缘(SOI)基底等，但不限于此。基底100具有一表面100a。
请参考图2。接着在基底100上形成绝缘结构102，定义出第一元件区R1、第二元件区R2、第三元件区R3及第四元件区R4，分别用于制作不同驱动电压的半导体元件。需特别说明的是，图中将第一元件区R1、第二元件区R2、第三元件区R3及第四元件区R4绘示为相邻设置，是以便于绘图及说明为目的，并不用于限制本发明。第一元件区R1、第二元件区R2、第三元件区R3及第四元件区R4于基底100的位置可根据设计需求调整。
请参考图3。接着，对基底100进行一次或多次的离子注入制作工艺P1，以分别在第一元件区R1、第二元件区R2、第三元件区R3及第四元件区R4中形成第一阱区110，第二阱区120，第三阱区130和第四阱区140。第一阱区110，第二阱区120，第三阱区130和第四阱区140可具有相同或不同的导电型，例如可分别是N型阱区或P型阱区，并且可具有相同或不同的掺杂种类、掺杂浓度及掺杂深度，视元件设计调整。
请参考图4。接着，形成一第一图案化掩模层200于基底100上并覆盖住基底100部分区域。第一图案化掩模层200例如是一图案化光阻层，但不限于此。根据本发明一实施例，第一图案化掩模层200覆盖住第三元件区R3及第四元件区R4的全部区域，并暴露出第一元件区R1的全部区域及第二元件区R2的部分区域。
请继续参考图4。接着，以第一图案化掩模层200为掩模对基底100进行一氧注入制作工艺P2，将含氧物质(oxygen-containing species)205注入自第一图案化掩模层200显露出来的第一元件区R1和第二元件区R2中，分别在第一元件区R1和第二元件区R2中形成包括含氧物质205的富氧层(oxygen-rich layer)210。
根据本发明一些实施例，含氧物质205可包括氧原子、氧离子、氧自由基、含氧化合物，或前述的组合，但不限于此。
根据本发明一些实施例，富氧层210所包含的含氧物质205的注入剂量可介于1E15和1E16 atoms/cm3之间，注入能量介于10和30keV之间，但不限于此。根据本发明一些实施例，富氧层210底部位于基底100表面100a之下的深度D1可达
Figure BDA0002749234630000061
至
Figure BDA0002749234630000062
之间。
根据本发明一些实施例，由于含氧物质205会穿过基底100的部分厚度而注入至富氧层210预定范围内，因此富氧层210上会被一薄层222覆盖。薄层222的表面即基底100的表面100a。薄层222的含氧物质205浓度会明显小于富氧层210的含氧物质205浓度，例如薄层222中可仅包括少量的含氧物质205，或者几乎不包括含氧物质205，而与基底100具有大致上相同的成分，例如硅。
请参考图5。移除第一图案化掩模层200后，接着在惰性气体环境下进行一快速热处理制作工艺P3，使富氧层210中的含氧物质205与基底100的材料反应，将富氧层210转化成一埋入氧化层220。惰性气体环境可通过将惰性气体，例如氮气(N2)或氩气(Ar)，通入快速热处理制作工艺P3的制作工艺腔中而实现。
根据本发明一些实施例，快速热处理制作工艺P3的制作工艺温度可介于850℃至1050℃之间，制作工艺时间可介于1分钟至5分钟之间，但不限于此。根据本发明一些实施例，快速热处理制作工艺P3可同时活化第一阱区110，第二阱区120，第三阱区130和第四阱区140的掺杂并修补基底100在离子注入制作工艺P1和氧注入制作工艺P2中受到的损坏。
根据本发明一些实施例，由于薄层222仅包括少量含氧物质205，或者几乎不包括含氧物质205，因此薄层222在快速热处理制作工艺P3中仅极少部分或者几乎不会转化成氧化物，因此快速热处理制作工艺P3后仍存在薄层222覆盖在埋入氧化层220上。
根据本发明一些实施例，快速热处理制作工艺P3之后，埋入氧化层220中仍可包括部分未反应的含氧物质205。
请参考图6。接着，在一含氧环境下进行一热氧化制作工艺P4，以在第一元件区R1、第二元件区R2、第三元件区R3及第四元件区R4形成栅极介电层230。栅极介电层230位于基底100表面100b上并覆盖住埋入氧化层220的表面220a。
含氧环境可通过将氧气或含氧气体(例如水气)通入热氧化制作工艺P4的制作工艺腔中而实现。根据本发明一实施例，热氧化制作工艺P4可包括现场蒸气产生(in-situsteam generation,ISSG)氧化制作工艺、湿式炉管氧化制作工艺，或干式炉管氧化制作工艺，但不限于此。
值得注意的是，第一元件区R1和第二元件区R2覆盖在埋入氧化层220上的薄层222及第三元件区R3和第四元件区R4的基底100的表层会在热氧化制作工艺P4中被氧化而成为栅极介电层230的一部分。因此热氧化制作工艺P4之后，栅极介电层230与基底100的交界面即基底100的表面100b，会大致上齐平或略低于热氧化制作工艺P4的前表面100a。在一些实施例中，基底100的表面100b与埋入氧化层220的表面220a大致上齐平。
请参考图7。接着，形成第二图案化掩模层240于基底100上并覆盖住基底100部分区域。第二图案化掩模层240例如是一图案化光阻层，但不限于此。根据本发明一实施例，第二图案化掩模层240覆盖住第一元件区R1及第三元件区R3的全部区域，暴露出第四元件区R4的全部区域及第二元件区R2的部分区域。
请继续参考图7。接着，以第二图案化掩模层240为掩模进行一蚀刻制作工艺P4-1，蚀刻移除栅极介电层230自第二图案化掩模层240显露出来的部分，显露出第四元件区R4的基底100表面110b及部分第二元件区R2的基底100表面110b。
请参考图8。移除第二图案化掩模层240后，接着在一含氧环境下进行另一热氧化制作工艺P5，以在第四元件区R4和第二元件区R2基底100显露出来的部分上形成栅极介电层250。如图8所示，栅极介电层250位于基底100表面100c上并邻接栅极介电层230。根据本发明一实施例，热氧化制作工艺P5可包括现场蒸气产生(in-situ steam generation,ISSG)氧化制作工艺、湿式炉管氧化制作工艺，或干式炉管氧化制作工艺，但不限于此。
值得注意的是，自栅极介电层230显露出来的基底100的表层会在热氧化制作工艺P5中被氧化而成为栅极介电层250的一部分，因此热氧化制作工艺P5后，栅极介电层250与基底100的交界面即基底100的表面100c，会大致上齐平或略低于基底100的表面100b。
在一些实施例中，栅极介电层230和栅极介电层250可具有不同厚度。例如在一些实施例中，栅极介电层230的厚度可介于30至50纳米，栅极介电层240的厚度可介于10至15纳米，但不限于此。
请参考图9。接着，利用例如薄膜沉积、光刻、蚀刻、离子注入等半导体制作工艺，分别于第一元件区R1、第二元件区R2、第三元件区R3及第四元件区R4中形成第一半导体元件310、第二半导体元件320、第三半导体元件330和第四半导体元件340。
详细来说，如图9所示，位于第一元件区R1的第一半导体元件310包括基底100，形成在基底100中并且邻近基底100表面的埋入氧化层220，栅极介电层230位于基底100上并且覆盖住埋入氧化层220。栅极结构311位于栅极介电层230上并且与埋入氧化层220在垂直方向上重叠。间隙壁312设置在栅极结构311的侧壁上。具有相同导电型的源极区313及漏极区314分别位于栅极结构311两侧的基底100中，且埋入氧化层220与漏极区313的一侧缘313a及源极区314的一侧缘314a接触。在一些实施例中，埋入氧化层220、源极区313及漏极区314是位于基底100的第一阱区110中。第一阱区110具有不同于源极区313及漏极区314的导电型。第一半导体元件310可用作中压(medium voltage,MV)元件，可于例如10V至250V的操作电压下运作。
位于第二元件区R2的第二半导体元件320包括基底100以及形成在基底100中并且邻近基底100表面的埋入氧化层220。栅极介电层230和栅极介电层250位于基底100上，其中栅极介电层230(第一部分)直接覆盖在埋入氧化层220上，栅极介电层250(第二部分)直接覆盖在基底100上。栅极结构321位于栅极介电层230和栅极介电层250上，重叠基底100与埋入氧化层220之间的一交界220c。栅极结构321也重叠栅极介电层230和栅极介电层250的交界。间隙壁322设置在栅极结构311的侧壁上。具有相同导电型的源极区323及漏极区324分别位于该栅极两侧的基底100中。漂移区325位于基底100中，介于栅极结构321与漏极区324之间，包围住漏极区324以及部分埋入氧化层220的下缘220b，即漂移区325的下缘325a会低于埋入氧化层220的下缘220b。漂移区325具有与源极区323及漏极区324相同的导电型。第二半导体元件320的埋入氧化层220的侧缘220c与源极区323及漏极区324被基底100和漂移区325区隔开，不直接接触。在一些实施例中，埋入氧化层220、源极区323、漏极区324和漂移区325是位于基底100的第二阱区120中。第二阱区120具有不同于源极区323、漏极区324和漂移区325的导电型。在一些实施例中，第二半导体元件320还包括一阱区拾起掺杂区326位于源极区323端的基底100中。阱区拾起掺杂区326与第二阱区120具有相同导电型。第二半导体元件320可用作高压(high voltage,HV)元件，可于例如40V至900V的操作电压下运作。
位于第三元件区R3的第三半导体元件330包括基底100，形成在基底100上的栅极介电层230，形成在栅极介电层230上的栅极结构331、形成在栅极结构331侧壁上的间隙壁332，以及形成在栅极结构331两侧的基底100中并且具有相同导电型的源极区333及漏极区334。在一些实施例中，第三半导体元件330的源极区333及漏极区334是位于基底100的第三阱区130中。第三阱区130具有不同于源极区333及漏极区334的导电型。第三半导体元件330可用作输入/输出(input/out-put,IO)元件，可于例如2.5V至3.3V的操作电压下运作。
位于第四元件区R4的第四半导体元件340包括基底100，形成在基底100上的栅极介电层250，形成在栅极介电层250上的栅极结构341、形成在栅极结构341侧壁上的间隙壁342，以及形成在栅极结构341两侧的基底100中并且具有相同导电型的源极区343及漏极区344。在一些实施例中，第四半导体元件340的源极区343及漏极区344是位于基底100的第四阱区140中。第四阱区140具有不同于源极区343及漏极区344的导电型。第四半导体元件340可用作核心元件(core device)，可于例如0.8V至1.2V的操作电压下运作。
本发明通过氧注入制作工艺在第一半导体元件310和第二半导体元件320的基底100中形成埋入氧化层320，可提高第一半导体元件310和第二半导体元件320的有效栅极介电层厚度，因此可提高第一半导体元件310和第二半导体元件320的崩溃电压，可在较高的操作电压下运作。
请参考图10，为根据本发明一实施例的半导体元件的剖面示意图。图10不同于图9的实施例之处在于，图10的第一半导体元件410、第二半导体元件420、第三半导体元件430和第四半导体元件440包括金属栅极结构。
详细来说，可在图9的步骤后，接着在基底100上全面性地沉积层间介电层500，然后对层间介电层500进行研磨移除制作工艺直到显露出第一栅极结构311、第二栅极结构321、第三栅极结构331和第四栅极341的顶部。接着，进行置换金属栅极(replacementmetal gate)制作工艺，包括先进行选择性蚀刻(例如湿蚀刻)移除第一栅极结构311、第二栅极结构321、第三栅极结构331和第四栅极341，在层间介电层500中形成多个栅极沟槽，然后在栅极沟槽内依序填入高介电常数介电层(图未示)、功函数金属层412、422、432、442以及低阻值金属层411、432、431、441，再进行化学机械研磨(CMP)制作工艺移除栅极沟槽外多余的高介电常数介电层、功函数金属层412、422、432、442，以及低阻值金属层411、432、431、441，获得如图10所示结构。
本发明通过氧注入制作工艺在第一半导体元件310和第二半导体元件320的基底100中形成埋入氧化层320来提高第一半导体元件310和第二半导体元件320的有效栅极介电层厚度，相较于现有以热氧化方式形成较厚的栅极介电层，本发明可使第一半导体元件310的栅极结构311、第二半导体元件320的栅极结构321、第三半导体元件330的栅极结构331以及第四半导体元件340的栅极结构341具有较一致的高度，可提高上述置换金属栅极制作工艺的制作工艺余裕度。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (21)

1.一种半导体元件，其特征在于，包括
基底；
埋入氧化层，位于该基底中，该埋入氧化层邻近该基底的表面；
栅极介电层，位于该基底上并且覆盖该埋入氧化层；
栅极结构，位于该栅极介电层上，并且重叠该埋入氧化层；以及
源极区及漏极区，分别位于该栅极结构两侧的该基底中。
2.如权利要求1所述的半导体元件，另包括漂移区，位于该基底中并且介于该栅极结构与该漏极区之间，其中该漂移区的下缘低于该埋入氧化层的下缘。
3.如权利要求2所述的半导体元件，其中该漂移区包围部分该埋入氧化层的该下缘。
4.如权利要求2所述的半导体元件，其中该源极区、该漏极区及该漂移区具有第一导电型，该基底具有第二导电型。
5.如权利要求1所述的半导体元件，其中该埋入氧化层的表面与该基底的该表面齐平。
6.如权利要求1所述的半导体元件，其中该栅极结构重叠该基底与该埋入氧化层之间的交界。
7.如权利要求1所述的半导体元件，其中该栅极介电层包括直接覆盖在该埋入氧化层上的第一部分，以及直接覆盖在该基底上的第二部分。
8.如权利要求7所述的半导体元件，其中该第一部分的厚度大于该第二部分的厚度。
9.如权利要求7所述的半导体元件，其中该第一部分及该第二部分之间的交界与该基底及该埋入氧化层之间的交界在垂直方向上对齐。
10.如权利要求1所述的半导体元件，其中该埋入氧化层接触该漏极区的侧缘以及该源极区的侧缘。
11.如权利要求1所述的半导体元件，其中该埋入氧化层包括注入的含氧物质。
12.一种制作半导体元件的方法，包括:
提供基底；
对该基底进行氧注入制作工艺，以于该基底的表面形成富氧层；
进行快速热处理制作工艺，以将该富氧层转化成一埋入氧化层；
形成栅极介电层位于该基底上并且覆盖该埋入氧化层；以及
形成栅极结构位于该栅极介电层上，并且重叠该埋入氧化层。
13.如权利要求12所述的方法，其中该氧注入制作工艺包括将含氧物质(oxygen-containing species)，注入该基底中以形成该富氧层，其中该含氧物质包括氧原子、氧离子、氧自由基、含氧化合物的其中至少一种。
14.如权利要求13所述的方法，其中该含氧物质的总注入剂量介于1E15和1E16 atoms/cm3之间。
15.如权利要求13所述的方法，其中该含氧物质的注入能量介于10和30keV之间。
16.如权利要求13所述的方法，其中该快速热处理制作工艺是在惰性气体环境下进行。
17.如权利要求13所述的方法，其中该快速热处理制作工艺的温度介于850和1050℃之间。
18.如权利要求13所述的方法，其中该快速热处理制作工艺的时间介于1到5分钟之间。
19.如权利要求13所述的方法，其中该栅极介电层是通过在含氧环境下进行热氧化制作工艺形成。
20.如权利要求13所述的方法，另包括:
形成源极区及漏极区，分别位于该栅极两侧的该基底中；以及
形成漂移区，位于该基底中并且介于该栅极结构与该漏极区之间，其中该漂移区的下缘低于该埋入氧化层的下缘。
21.如权利要求13所述的方法，其中该栅极结构重叠该基底与该埋入氧化层之间的交界。
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