KR970054438A - 경사진 게이트 산화막을 갖는 전력용 모스 소자 및 그 제조 방법 - Google Patents

경사진 게이트 산화막을 갖는 전력용 모스 소자 및 그 제조 방법 Download PDF

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KR970054438A
KR970054438A KR1019950068625A KR19950068625A KR970054438A KR 970054438 A KR970054438 A KR 970054438A KR 1019950068625 A KR1019950068625 A KR 1019950068625A KR 19950068625 A KR19950068625 A KR 19950068625A KR 970054438 A KR970054438 A KR 970054438A
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South Korea
Prior art keywords
oxide film
gate oxide
source
contact
drain region
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KR1019950068625A
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English (en)
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KR100192973B1 (ko
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김한수
임필규
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김광호
삼성전자 주식회사
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Priority to KR1019950068625A priority Critical patent/KR100192973B1/ko
Publication of KR970054438A publication Critical patent/KR970054438A/ko
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Publication of KR100192973B1 publication Critical patent/KR100192973B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Abstract

본 발명은 문턱을 낮게 유지하면서 게이트 캐패시턴스를 줄일 수 있도록 게이트 산화막을 경사지게 형성한 전력용 모스(MOS) 소자 및 그 제조방법에 관한 것으로서, 소스/드레인 영역이 형성된 반도체 기판 상부에 게이트 산화막을 형성함에 있어서, 게이트 절연막이 소스/드레인 영역에 접하는 곳은 얇게 형성되고 소스/드레인 영역이 접하는 곳으로부터 멀어질수록 두껍게 형성되어 경사 구조를 이루도록 한 데에 그 특징이 있는 것이다.

Description

경사진 게이트 산화막을 갖는 전력용 모스 소자 및 그 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명에 따른 전력용 모스 소자의 구조 단면도.

Claims (4)

  1. 소스/드레인 영역이 형성된 반도체 기판 상부에 게이트 산화막을 형성함에 있어서, 게이트 절연막이 소스/드레인 영역에 접하는 곳은 얇게 형성되고 소스/드레인 영역이 접하는 곳으로부터 멀어질수록 두껍게 형성되어 경사 구조를 이루도록 한 것을 특징으로 하는 경사진 게이트 산화막을 갖는 전력용 모스 소자.
  2. 소스/드레인 영역이 형성된 반도체 기판 상부에 게이트 산화막을 형성함에 있어서, 상기 기판 상부에 두꺼운 게이트 산화막을 형성하는 단계; 및 상기 게이트 절연막이 상기 소스/드레인 영역에 접하는 곳은 얇고 소스/드레인 영역이 접하는 곳으로부터 멀어질수록 두껍게 형성되도록 경사지게 식각하는 단계를 포함하여 이루어지는 경사진 게이트 산화막을 갖는 전력용 모스 소자의 제조 방법.
  3. 제2항에 있어서, 상기 게이트 산화막 형성 후 그 상부에 SOG를 성층하고 이를 습식 식각하여 SOG와 산화막의 식각 속도 차에 의해 산화막 상부를 경사지게 형성하는 것을 특징으로 하는 경사진 게이트 산화막을 갖는 전력용 모스 소자의 제조 방법.
  4. 제2항에 있어서, 상기 게이트 산화막 형성 후 소스/드레인 영역에 접하는 게이트 산화막 부분을 이온 주입으로 손상시킨 다음 식각하여 산화막 상부가 경사구조를 이루도록 한 것을 특징으로 하는 경사진 게이트 산화막을 갖는 전력용 모스 소자의 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950068625A 1995-12-30 1995-12-30 경사진 게이트 산화막을 갖는 전력용 모스 소자및그제조방법 KR100192973B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950068625A KR100192973B1 (ko) 1995-12-30 1995-12-30 경사진 게이트 산화막을 갖는 전력용 모스 소자및그제조방법

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Application Number Priority Date Filing Date Title
KR1019950068625A KR100192973B1 (ko) 1995-12-30 1995-12-30 경사진 게이트 산화막을 갖는 전력용 모스 소자및그제조방법

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KR970054438A true KR970054438A (ko) 1997-07-31
KR100192973B1 KR100192973B1 (ko) 1999-06-15

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100854078B1 (ko) * 2001-09-12 2008-08-25 페어차일드코리아반도체 주식회사 모스 게이트형 전력용 반도체소자 및 그 제조방법
CN111564495A (zh) * 2020-04-08 2020-08-21 中国科学院微电子研究所 双沟道mosfet、掩埋沟道晶体管及制造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6531410B2 (en) * 2001-02-27 2003-03-11 International Business Machines Corporation Intrinsic dual gate oxide MOSFET using a damascene gate process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100854078B1 (ko) * 2001-09-12 2008-08-25 페어차일드코리아반도체 주식회사 모스 게이트형 전력용 반도체소자 및 그 제조방법
CN111564495A (zh) * 2020-04-08 2020-08-21 中国科学院微电子研究所 双沟道mosfet、掩埋沟道晶体管及制造方法

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