KR910017635A - 메모리 셀 커패시터 제조방법 - Google Patents

메모리 셀 커패시터 제조방법 Download PDF

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Publication number
KR910017635A
KR910017635A KR1019900004419A KR900004419A KR910017635A KR 910017635 A KR910017635 A KR 910017635A KR 1019900004419 A KR1019900004419 A KR 1019900004419A KR 900004419 A KR900004419 A KR 900004419A KR 910017635 A KR910017635 A KR 910017635A
Authority
KR
South Korea
Prior art keywords
polysilicon
memory cell
cell capacitor
capacitor manufacturing
mos transistor
Prior art date
Application number
KR1019900004419A
Other languages
English (en)
Other versions
KR100215914B1 (ko
Inventor
전영권
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019900004419A priority Critical patent/KR100215914B1/ko
Publication of KR910017635A publication Critical patent/KR910017635A/ko
Application granted granted Critical
Publication of KR100215914B1 publication Critical patent/KR100215914B1/ko

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/036—Making the capacitor or connections thereto the capacitor extending under the transistor

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음

Description

메모리 셀 커패시터 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 2도는 본 발명 커패시터의 제조공정을 나타낸 단면도.

Claims (1)

  1. 기판(1)에 N+이온 주입으로 드레인/소오스 영역을 형성하고 게이트(3)와 필드 옥사이드(2)를 형성하 모스트랜지스터를 제조한 것에 있어서, 상기 모스트랜지스터위에 폴리실리콘(4)을 디포지션하고 마스팅 및 에칭작업으로 불필요한 부분을 제거한후 이 폴리실리콘(4)을 에칭하여 트렌치를 형성하고 트렌치가 형성된 폴리 실리콘(4)위에 폴리 실리콘(5), 절연층(6), 폴리실리콘(7)을 디포지션함을 특징으로하는 메모리 셀 커패시터 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900004419A 1990-03-31 1990-03-31 메모리셀커패시터 제조방법 KR100215914B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900004419A KR100215914B1 (ko) 1990-03-31 1990-03-31 메모리셀커패시터 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900004419A KR100215914B1 (ko) 1990-03-31 1990-03-31 메모리셀커패시터 제조방법

Publications (2)

Publication Number Publication Date
KR910017635A true KR910017635A (ko) 1991-11-05
KR100215914B1 KR100215914B1 (ko) 1999-08-16

Family

ID=19297559

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900004419A KR100215914B1 (ko) 1990-03-31 1990-03-31 메모리셀커패시터 제조방법

Country Status (1)

Country Link
KR (1) KR100215914B1 (ko)

Also Published As

Publication number Publication date
KR100215914B1 (ko) 1999-08-16

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