KR910017635A - 메모리 셀 커패시터 제조방법 - Google Patents
메모리 셀 커패시터 제조방법 Download PDFInfo
- Publication number
- KR910017635A KR910017635A KR1019900004419A KR900004419A KR910017635A KR 910017635 A KR910017635 A KR 910017635A KR 1019900004419 A KR1019900004419 A KR 1019900004419A KR 900004419 A KR900004419 A KR 900004419A KR 910017635 A KR910017635 A KR 910017635A
- Authority
- KR
- South Korea
- Prior art keywords
- polysilicon
- memory cell
- cell capacitor
- capacitor manufacturing
- mos transistor
- Prior art date
Links
- 239000003990 capacitor Substances 0.000 title claims description 3
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 5
- 229920005591 polysilicon Polymers 0.000 claims 5
- 238000000151 deposition Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/036—Making the capacitor or connections thereto the capacitor extending under the transistor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 2도는 본 발명 커패시터의 제조공정을 나타낸 단면도.
Claims (1)
- 기판(1)에 N+이온 주입으로 드레인/소오스 영역을 형성하고 게이트(3)와 필드 옥사이드(2)를 형성하 모스트랜지스터를 제조한 것에 있어서, 상기 모스트랜지스터위에 폴리실리콘(4)을 디포지션하고 마스팅 및 에칭작업으로 불필요한 부분을 제거한후 이 폴리실리콘(4)을 에칭하여 트렌치를 형성하고 트렌치가 형성된 폴리 실리콘(4)위에 폴리 실리콘(5), 절연층(6), 폴리실리콘(7)을 디포지션함을 특징으로하는 메모리 셀 커패시터 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900004419A KR100215914B1 (ko) | 1990-03-31 | 1990-03-31 | 메모리셀커패시터 제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900004419A KR100215914B1 (ko) | 1990-03-31 | 1990-03-31 | 메모리셀커패시터 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910017635A true KR910017635A (ko) | 1991-11-05 |
KR100215914B1 KR100215914B1 (ko) | 1999-08-16 |
Family
ID=19297559
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900004419A KR100215914B1 (ko) | 1990-03-31 | 1990-03-31 | 메모리셀커패시터 제조방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100215914B1 (ko) |
-
1990
- 1990-03-31 KR KR1019900004419A patent/KR100215914B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100215914B1 (ko) | 1999-08-16 |
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Legal Events
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A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application | ||
J201 | Request for trial against refusal decision | ||
J301 | Trial decision |
Free format text: TRIAL DECISION FOR APPEAL AGAINST DECISION TO DECLINE REFUSAL REQUESTED 19981002 Effective date: 19990318 |
|
S901 | Examination by remand of revocation | ||
GRNO | Decision to grant (after opposition) | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20050422 Year of fee payment: 7 |
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LAPS | Lapse due to unpaid annual fee |