KR910017684A - 메모리 셀 커패시터 제조방법 - Google Patents
메모리 셀 커패시터 제조방법 Download PDFInfo
- Publication number
- KR910017684A KR910017684A KR1019900004420A KR900004420A KR910017684A KR 910017684 A KR910017684 A KR 910017684A KR 1019900004420 A KR1019900004420 A KR 1019900004420A KR 900004420 A KR900004420 A KR 900004420A KR 910017684 A KR910017684 A KR 910017684A
- Authority
- KR
- South Korea
- Prior art keywords
- polysilicon
- insulating layer
- deposited
- memory cell
- cell capacitor
- Prior art date
Links
- 239000003990 capacitor Substances 0.000 title claims description 3
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 8
- 229920005591 polysilicon Polymers 0.000 claims 8
- 238000000151 deposition Methods 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 2
- 238000005468 ion implantation Methods 0.000 claims 1
- 230000000873 masking effect Effects 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 2도는 본 발명 커패시터의 제조공정을 나타낸 단면도.
Claims (1)
- 기판⑴에 N+이온주입으로 소오스/드레인 영역을 형성하고 게이트⑶, 필드 옥사이드⑵를 형성한 것에 있어서, 상기 필드 옥사이드⑵와 N+소오스/드레인 영역위에 폴리 실리콘⑸을 디포지션 하고 에칭하여 불필요 한 부분을 제거한 후 절연층⑹을 디포지션하며 상기 절연층⑸을 마스킹 및 에칭작업에 의해 선택적으로 제거하고 폴리 실리콘⑹을 디포지션한 후 다시 절연층⑺과 폴리 실리콘⑻을 디포지션하여 상기 절연층⑸/폴리실리콘⑹/절연층⑺/폴리 실리콘⑻의적층구조를 트렌치 에칭한 후 폴리 실리콘⑼을 디포지션하고 드라이 에칭하여 네크 웰을 형성하며 이어서 절연층⑸⑺을 제거한 후 폴리 실리콘⑽/절연층⑾/폴리 실리콘⑿을 차례로 디포지션 함을 특징으로 하는 메모리 셀 커패시터 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900004420A KR0156107B1 (ko) | 1990-03-31 | 1990-03-31 | 메모리 셀 커패시터 제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900004420A KR0156107B1 (ko) | 1990-03-31 | 1990-03-31 | 메모리 셀 커패시터 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910017684A true KR910017684A (ko) | 1991-11-05 |
KR0156107B1 KR0156107B1 (ko) | 1998-10-15 |
Family
ID=19297560
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900004420A KR0156107B1 (ko) | 1990-03-31 | 1990-03-31 | 메모리 셀 커패시터 제조방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0156107B1 (ko) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102402616B1 (ko) | 2017-05-26 | 2022-05-27 | 엘지이노텍 주식회사 | 렌즈 구동 장치, 및 이를 포함하는 카메라 모듈 및 광학 기기 |
-
1990
- 1990-03-31 KR KR1019900004420A patent/KR0156107B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0156107B1 (ko) | 1998-10-15 |
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