KR940001460A - 반도체 소자의 ldd 제조방법 - Google Patents

반도체 소자의 ldd 제조방법 Download PDF

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Publication number
KR940001460A
KR940001460A KR1019920010235A KR920010235A KR940001460A KR 940001460 A KR940001460 A KR 940001460A KR 1019920010235 A KR1019920010235 A KR 1019920010235A KR 920010235 A KR920010235 A KR 920010235A KR 940001460 A KR940001460 A KR 940001460A
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KR
South Korea
Prior art keywords
sidewall
semiconductor device
ions
gate
nitride film
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KR1019920010235A
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English (en)
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KR950002196B1 (ko
Inventor
구정석
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문정환
금성일렉트론주식회사
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Priority to KR1019920010235A priority Critical patent/KR950002196B1/ko
Priority to TW082102471A priority patent/TW234773B/zh
Priority to DE4318866A priority patent/DE4318866C2/de
Priority to JP16333193A priority patent/JP3394562B2/ja
Publication of KR940001460A publication Critical patent/KR940001460A/ko
Application granted granted Critical
Publication of KR950002196B1 publication Critical patent/KR950002196B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 공정을 단순화시켜 정션 커패시턴스를 최소화 시키기에 적당하도록 한 반도체 소자의 LDD제조방법에 관한 것으로 기판(21)의 액티브 영역상에 게이트를 형성하는 공정과, 상기 게이트 측면에 측벽을 형성하고 N+이온을 주입하는 공정과, 산화막(27)을 형성하는 공정과, 측벽을 제거하고 N-,P-이온을 주입하는 공정을 차례로 실시하여서 이루어진다.

Description

반도체 소자의 LDD 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 LDD 제조 공정 단면도.
제3도는 본 발명의 다른 실시예를 나타낸 공정 단면도.

Claims (4)

  1. 기판(21)의 액티브 영역상에 게이트를 형성하는 공정과, 상기 게이트측면에 측벽을 형성하고 N+이온을 주입하는 공정과, 산화를 실시하여 상기 측벽을 제외한 전표면에 산화막(27)을 형성하는 공정과, 상기 측벽을 제거하고, N-,P-이온을 주입하는 공정을 차례로 실시하여서 이루어짐을 특징으로 하는 반도체 소자의 LDD제조방법.
  2. 제 1항에 있어서, P-이온은 게이트에 인접한 측벽 밑부분에만 형성됨을 특징으로 하는 반도체 소자의 LDD제조방법.
  3. 제 1항에 있어서, 측벽은 질화막(25)으로 형성됨을 특징으로 하는 반도체 소자의 LDD제조방법.
  4. 기판(21)의 액티브 영역상에 게이트를 형성하는 공정과, 질화막(30)과 폴리실리콘(31)을 차례로 증착하고 에치하여 질화막(30)과 폴리실리콘(31)으로 된 측벽을 형성한후 N+이온을 주입하는 공정과, 상기 폴리실리콘(31)을 제거하고 산화막(27)을 형성하는 공정과, 상기 질화막(30)을 제거하고, N-,P-이온을 주입하는 공정을 차례로 실시하여서 이루어짐을 특징으로 하는 반도체 소자의 LDD제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920010235A 1992-06-12 1992-06-12 반도체 소자의 ldd 제조방법 KR950002196B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019920010235A KR950002196B1 (ko) 1992-06-12 1992-06-12 반도체 소자의 ldd 제조방법
TW082102471A TW234773B (ko) 1992-06-12 1993-04-02
DE4318866A DE4318866C2 (de) 1992-06-12 1993-06-07 Verfahren zum Herstellen eines MOSFET
JP16333193A JP3394562B2 (ja) 1992-06-12 1993-06-08 Ｍｏｓｆｅｔ製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920010235A KR950002196B1 (ko) 1992-06-12 1992-06-12 반도체 소자의 ldd 제조방법

Publications (2)

Publication Number Publication Date
KR940001460A true KR940001460A (ko) 1994-01-11
KR950002196B1 KR950002196B1 (ko) 1995-03-14

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ID=19334606

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920010235A KR950002196B1 (ko) 1992-06-12 1992-06-12 반도체 소자의 ldd 제조방법

Country Status (4)

Country Link
JP (1) JP3394562B2 (ko)
KR (1) KR950002196B1 (ko)
DE (1) DE4318866C2 (ko)
TW (1) TW234773B (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444002A (en) * 1993-12-22 1995-08-22 United Microelectronics Corp. Method of fabricating a short-channel DMOS transistor with removable sidewall spacers
EP2073391B1 (en) 2007-12-21 2011-06-08 Fujitsu Ten Limited Method of operating a radio tuner, for detecting and responding to effects of tunnel situations on radio reception by an in-vehicle radio receiver

Also Published As

Publication number Publication date
DE4318866A1 (de) 1993-12-16
DE4318866C2 (de) 1997-01-23
KR950002196B1 (ko) 1995-03-14
JP3394562B2 (ja) 2003-04-07
JPH0653231A (ja) 1994-02-25
TW234773B (ko) 1994-11-21

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