KR920015592A - Ldd구조의 트랜지스터 제조방법 - Google Patents
Ldd구조의 트랜지스터 제조방법 Download PDFInfo
- Publication number
- KR920015592A KR920015592A KR1019910000561A KR910000561A KR920015592A KR 920015592 A KR920015592 A KR 920015592A KR 1019910000561 A KR1019910000561 A KR 1019910000561A KR 910000561 A KR910000561 A KR 910000561A KR 920015592 A KR920015592 A KR 920015592A
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- forming
- film
- nitride film
- ldd structure
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims 2
- 238000000034 method Methods 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims 6
- 150000002500 ions Chemical class 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 230000000873 masking effect Effects 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 공정단면도.
Claims (1)
- 기판위에 버퍼산화막과 제1질화막을 형성하고 액티브 영역을 정의한 후 필드산화막을 형성하는 공정과, 상기 산화막과 제1질화막을 제거하고 베이스산화막 및 제2질화막을 증착 후 제2질화막을 패터닝하고 N-이온을 주입하는 공정과, 상기 제2질화막을 이용한 선택적 산화막을 500-1500Å 형성하는 공정과, 상기 제2질화막과 베이스산화막을 제거하고 게이트산화막과 다결정 실리콘을 형성한 후 패터닝하는 공정과, 산화막을 형성하여 마스킹없이 식각함으로 게이트 측벽산화막을 남긴 후 N+이온을 주입하는 공정을 차례로 실시하여서 이루어짐을 특징으로 하는 LDD구조의 트랜지스터 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910000561A KR940002778B1 (ko) | 1991-01-15 | 1991-01-15 | Ldd 구조의 트랜지스터 제조방법 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910000561A KR940002778B1 (ko) | 1991-01-15 | 1991-01-15 | Ldd 구조의 트랜지스터 제조방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920015592A true KR920015592A (ko) | 1992-08-27 |
| KR940002778B1 KR940002778B1 (ko) | 1994-04-02 |
Family
ID=19309828
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910000561A KR940002778B1 (ko) | 1991-01-15 | 1991-01-15 | Ldd 구조의 트랜지스터 제조방법 |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR940002778B1 (ko) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100298984B1 (ko) * | 1997-06-24 | 2001-11-30 | 다니구찌 이찌로오, 기타오카 다카시 | 반도체장치및그제조방법 |
-
1991
- 1991-01-15 KR KR1019910000561A patent/KR940002778B1/ko not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100298984B1 (ko) * | 1997-06-24 | 2001-11-30 | 다니구찌 이찌로오, 기타오카 다카시 | 반도체장치및그제조방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR940002778B1 (ko) | 1994-04-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR920015592A (ko) | Ldd구조의 트랜지스터 제조방법 | |
| KR940016887A (ko) | 반도체 소자의 미세 게이트전극 형성방법 | |
| KR920015424A (ko) | 반도체 제조 방법 | |
| KR960009015A (ko) | 반도체 소자의 게이트 전극 형성방법 | |
| KR970054387A (ko) | 모스트랜지스터 제조 방법 | |
| KR920010769A (ko) | 국부적 질소이온 주입을 이용한 모스 트랜지스터 제조방법 | |
| KR970054209A (ko) | 트랜지스터 및 그 트랜지스터를 이용한 마스크 롬 제조방법 | |
| KR920013755A (ko) | 멀티게이트를 사용한 모스 트랜지스터 및 그 제조방법 | |
| KR940010308A (ko) | 박막 트랜지스터 및 그 제조 방법 | |
| KR920013775A (ko) | 트랜치 사용 트랜지스터 제조방법 | |
| KR920020606A (ko) | 반도체장치 및 그 제조방법 | |
| KR920013601A (ko) | 모스 트랜지스터 제조방법 | |
| KR920015433A (ko) | 모스 트렌지스터 공정방법 | |
| KR910016099A (ko) | 듀얼게이트 트랜지스터 제조방법 | |
| KR910005441A (ko) | 실리사이드를 사용한 매설 접촉 형성방법 | |
| KR910017634A (ko) | 메모리 셀 커패시터 제조방법 | |
| KR980005881A (ko) | 반도체 소자의 제조방법 | |
| KR920017215A (ko) | 실리콘 성장을 이용한 soi의 제조방법 | |
| KR940008126A (ko) | 모스(mos) 트랜지스터의 게이트 제조방법 | |
| KR940016753A (ko) | 박막트랜지스터 및 그 제조방법 | |
| KR970053448A (ko) | 반도체 장치의 제조방법 | |
| KR950030381A (ko) | 다결정실리콘 소오스, 드레인(source, drain)을 갖는 상보형 트랜지스터 및 그 제조방법 | |
| KR920018877A (ko) | n및 p모스패트 제조방법 | |
| KR910019255A (ko) | 폴리슬로우프프로파일을 이용한 l.d.d의 형성방법 | |
| KR920013625A (ko) | 반도체장치의 이온 주입 방법 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| G160 | Decision to publish patent application | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20050318 Year of fee payment: 12 |
|
| LAPS | Lapse due to unpaid annual fee |