KR920015433A - 모스 트렌지스터 공정방법 - Google Patents
모스 트렌지스터 공정방법 Download PDFInfo
- Publication number
- KR920015433A KR920015433A KR1019910000483A KR910000483A KR920015433A KR 920015433 A KR920015433 A KR 920015433A KR 1019910000483 A KR1019910000483 A KR 1019910000483A KR 910000483 A KR910000483 A KR 910000483A KR 920015433 A KR920015433 A KR 920015433A
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- forming
- mos transistor
- process method
- transistor process
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 9
- 125000006850 spacer group Chemical group 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 2
- 150000004767 nitrides Chemical class 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 150000002500 ions Chemical class 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명의 싸이드-웰 스페이서 밑에 게이트 산화막을 두번 형성시키는 모스 트랜지스터 공정도.
Claims (1)
- 실리콘 기판에 베이스 산화막을 증착한 후 질화막을 형성하면 "N-"층을 형성하고 베이스 산화막을 제거하는 공정과, 상기베이스 산화막을 제거하고 게이트 산화막과 고온 산화막을 증착한 후 싸이드-웰 스페이서(5) 밑에 게이트 산화막(20)을형성하는 공정과, 소오스와 드레인영역을 형성하기 위해서 n+ 이온주입하고 질화막을 제거하여 게이트 산화막(0)과 게이트 폴리를 증착한 후 게이트 전극의 공정을 포함하여 이루어진 것을 특징으로 하는 모스 트랜지스터 공정방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910000483A KR940001500B1 (ko) | 1991-01-15 | 1991-01-15 | 모스 트랜지스터 공정방법 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910000483A KR940001500B1 (ko) | 1991-01-15 | 1991-01-15 | 모스 트랜지스터 공정방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920015433A true KR920015433A (ko) | 1992-08-26 |
| KR940001500B1 KR940001500B1 (ko) | 1994-02-23 |
Family
ID=19309772
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910000483A KR940001500B1 (ko) | 1991-01-15 | 1991-01-15 | 모스 트랜지스터 공정방법 |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR940001500B1 (ko) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100418923B1 (ko) * | 2001-06-27 | 2004-02-14 | 주식회사 하이닉스반도체 | 반도체소자의 제조방법 |
-
1991
- 1991-01-15 KR KR1019910000483A patent/KR940001500B1/ko active IP Right Grant
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100418923B1 (ko) * | 2001-06-27 | 2004-02-14 | 주식회사 하이닉스반도체 | 반도체소자의 제조방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR940001500B1 (ko) | 1994-02-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR850005163A (ko) | 전계효과형 트랜지스터의 제조방법 | |
| KR920015433A (ko) | 모스 트렌지스터 공정방법 | |
| KR920013601A (ko) | 모스 트랜지스터 제조방법 | |
| KR920015572A (ko) | 반도체 장치의 제조방법 | |
| KR920003540A (ko) | 측벽을 가지지 않는 반도체 소자의 제조방법 | |
| KR910017672A (ko) | 모스패트 제조방법 | |
| KR970003447A (ko) | 모스 트랜지스터의 소스/드레인 영역의 어닐링 방법 | |
| KR920015592A (ko) | Ldd구조의 트랜지스터 제조방법 | |
| KR930003423A (ko) | 반도체 장치의 제조방법 | |
| KR930006982A (ko) | 모스펫 (mosfet) 제조 방법 | |
| KR970052835A (ko) | 코발트 실리사이드막을 이용한 트랜지스터 형성방법 | |
| KR910020934A (ko) | Tita 모스 fet제조방법 및 구조 | |
| KR920013746A (ko) | Ldd구조의 트랜지스터 제조방법 | |
| KR920015611A (ko) | 씨모스 제조방법 | |
| KR920008963A (ko) | Mos트랜지스터의 채널도핑방법 | |
| KR910020798A (ko) | 씨모스 트랜지스터 제조방법 | |
| KR970054209A (ko) | 트랜지스터 및 그 트랜지스터를 이용한 마스크 롬 제조방법 | |
| KR960026395A (ko) | 반도체 소자의 도전층 형성방법 | |
| KR930015084A (ko) | 박막 트랜지스터의 구조와 그 제조방법 | |
| KR920017215A (ko) | 실리콘 성장을 이용한 soi의 제조방법 | |
| KR920013755A (ko) | 멀티게이트를 사용한 모스 트랜지스터 및 그 제조방법 | |
| KR920022554A (ko) | 반도체장치의 제조방법 | |
| KR920001656A (ko) | 모스 박막 트랜지스터 제조방법 | |
| KR890002991A (ko) | 씨모오스 반도체장치의 제조방법 | |
| KR910001941A (ko) | 모오스 fet 제조방법 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| G160 | Decision to publish patent application | ||
| E701 | Decision to grant or registration of patent right | ||
| NORF | Unpaid initial registration fee |