KR910019204A - 슬롭형 게이트를 이용한 ldd제조방법 - Google Patents
슬롭형 게이트를 이용한 ldd제조방법 Download PDFInfo
- Publication number
- KR910019204A KR910019204A KR1019900006277A KR900006277A KR910019204A KR 910019204 A KR910019204 A KR 910019204A KR 1019900006277 A KR1019900006277 A KR 1019900006277A KR 900006277 A KR900006277 A KR 900006277A KR 910019204 A KR910019204 A KR 910019204A
- Authority
- KR
- South Korea
- Prior art keywords
- gate
- slop
- depositing
- forming
- ldd
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 238000000151 deposition Methods 0.000 claims 4
- 238000000034 method Methods 0.000 claims 3
- 239000005380 borophosphosilicate glass Substances 0.000 claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 2
- 229920005591 polysilicon Polymers 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 239000007943 implant Substances 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 claims 1
- 150000002500 ions Chemical class 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Drying Of Semiconductors (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 2 도(A)∼(F)는 본 발명에 따른 LDD제조 공정도, 제 3 도는 본 발명에 따른 LDD형성 원리도.
Claims (1)
- 실리콘 기판(10)에 필드옥사이드(20)를 형성하고 게이트 옥사이드(30)를 증착한후 폴리실리콘(40)을 증착하는 공정과, 상기 폴리실리콘(40)를 에치 바이어스를 주어 경사지게 에치하여 슬롭형게이트(40a)를 형성하는 공정과, 상기 슬롭형 게이트(40a)를 형성한 다음, LTO(50)를 증착하고 N+이온(60) 주입하여 N+소오스 드레인 영역(70)과 N-LDD영역(80)을 형성하는 공정과, 상기 공정후 BPSG(90)를 증착한 다음 LTO(5)와 BPSG(90)를 에치하고 콘택 베탈(100)을 주입하는 공정을 포함하여 N-이온주입공정과 사이드월 공정을 생략하는 것을 특징으로 하는 슬롭형 게이트를 이용한 LDD제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900006277A KR920007359B1 (ko) | 1990-04-30 | 1990-04-30 | 슬롭형 게이트를 이용한 ldd 제조방법 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900006277A KR920007359B1 (ko) | 1990-04-30 | 1990-04-30 | 슬롭형 게이트를 이용한 ldd 제조방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR910019204A true KR910019204A (ko) | 1991-11-30 |
| KR920007359B1 KR920007359B1 (ko) | 1992-08-31 |
Family
ID=19298661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019900006277A KR920007359B1 (ko) | 1990-04-30 | 1990-04-30 | 슬롭형 게이트를 이용한 ldd 제조방법 |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR920007359B1 (ko) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100418571B1 (ko) * | 2001-06-28 | 2004-02-11 | 주식회사 하이닉스반도체 | 저농도 도핑 드레인 구조의 모스 트랜지스터 제조방법 |
-
1990
- 1990-04-30 KR KR1019900006277A patent/KR920007359B1/ko not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100418571B1 (ko) * | 2001-06-28 | 2004-02-11 | 주식회사 하이닉스반도체 | 저농도 도핑 드레인 구조의 모스 트랜지스터 제조방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR920007359B1 (ko) | 1992-08-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR870000763A (ko) | 반도체 장치 및 그 제조방법 | |
| KR920022553A (ko) | Ldd 소자의 구조 및 제조방법 | |
| KR910019204A (ko) | 슬롭형 게이트를 이용한 ldd제조방법 | |
| KR930001485A (ko) | Gldd 모스패트 제조방법 | |
| KR940001460A (ko) | 반도체 소자의 ldd 제조방법 | |
| KR940016888A (ko) | 트랜지스터 형성 방법 | |
| KR950009978A (ko) | 모스트랜지스터의 제조방법 | |
| KR930003434A (ko) | Ldd 구조의 모스 트랜지스터 제조방법 | |
| KR920010769A (ko) | 국부적 질소이온 주입을 이용한 모스 트랜지스터 제조방법 | |
| KR920018980A (ko) | P형 채널 mosfet 제조방법 | |
| KR910016099A (ko) | 듀얼게이트 트랜지스터 제조방법 | |
| KR910019257A (ko) | 피-채널 트랜지스터 제조방법 | |
| KR930001480A (ko) | 트랜치 베리드 ldd mosfet의 구조 및 제조 방법 | |
| KR910017635A (ko) | 메모리 셀 커패시터 제조방법 | |
| KR930015081A (ko) | 얕은 접합 모스패트 제조방법 | |
| KR890002992A (ko) | 모오스 전계효과 트랜지스터의 제조방법 | |
| KR930001478A (ko) | 모스패트의 구조 및 제조 방법 | |
| KR970054497A (ko) | 박막 트랜지스터 제조방법 | |
| KR960026973A (ko) | 박막트랜지스터 제조방법 | |
| KR910019256A (ko) | 앤-채널 트랜지스터 제조방법 | |
| KR970008585A (ko) | 시모스 반도체 장치의 제조방법 | |
| KR920013765A (ko) | Mosfet 제조방법 | |
| KR920015426A (ko) | 폴리머를 이용한 측벽 및 자기 정합 콘택 형성방법 | |
| KR970053920A (ko) | 씨모스(cmos) 트랜지스터의 제조방법 | |
| KR910017634A (ko) | 메모리 셀 커패시터 제조방법 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| G160 | Decision to publish patent application | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20020716 Year of fee payment: 11 |
|
| LAPS | Lapse due to unpaid annual fee |