KR100418571B1 - 저농도 도핑 드레인 구조의 모스 트랜지스터 제조방법 - Google Patents
저농도 도핑 드레인 구조의 모스 트랜지스터 제조방법 Download PDFInfo
- Publication number
- KR100418571B1 KR100418571B1 KR10-2001-0037397A KR20010037397A KR100418571B1 KR 100418571 B1 KR100418571 B1 KR 100418571B1 KR 20010037397 A KR20010037397 A KR 20010037397A KR 100418571 B1 KR100418571 B1 KR 100418571B1
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- South Korea
- Prior art keywords
- ldd
- drain
- source
- ion implantation
- gate electrode
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000005468 ion implantation Methods 0.000 claims abstract description 27
- 125000006850 spacer group Chemical group 0.000 claims abstract description 22
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 21
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 230000004913 activation Effects 0.000 claims 2
- 239000002019 doping agent Substances 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Ceramic Engineering (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims (4)
- 소자분리막이 형성된 반도체 기판 상에 게이트 절연막 및 게이트 전극을 형성하는 제1 단계;상기 게이트 전극이 형성된 전체 구조 표면을 따라 절연막을 형성하는 제2 단계;상기 절연막이 형성된 반도체 기판에 대해 고농도 소오스/드레인 이온주입을 실시하는 제3 단계;상기 게이트 전극의 일측 및 타측 방향으로 각각 경사를 주어 제1 및 제2 LDD 이온주입을 실시하는 제4 단계;상기 절연막을 비등방성 전면 식각하여 상기 게이트 전극 측벽에 스페이서 절연막을 형성하는 제5 단계; 및상기 제5 단계 수행 후, 노출된 상기 반도체 기판 및 게이트 전극 표면에 자기정렬 실리사이드막을 형성하는 제6 단계를 포함하는 저농도 도핑 드레인 구조의 모스 트랜지스터 제조방법.
- 제1항에 있어서,상기 제3 단계 수행 후,900∼1100℃의 온도에서 30∼90초 동안 도펀트 활성화를 위한 어닐링을 실시하는 제7 단계를 더 포함하는 것을 특징으로 하는 저농도 도핑 드레인 구조의 모스트랜지스터 제조방법.
- 제2항에 있어서,상기 제4 단계 수행 후,700∼900℃의 온도에서 30∼90초 동안 도펀트 활성화를 위한 어닐링을 실시하는 제8 단계를 더 포함하는 것을 특징으로 하는 저농도 도핑 드레인 구조의 모스 트랜지스터 제조방법.
- 제2항 또는 제3항에 있어서,상기 제1 및 제2 LDD 이온주입은 상기 게이트 전극의 일측 및 타측 방향으로 각각 30∼45°의 경사를 두고 이온주입을 수행하는 것을 특징으로 하는 저농도 도핑 드레인 구조의 모스 트랜지스터 제조방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0037397A KR100418571B1 (ko) | 2001-06-28 | 2001-06-28 | 저농도 도핑 드레인 구조의 모스 트랜지스터 제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2001-0037397A KR100418571B1 (ko) | 2001-06-28 | 2001-06-28 | 저농도 도핑 드레인 구조의 모스 트랜지스터 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20030001067A KR20030001067A (ko) | 2003-01-06 |
KR100418571B1 true KR100418571B1 (ko) | 2004-02-11 |
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KR10-2001-0037397A KR100418571B1 (ko) | 2001-06-28 | 2001-06-28 | 저농도 도핑 드레인 구조의 모스 트랜지스터 제조방법 |
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Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100924859B1 (ko) * | 2007-12-28 | 2009-11-02 | 주식회사 동부하이텍 | 고전압 반도체 소자의 제조방법 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR910019204A (ko) * | 1990-04-30 | 1991-11-30 | 문정환 | 슬롭형 게이트를 이용한 ldd제조방법 |
EP0541212A2 (en) * | 1991-11-08 | 1993-05-12 | Advanced Micro Devices, Inc. | Process for fabricating semiconductor metal oxide device |
KR940016884A (ko) * | 1992-12-07 | 1994-07-25 | 김광호 | 엘디디(ldd)형 모스 트랜지스터 제조방법 |
JP2000138369A (ja) * | 1998-10-30 | 2000-05-16 | Sharp Corp | 半導体装置の製造方法 |
US6180464B1 (en) * | 1998-11-24 | 2001-01-30 | Advanced Micro Devices, Inc. | Metal oxide semiconductor device with localized laterally doped channel |
US6218250B1 (en) * | 1999-06-02 | 2001-04-17 | Advanced Micro Devices, Inc. | Method and apparatus for minimizing parasitic resistance of semiconductor devices |
KR20010050044A (ko) * | 1999-08-12 | 2001-06-15 | 포만 제프리 엘 | 소스/드레인 접합부에서 측방 도핑 분포를 급경사지게형성하는 방법 및 소자 |
-
2001
- 2001-06-28 KR KR10-2001-0037397A patent/KR100418571B1/ko active IP Right Grant
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR910019204A (ko) * | 1990-04-30 | 1991-11-30 | 문정환 | 슬롭형 게이트를 이용한 ldd제조방법 |
EP0541212A2 (en) * | 1991-11-08 | 1993-05-12 | Advanced Micro Devices, Inc. | Process for fabricating semiconductor metal oxide device |
KR940016884A (ko) * | 1992-12-07 | 1994-07-25 | 김광호 | 엘디디(ldd)형 모스 트랜지스터 제조방법 |
JP2000138369A (ja) * | 1998-10-30 | 2000-05-16 | Sharp Corp | 半導体装置の製造方法 |
US6180464B1 (en) * | 1998-11-24 | 2001-01-30 | Advanced Micro Devices, Inc. | Metal oxide semiconductor device with localized laterally doped channel |
US6218250B1 (en) * | 1999-06-02 | 2001-04-17 | Advanced Micro Devices, Inc. | Method and apparatus for minimizing parasitic resistance of semiconductor devices |
KR20010050044A (ko) * | 1999-08-12 | 2001-06-15 | 포만 제프리 엘 | 소스/드레인 접합부에서 측방 도핑 분포를 급경사지게형성하는 방법 및 소자 |
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KR20030001067A (ko) | 2003-01-06 |
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