KR960039239A - 반도체 장치 - Google Patents
반도체 장치 Download PDFInfo
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- KR960039239A KR960039239A KR1019960011710A KR19960011710A KR960039239A KR 960039239 A KR960039239 A KR 960039239A KR 1019960011710 A KR1019960011710 A KR 1019960011710A KR 19960011710 A KR19960011710 A KR 19960011710A KR 960039239 A KR960039239 A KR 960039239A
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- flexible substrate
- semiconductor chip
- bump
- conductor
- conductor lead
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
제1범프는 반도체 칩의 전극상에 배열된다. 개방부는 반도체칩상의 전극에 대응하는 위치에 형성되고, 도체리드는 패턴 형성되고 개방부에 배열되며, 장치의 외측에 접속된 제2범프는 플렉시블 기판상에 형성되고, 도체리드와 제1범프는 개방부에서 서로 접속되어 있다. 플렉시블 기판의 외형은 반도체 칩의 외형과 거의 같다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명의 반도체 장치의 제1실시예의 단면도.
Claims (10)
- 외형이 반도체칩과 동일하고, 반도체칩상의 전극에 대응하는 위치에 개방부를 갖고 있는 플렉시블기판과, 플렉시블기판상에 패턴 형성되고 상기 개방부에 배치된 도체 리드와, 상기 반도체칩의 전극상에 형성되어 상기 도체 리드와 접속하는 제1범프와, 상기 플렉시블기판상의 도체 리드에 접속된 외부 접속용이 제2범프를 포함하는 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서, 도체 리드가 반도체칩에 대향인 플렉시블기판의 면에 설치되고, 제1범프가 플렉시블기판의 개방부에 끼워 합쳐진것을 특징으로 하는 반도체 장치.
- 제2항에 있어서, 제1범프는 금속돌기를 복수단으로 포갠 것을 특징으로 하는 반도체 장치.
- 제2항에 있어서, 제1범프와 개방부가 수지로 밀봉된 것을 특징으로 하는 반도체 장치.
- 제1항에 있어서, 금속돌기를 복수단으로 포갠 위치결정용 범프는 반도체칩에 설치되고 위치 결정용 범프가 위치 결정용 범프에 대응하는 플렉시블 기판상의 위치에 형성된 위치결정용 개방부에 끼워합쳐진 것을 특징으로 하는 반도체 장치.
- 외형이 반도체칩과 동일하고 반도체칩상의 전극에 대응하는 위치에서 개방 관통구멍을 가진 플랙시블 기판과, 상기 관통구멍을 전도재로 묻은 패드와, 플렉시블기판상에 패턴성형되고 패드에 접속된 도체리드와, 상기 반도체칩상의 전극에 설치되고 패드와 접속하는 제1범프와, 상기 플렉시블기관상의 도체 리드에 접속된 외부접속용의 제2범프를 포함하는 것을 특징으로 하는 반도체 장치.
- 제6항에 있어서, 플렉시블 기판과 반도체 칩 사이의 공간이 수지로 밀봉되는 것을 특징으로 하는 반도체 장치.
- 외형이 반도체칩보다 크고 반도체칩상의 전극에 대응하는 위치에서 개방부를 가진 플렉시블 기판과, 플렉시블 기판상에 패턴 형성되고 개방부에 배열된 도체 리드와, 반도체 칩상의 전극상에 형성되어 도체 리드에 접속된 제1범프와, 반도체칩이 도체 리드에 장착 접속된 플렉시블 기판상의 영역에 형성된 외부 접속용 제2범프와, 반도체칩이 장착되는 영역과 다른 플렉시블 기판상의 영역에 형성되고 도체 리드에 접속되는 테스트용 전극을 포함하며, 상기 절단전 플렉시블 기판을 도체 리드와 함께 반도체칩의 외주를 거의 따라 절단하여, 도체 리드와 플렉시블기판의 외측부분을 제거함으로써, 플렉시블 기판의 외형이 반도체 칩의 외형과 같게 되는 것을 특징으로 하는 반도체 장치.
- 제8항에 있어서, 도체 리드는 반도체칩에 대향인 플렉시블 기판의 표면에 형성되고, 제1범프는 플렉시블 기판의 개방부에 끼워 합쳐지는 것을 특징으로 하는 반도체 장치.
- 외형이 반도체칩보다 크고 반도체 칩상의 전극에 대응하는 위치에서 관통구멍을 가진 플렉시블 기판과, 상기 관통구멍을 전도재로 메워넣은 패드와, 플렉시블 기판상에 패턴 형성되고 패드에 접속된 도체 리드와, 반도체 칩상의 전극상에 형성되어 패드에 접속된 제1범프와, 반도체칩이 도체 리드에 장착 접속된 플렉시블 기판상의 영역에 형성된 외부 접속용 제2범프와, 반도체칩이 장착되는 영역과 다른 플렉시블 기판상의 영역에 형성되고 도체 리드에 접속되는 테스트용 전극을 포함하며, 상기 플렉시블 기판을 도체 리드와 함께 반도체칩의 외주를 거의 따라절단하여, 도체 리드와 플렉시블 기판의 외측부분을 제거함으로써, 플렉시블 기판의 외형이 반도체 칩의 외형과 같게 되는 것을 특징으로 하는 반도체 장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7092155A JPH08288424A (ja) | 1995-04-18 | 1995-04-18 | 半導体装置 |
JP95-92155 | 1995-04-18 |
Publications (2)
Publication Number | Publication Date |
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KR960039239A true KR960039239A (ko) | 1996-11-21 |
KR100223727B1 KR100223727B1 (ko) | 1999-10-15 |
Family
ID=14046540
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960011710A KR100223727B1 (ko) | 1995-04-18 | 1996-04-18 | 반도체 장치 |
Country Status (3)
Country | Link |
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US (1) | US5892271A (ko) |
JP (1) | JPH08288424A (ko) |
KR (1) | KR100223727B1 (ko) |
Families Citing this family (55)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SG60102A1 (en) * | 1996-08-13 | 1999-02-22 | Sony Corp | Lead frame semiconductor package having the same and method for manufacturing the same |
KR100222299B1 (ko) * | 1996-12-16 | 1999-10-01 | 윤종용 | 웨이퍼 레벨 칩 스케일 패키지 및 그의 제조 방법 |
US6064576A (en) * | 1997-01-02 | 2000-05-16 | Texas Instruments Incorporated | Interposer having a cantilevered ball connection and being electrically connected to a printed circuit board |
JPH10326795A (ja) * | 1997-03-28 | 1998-12-08 | Sony Corp | 半導体装置とその製造方法 |
US6551857B2 (en) * | 1997-04-04 | 2003-04-22 | Elm Technology Corporation | Three dimensional structure integrated circuits |
US6114763A (en) * | 1997-05-30 | 2000-09-05 | Tessera, Inc. | Semiconductor package with translator for connection to an external substrate |
JPH10335567A (ja) * | 1997-05-30 | 1998-12-18 | Mitsubishi Electric Corp | 半導体集積回路装置 |
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-
1995
- 1995-04-18 JP JP7092155A patent/JPH08288424A/ja active Pending
-
1996
- 1996-04-18 KR KR1019960011710A patent/KR100223727B1/ko not_active IP Right Cessation
- 1996-04-18 US US08/634,411 patent/US5892271A/en not_active Expired - Lifetime
Also Published As
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KR100223727B1 (ko) | 1999-10-15 |
JPH08288424A (ja) | 1996-11-01 |
US5892271A (en) | 1999-04-06 |
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