KR960035987A - 반도체장치 - Google Patents
반도체장치 Download PDFInfo
- Publication number
- KR960035987A KR960035987A KR1019960006516A KR19960006516A KR960035987A KR 960035987 A KR960035987 A KR 960035987A KR 1019960006516 A KR1019960006516 A KR 1019960006516A KR 19960006516 A KR19960006516 A KR 19960006516A KR 960035987 A KR960035987 A KR 960035987A
- Authority
- KR
- South Korea
- Prior art keywords
- anisotropic conductive
- conductive sheet
- external connection
- wiring pattern
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract 14
- 239000011248 coating agent Substances 0.000 claims abstract 2
- 238000000576 coating method Methods 0.000 claims abstract 2
- 229910000679 solder Inorganic materials 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/5328—Conductive materials containing conductive organic materials or pastes, e.g. conductive adhesives, inks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/13164—Palladium [Pd] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
Abstract
본 발명은 간단한 구성으로 제조가 용이하고, 저가로 제조할 수 있는 반도체장치에 관한 것으로, 본 발명은 반도체칩(32)의 비활성화막(34) 상에 이방성도전시트(38)가 배치되고, 상기 이방성 도전시트(38)상에 배선패턴(40)이 형성되고, 상기 배선패턴(40)과 상기 반도체칩(32)의 전극(36)이 상기 이방성도전시트(38)가 가압됨으로서 전기적도통이 되고, 상기 이방성도전시트(38) 및 전기배성패턴(40)상에 배선패턴(40)의 외부접속단자접합부(40a)를 노출하여 전기적절연피막(42)이 형성되고, 상기 노출된 외부 접속 단자접합부(40a)에 외부접속단자(46)가 형성되어 있는 것을 특징으로 한다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 제1실시예를 나타낸 단면도.
Claims (6)
- 비활성화막이 형성도니 반도체칩면상에 한쪽 면에 배선패턴이 형성된 이방성도전시트의 다른쪽 면이 고착되고, 상기 배선패턴과 상기 반도체칩의 전극이 상기 이방성도전시트를 거쳐서 전기적으로 접속되어 있고, 상기 배선패턴의 외부접속단접합부를 노출하여 전기적절연피막이 형성되고, 또 상기 외부접속자접합부에 외부접속단자가 형성된 것을 특징으로 하는 반도체장치.
- 제1항에 있어서, 상기 배선패턴에 의해서 상기 이방성도전시트가 밀어눌림으로서 전기적으로 접속된 것을 특징으로 하는 반도체장치.
- 제1항에 있어서, 상기 반도체칩의 전극에 상기 비활성막보다도 밖깥쪽으로 돌출하는 범프가 형성되고, 상기 범프에 의해 상기 이방성도전 시트가 밀어눌림으로서 전기적으로 접속된 것을 특징으로 하는 반도체장치.
- 제1항 내지 제3항중 어느 한항에 있어서, 상기 전기적절연피막이 감광성 솔더레지스트막으로 형성된 것을 특징으로 하는 반도체장치.
- 제1항 내지 제4항중 어느 한항에 있어서, 상기 외부접속단자접합부에 형성되는 외부접속단자가 범프인 것을 특징으로 하는 반도체장치.
- 제1항 내지 제5항중 어느 한항에 있어서, 상기 반도체칩을 복수개 구비하고, 상기 복수의 반도체칩상에 공통의 상기 이방성도전시트가 고착되고, 상기 복수의 반도체칩의 소요의 전극끼리 상기 배선패턴에 의해 접속되고, 상기 배선패턴상에 공통의 상기 전기적절연피막이 형성된 것을 특징으로 하는 반도체장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6560995 | 1995-03-24 | ||
JP95-065609 | 1995-03-24 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960035987A true KR960035987A (ko) | 1996-10-28 |
KR100218996B1 KR100218996B1 (ko) | 1999-09-01 |
Family
ID=13291934
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960006516A KR100218996B1 (ko) | 1995-03-24 | 1996-03-12 | 반도체장치 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5677576A (ko) |
EP (1) | EP0734065B1 (ko) |
KR (1) | KR100218996B1 (ko) |
DE (1) | DE69621863T2 (ko) |
Families Citing this family (60)
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FR2863767B1 (fr) * | 2003-12-12 | 2006-06-09 | Commissariat Energie Atomique | Support memoire irreversible a deformation plastique et procede de realisation d'un tel support |
US7419852B2 (en) * | 2004-08-27 | 2008-09-02 | Micron Technology, Inc. | Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies |
JP3976043B2 (ja) * | 2004-10-25 | 2007-09-12 | セイコーエプソン株式会社 | 半導体装置及びその製造方法 |
US20060170096A1 (en) * | 2005-02-02 | 2006-08-03 | Yang Jun Y | Chip scale package and method for manufacturing the same |
KR100664310B1 (ko) * | 2005-07-13 | 2007-01-04 | 삼성전자주식회사 | 웨이퍼 레벨 인캡슐레이션 칩 및 인캡슐레이션 칩 제조방법 |
JP4105202B2 (ja) | 2006-09-26 | 2008-06-25 | 新光電気工業株式会社 | 半導体装置の製造方法 |
JP4883095B2 (ja) * | 2006-12-19 | 2012-02-22 | 株式会社村田製作所 | 多層配線基板 |
KR100905779B1 (ko) * | 2007-08-20 | 2009-07-02 | 주식회사 하이닉스반도체 | 반도체 패키지 |
US20090279275A1 (en) * | 2008-05-09 | 2009-11-12 | Stephen Peter Ayotte | Method of attaching an integrated circuit chip to a module |
FR2943849B1 (fr) * | 2009-03-31 | 2011-08-26 | St Microelectronics Grenoble 2 | Procede de realisation de boitiers semi-conducteurs et boitier semi-conducteur |
CN103824836B (zh) * | 2010-08-31 | 2017-03-01 | 先进封装技术私人有限公司 | 半导体承载元件及半导体封装件 |
US9502270B2 (en) | 2014-07-08 | 2016-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device packages, packaging methods, and packaged semiconductor devices |
KR102387541B1 (ko) * | 2015-03-25 | 2022-04-18 | 삼성전자주식회사 | 반도체 칩, 및 이를 포함하는 플립 칩 패키지와 웨이퍼 레벨 패키지 |
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JPS60116157A (ja) * | 1983-11-29 | 1985-06-22 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JPS634633A (ja) * | 1986-06-25 | 1988-01-09 | Hitachi Ltd | バンプレスフイルムキヤリア |
US4811081A (en) * | 1987-03-23 | 1989-03-07 | Motorola, Inc. | Semiconductor die bonding with conductive adhesive |
JPH01122128A (ja) * | 1987-11-05 | 1989-05-15 | Fuji Electric Co Ltd | 半導体装置 |
SG49842A1 (en) * | 1988-11-09 | 1998-06-15 | Nitto Denko Corp | Wiring substrate film carrier semiconductor device made by using the film carrier and mounting structure comprising the semiconductor |
JPH0724270B2 (ja) * | 1989-12-14 | 1995-03-15 | 株式会社東芝 | 半導体装置及びその製造方法 |
JPH03244140A (ja) * | 1990-02-22 | 1991-10-30 | Sony Corp | 半導体装置 |
FR2673043B1 (fr) * | 1991-02-20 | 1997-07-04 | Telecommunications Sa | Systeme de composants electriques, d'un reseau d'interconnexion et d'une embase. |
US5667884A (en) * | 1993-04-12 | 1997-09-16 | Bolger; Justin C. | Area bonding conductive adhesive preforms |
JP2833996B2 (ja) * | 1994-05-25 | 1998-12-09 | 日本電気株式会社 | フレキシブルフィルム及びこれを有する半導体装置 |
JP3142723B2 (ja) * | 1994-09-21 | 2001-03-07 | シャープ株式会社 | 半導体装置及びその製造方法 |
-
1996
- 1996-03-12 KR KR1019960006516A patent/KR100218996B1/ko not_active IP Right Cessation
- 1996-03-20 US US08/618,807 patent/US5677576A/en not_active Expired - Lifetime
- 1996-03-21 EP EP96301937A patent/EP0734065B1/en not_active Expired - Lifetime
- 1996-03-21 DE DE69621863T patent/DE69621863T2/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5677576A (en) | 1997-10-14 |
DE69621863D1 (de) | 2002-07-25 |
EP0734065A3 (en) | 1997-03-05 |
DE69621863T2 (de) | 2002-11-21 |
EP0734065B1 (en) | 2002-06-19 |
EP0734065A2 (en) | 1996-09-25 |
KR100218996B1 (ko) | 1999-09-01 |
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