KR950034638A - 반도체장치 - Google Patents

반도체장치 Download PDF

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Publication number
KR950034638A
KR950034638A KR1019950012574A KR19950012574A KR950034638A KR 950034638 A KR950034638 A KR 950034638A KR 1019950012574 A KR1019950012574 A KR 1019950012574A KR 19950012574 A KR19950012574 A KR 19950012574A KR 950034638 A KR950034638 A KR 950034638A
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KR
South Korea
Prior art keywords
mounting portion
substrate mounting
signal lead
semiconductor device
ceramic layer
Prior art date
Application number
KR1019950012574A
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English (en)
Other versions
KR100192631B1 (ko
Inventor
메그미 구스미
Original Assignee
사토 후미오
가부시키가이샤 도시바
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Application filed by 사토 후미오, 가부시키가이샤 도시바 filed Critical 사토 후미오
Publication of KR950034638A publication Critical patent/KR950034638A/ko
Application granted granted Critical
Publication of KR100192631B1 publication Critical patent/KR100192631B1/ko

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Abstract

본 발명은 전기 특성의 핀 간 의존성을 감소시켜 고주파 영역에서의 동작이 가능한 반도체장치를 제공하고, 반도체기판의 칩 두께가 증대해도 기판 탑재부의 캐비티부로의 와이어본딩을 가능하게 하며, 캐비티부에 특정의 전위를 유지한 대전류하에서의 사용 및 고속동자에 대응한 반도체장치를 제공한다.
기판 탑재부(10)에는 주면 중앙부분의 캐비티부(11)에 반도체기판(1)이 고착되어 있다. 신호리드(41)와 전원리드(31)를 갖춘 복수의 내부리드는 기판탑재부의 주면 주변부분에 그 선단이 반도체기판에 대향하도록 배치되고, 상기 내부리드의 선단부와 반도체기판은 본딩와이어로 접속되어 있다. 신호리드(41)와 반도체기판(1)을 잇는 본딩와이어 길이는 모두 실질적으로 동일하다.
내부리드는 기판 탑재부 주변에 적어도 2층에 적층된 세리믹층(40)에 형성된 개구부의 개구 형상은 기판 탑재부보다 각이 많은 다각형으로 하고 있다. 신호리드를 지지하는 세라믹층(40)에 있어서, 이 기판 탑재부(10)의 각에 가까운 부분은 높고, 이 기판 탑재부의 변의 중앙부분으로 되는 만큼 낮게 하도록 단차를 형성할 수 있다. 내부리드의 신호리드를 지지하는 기판 탑재부의 세라믹층의 개구부 또는 캐비티부의 형상을 각형의 기판 탑재부보다 각을 많게 하여 다각형으로 하든가 또는 신호리드를 갖춘 세라믹층의 소정의 영역에 단차를 형성하는 것에 의해 내부리드/반도체기판의 접속전극간의 본딩와이어 길이의 오차를 적게한다.

Description

반도체장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 따른 반도체장치의 평면도, 제2도는 제1실시예에 따른 반도체장치의 평면도. 제3도는 제1실시예에 따른 기판 탑재부의 사시도.

Claims (27)

  1. 집적회로가 형성된 반도체기판(1)과, 주면 중앙부분에 형성된 캐비티부(11)에 상기 반도체기판(1)이 고착되어 있는 기판탑재부(10), 이 기판 탑재부(10)의 주면 주변부분에 그 선단이 상기 반도체기판(1)에 대향하도록 배치되고, 신호리드(41)와 전원리드(31)를 갖춘 복수이 내부리드(31,41,61) 및, 상기 내부리드(31,41,61)의 선단부와 상기 반도체기판(1)에 형성된 접속전극을 접속하는 본딩화이어(32,33,35,42,62)를 구비하고, 상기 내부리드(31,41,61) 중의 신호리드와 상기 반도체기판(1)의 접속전극을 잇는 상기 본딩와이어의 와이어 길이가 모두 실질적으로 동일한 것을 특징으로 하는 반도체장치.
  2. 제1항에 있어서, 상기 내부리드(31,41,61)는 상기 기판 탑재부(10) 주변부에 적어도 2층으로 적층된 세라믹층(30,40,60)의 표면에 형성되면서 상기 신호리드(41)를 지지하는 상기 세라믹층(30,40,60)에 형성된 개구부(15)의 개구 형상은 기판 탑재부(10)보다 각이 많은 다각형인 것을 특징으로 하는 반도체장치.
  3. 제1항에 있어서,상기 내부리드(31,41,61)는 상기 캐비티부(11)를 구성하는 1층의 세라믹층(20,60)의 표면에 형성되고, 이 층 상에는 전원리드(31) 및 신호리드(41)가 형성되고 있고, 더욱이 이 세라믹층(20,60)의 중앙부분에 형성된 상기 캐비티부(11)의 개구형상은 상기 기판 탑재부(10)보다 각이 많은 다각형인 것을 특징으로 하는 반도체장치.
  4. 제1항에 있어서, 캐비티부 저면 상에는 소정의 위치에 어셈블리마크(12)를 형성하는 것을 특징으로 하는 반도체장치.
  5. 제2항에 있어서, 상기 캐비티부(11) 저면 상에는 소정의 위치에 어셈블리마크(12)를 형성하는 것을 특징으로 하는 반도체장치.
  6. 제3항에 있어서, 상기 캐비티부(11) 저면 상에는 소정의 위치에 어셈블리마크(12)를 형성하는 것을 특징으로 하는 반도체장치.
  7. 제1항에 있어서, 상기 신호리드(41)를 지지하는 세라믹층(40)에 있어서 그 소정의 영역을 다른 영역보다 낮게 하여 그곳에 단차를 설치하면서 이 소정의 영역에 형성되어 있는 신호리드에 본딩되는 본딩아이어(42)의 접합점은 상기 다른 영역의 신호리드에 본딩되는 본딩와이어의 접합점보다 상기 반도체기판(1)으로부터 떨어져 있는 것을 특징으로 하는 반도체장치.
  8. 제2항에 있어서, 상기 신호리드(41)를 지지하는 세라믹층(40)에 있어서 그 소정의 영역을 다른 영역보다 낮게 하여 그곳에 단차를 설치하면서 이 소정의 영역에 형성되어 있는 신호리드에 본딩되는 본딩아이어(42)의 접합점의 상기 다른 영역의 신호리드에 본딩되는 본딩와이어 접합점보다 상기 반도체기판(1)으로부터 떨어져 있는 것을 특징으로 하는 반도체장치.
  9. 제3항에 있어서, 상기 신호리드(41)를 지지하는 세라믹층(40)에 있어서, 그 소정이 영역을 다른 영역보다 낮게 하여 그곳에 단차를 설치하면서 이 소정의 영역에 형성되어 있는 신호리드에 본딩되는 본딩와이어(42)의 접합점의 상기 다른 영역의 신호리드에 본딩되는 본딩와이어 접합점보다 상기 반도체기판(1)으로부터 떨어져 있는 것을 특징으로 하는 반도체장치.
  10. 제4항에 있어서, 상기 신호리드(41)를 지지하는 세라믹층(40)에 있어서, 그 소정이 영역을 다른 영역보다 낮게 하여 그곳에 단차를 설치하면서 이 소정의 영역에 형성되어 있는 신호리드에 본딩되는 본딩와이어(42)의 접합점의 상기 다른 영역의 신호리드에 본딩되는 본딩와이어 접합점보다 상기 반도체기판(1)으로부터 떨어져 있는 것을 특징으로 하는 반도체장치.
  11. 제5항에 있어서, 상기 신호리드(41)를 지지하는 세라믹층(40)에 있어서, 그 소정이 영역을 다른 영역보다 낮게 하여 그곳에 단차를 설치하면서 이 소정의 영역에 형성되어 있는 신호리드에 본딩되는 본딩와이어(42)의 접합점의 상기 다른 영역의 신호리드에 본딩되는 본딩와이어 접합점보다 상기 반도체기판(1)으로부터 떨어져 있는 것을 특징으로 하는 반도체장치.
  12. 제6항에 있어서, 상기 신호리드(41)를 지지하는 세라믹층(40)에 있어서, 그 소정이 영역을 다른 영역보다 낮게 하여 그곳에 단차를 설치하면서 이 소정의 영역에 형성되어 있는 신호리드에 본딩되는 본딩와이어(42)의 접합점의 상기 다른 영역의 신호리드에 본딩되는 본딩와이어 접합점보다 상기 반도체기판(1)으로부터 떨어져 있는 것을 특징으로 하는 반도체장치.
  13. 제1항에 있어서, 상기 신호리드(41)를 지지하는 세라믹층(40)에 있어서 상기 기판 탑재부(10)의 각에 가까운 부분은 높고, 상기 기판 탑재부(10)의 변의 중앙부분으로 되는 만큼 낮게 하도록 단차를 형성하는 것을 특징으로 하는 반도체장치.
  14. 제2항에 있어서, 상기 신호리드(41)를 지지하는 세라믹층(40)에 있어서 상기 기판 탑재부(10)의 각에 가까운 부분은 높고, 상기 기판 탑재부(10)의 변의 중앙부분으로 되는 만큼 낮게 하도록 단차를 형성하는 것을 특징으로 하는 반도체장치.
  15. 제3항에 있어서, 상기 신호리드(41)를 지지하는 세라믹층(40)에 있어서 상기 기판 탑재부(10)의 각에 가까운 부분은 높고, 상기 기판 탑재부(10)의 변의 중앙부분으로 되는 만큼 낮게 하도록 단차를 형성하는 것을 특징으로 하는 반도체장치.
  16. 제4항에 있어서, 상기 신호리드(41)를 지지하는 세라믹층(40)에 있어서 상기 기판 탑재부(10)의 각에 가까운 부분은 높고, 상기 기판 탑재부(10)의 변의 중앙부분으로 되는 만큼 낮게 하도록 단차를 형성하는 것을 특징으로 하는 반도체장치.
  17. 제5항에 있어서, 상기 신호리드(41)를 지지하는 세라믹층(40)에 있어서 상기 기판 탑재부(10)의 각에 가까운 부분은 높고, 상기 기판 탑재부(10)의 변의 중앙부분으로 되는 만큼 낮게 하도록 단차를 형성하는 것을 특징으로 하는 반도체장치.
  18. 제6항에 있어서, 상기 신호리드(41)를 지지하는 세라믹층(40)에 있어서 상기 기판 탑재부(10)의 각에 가까운 부분은 높고, 상기 기판 탑재부(10)의 변의 중앙부분으로 되는 만큼 낮게 하도록 단차를 형성하는 것을 특징으로 하는 반도체장치.
  19. 제7항에 있어서, 상기 신호리드(41)를 지지하는 세라믹층(40)에 있어서 상기 기판 탑재부(10)의 각에 가까운 부분은 높고, 상기 기판 탑재부(10)의 변의 중앙부분으로 되는 만큼 낮게 하도록 단차를 형성하는 것을 특징으로 하는 반도체장치.
  20. 제8항에 있어서, 상기 신호리드(41)를 지지하는 세라믹층(40)에 있어서 상기 기판 탑재부(10)의 각에 가까운 부분은 높고, 상기 기판 탑재부(10)의 변의 중앙부분으로 되는 만큼 낮게 하도록 단차를 형성하는 것을 특징으로 하는 반도체장치.
  21. 제9항에 있어서, 상기 신호리드(41)를 지지하는 세라믹층(40)에 있어서 상기 기판 탑재부(10)의 각에 가까운 부분은 높고, 상기 기판 탑재부(10)의 변의 중앙부분으로 되는 만큼 낮게 하도록 단차를 형성하는 것을 특징으로 하는 반도체장치.
  22. 제10항에 있어서, 상기 신호리드(41)를 지지하는 세라믹층(40)에 있어서 상기 기판 탑재부(10)의 각에 가까운 부분은 높고, 상기 기판 탑재부(10)의 변의 중앙부분으로 되는 만큼 낮게 하도록 단차를 형성하는 것을 특징으로 하는 반도체장치.
  23. 제11항에 있어서, 상기 신호리드(41)를 지지하는 세라믹층(40)에 있어서 상기 기판 탑재부(10)의 각에 가까운 부분은 높고, 상기 기판 탑재부(10)의 변의 중앙부분으로 되는 만큼 낮게 하도록 단차를 형성하는 것을 특징으로 하는 반도체장치.
  24. 제12항에 있어서, 상기 신호리드(41)를 지지하는 세라믹층(40)에 있어서 상기 기판 탑재부(10)의 각에 가까운 부분은 높고, 상기 기판 탑재부(10)의 변의 중앙부분으로 되는 만큼 낮게 하도록 단차를 형성하는 것을 특징으로 하는 반도체장치.
  25. 제13항 내지 제24항 중 어느 한 항에 있어서, 상기 전원리드(31)를 지지하는 세라믹층(30)에 있어서 그 소정의 영역을 다른 영역보다 낮게 하여 그곳에 단차를 설치하면서 이 소정의 영역에형성되어 있는 전원리드에 본딩되는 본딩와이어(32)의 접합점은 상기 다른 영역의 전원리드에 본딩되는 본딩와이어의 접합점보다 상기반도체기판(1)으로부터 떨어져 있는 것을 특징으로 하는 반도체장치.
  26. 집접회로가 형성된 반도체기판(1)과, 주변 중앙부분에 형성된 캐비티부(11)에 상기 반도체기판이 고착되어 있는 기판 탑재부(10), 이 기판 탑재부(10)의 주면 주변부분에 그 선단이 상기 반도체기판에 대향하도록 배치되고, 신호리드(41)와 전원리드(31)를 갖춘 복수의 내부리드(31,41,61) 및, 이 내부리드(31,41,61)의 선단부와 상기 반도체기판(1)에 형성된 접속전극 또는 상기 캐비티부(11)의 전원층을 접속하는 본딩아이어(32,33,35,42,62)를 구비하고, 상기 기판 탑재부(10)는 상기 내부리드(31,41,61)를 지지하는 세라믹층(30,40,60)을 갖추고 있고, 이 세라믹층(30,40,60)에는 소정의 영역을 다른 영역보다 낮게 하여 그곳에 단차를 설치하면서 이 소정의 영역에 형성되어 있는 전원리드에 본딩되는 본딩와이어의 접합점은 상기 다른 영역의 전원리드에 본딩되는 본딩와이어의 접합점보다 상기 반도체기판(1)으로부터 떨어져 있는 것을 특징으로 하는 반도체장치.
  27. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950012574A 1994-05-19 1995-05-19 반도체장치 KR100192631B1 (ko)

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JP12964094A JP3247544B2 (ja) 1994-05-19 1994-05-19 半導体装置
JP94-129640 1994-05-19

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KR950034638A true KR950034638A (ko) 1995-12-28
KR100192631B1 KR100192631B1 (ko) 1999-06-15

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JP3825181B2 (ja) 1998-08-20 2006-09-20 沖電気工業株式会社 半導体装置の製造方法及び半導体装置
JP3609692B2 (ja) * 2000-05-24 2005-01-12 松下電器産業株式会社 高周波信号増幅装置およびその製造方法
US6879039B2 (en) * 2001-12-18 2005-04-12 Broadcom Corporation Ball grid array package substrates and method of making the same
US6847123B2 (en) * 2002-04-02 2005-01-25 Lsi Logic Corporation Vertically staggered bondpad array
DE10245452A1 (de) * 2002-09-27 2004-04-08 Infineon Technologies Ag Verfahren zum Bestimmen der Anordnung von Kontaktflächen auf der aktiven Oberseite eines Halbleiterchips
KR100546698B1 (ko) * 2003-07-04 2006-01-26 앰코 테크놀로지 코리아 주식회사 반도체 패키지의 서브스트레이트
US7466021B2 (en) * 2003-11-17 2008-12-16 Interconnect Portfolio, Llp Memory packages having stair step interconnection layers
JP2022154813A (ja) * 2021-03-30 2022-10-13 ソニーセミコンダクタソリューションズ株式会社 半導体パッケージ

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JPH073874B2 (ja) * 1987-07-22 1995-01-18 工業技術院長 半導体装置
US5008734A (en) * 1989-12-20 1991-04-16 National Semiconductor Corporation Stadium-stepped package for an integrated circuit with air dielectric
US5245214A (en) * 1991-06-06 1993-09-14 Northern Telecom Limited Method of designing a leadframe and a leadframe created thereby

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JPH07321160A (ja) 1995-12-08
JP3247544B2 (ja) 2002-01-15
US5627408A (en) 1997-05-06
KR100192631B1 (ko) 1999-06-15

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