KR890017806A - 반도체 집적회로 - Google Patents

반도체 집적회로 Download PDF

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Publication number
KR890017806A
KR890017806A KR1019890006933A KR890006933A KR890017806A KR 890017806 A KR890017806 A KR 890017806A KR 1019890006933 A KR1019890006933 A KR 1019890006933A KR 890006933 A KR890006933 A KR 890006933A KR 890017806 A KR890017806 A KR 890017806A
Authority
KR
South Korea
Prior art keywords
semiconductor chip
integrated circuit
lead portion
semiconductor integrated
inner lead
Prior art date
Application number
KR1019890006933A
Other languages
English (en)
Other versions
KR930003147B1 (ko
Inventor
마사미치 아사노
기요시 고바야시
히로시 이와하시
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR890017806A publication Critical patent/KR890017806A/ko
Application granted granted Critical
Publication of KR930003147B1 publication Critical patent/KR930003147B1/ko

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)

Abstract

내용 없음

Description

반도체 집적회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 1실시예에 따른 IC 패키지의 내부 구조를 도시해 놓은 평면도. 제 2 도는 제 1 도에 도시된 IC 패키지의 전체구조를 도시해 놓은 사시도. 제 3 도는 내지 제 7 도는 각각 본 발명의 다른 실시예에 따른 IC 패키지의 내부구조를 도시해 놓은 평면도.

Claims (2)

  1. 표면상에 복수의 패드전극(19~21)이 형성된 반도체칩(31)과, 이 반도체칩(31)을 봉입하는 패키지(34), 각각 내부리이드부(32)와 외부리이드부(35)로 구성된 복수의 리이드페리임단자 및, 이 복수의 각 리이드프레임 단자의 내부리이드부(32)의 선단부와 상기 반도체칩(31)의 표면상에 형성된 패드전극(19~21)을 접속시켜 주는 가느다란 금속선(32)을 구비한 반도체 집적회로에 있어서, 적어도 전원접압을 상기 반도체칩(31)에 공급하기 위한 리이드프레임단자의 내부리이드부(32C,32F)의 면적이 다른 내부리이드부(32)의 면적보다도 크게 되어 있는 것을 특징으로 하는 반도체 집적회로.
  2. 표면상에 복수의 패드전극(19~21)이 형성된 반도체칩(31)과, 이 반도체칩(31)을 봉입하는 패키지(34), 각각 내부리이드부(32)와 외부리이드부(35)로 구성된 복수의 리이드프레임단자 및, 이 복수의 각 리이드프레임단자의 내부리이드부(32)의 선단부와 상기 반도체칩(31)의 표면상에 형성된 패드전극(19~21)을 접속시켜 주는 가느다란 금속선(33)을 구비한 반도체 집적회로에 있어서, 적어도 전원접압을 상기 반도체칩(31)에 공급하기 위한 리이드프레임단자의 외부리이드부(35) 앞쪽의 내부리이드부가 복수의 부분(32A,32B)으로 분할되어 있는 것을 특징으로 하는 반도체 집적회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890006933A 1988-05-24 1989-05-24 반도체 집적회로 KR930003147B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63126514A JPH0666353B2 (ja) 1988-05-24 1988-05-24 半導体集積回路
JP88-126514 1988-05-24

Publications (2)

Publication Number Publication Date
KR890017806A true KR890017806A (ko) 1989-12-18
KR930003147B1 KR930003147B1 (ko) 1993-04-22

Family

ID=14937094

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890006933A KR930003147B1 (ko) 1988-05-24 1989-05-24 반도체 집적회로

Country Status (2)

Country Link
JP (1) JPH0666353B2 (ko)
KR (1) KR930003147B1 (ko)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5571030A (en) * 1978-11-24 1980-05-28 Hitachi Ltd Mounting system for semiconductor device
JPS5814544A (ja) * 1981-07-17 1983-01-27 Nec Corp モノリシツク集積回路容器
JPS60117635A (ja) * 1983-11-29 1985-06-25 Fujitsu Ltd 集積回路パッケ−ジ
JPS62134255U (ko) * 1986-02-17 1987-08-24
JPS63211658A (ja) * 1987-02-26 1988-09-02 Nec Corp 半導体装置

Also Published As

Publication number Publication date
JPH0666353B2 (ja) 1994-08-24
KR930003147B1 (ko) 1993-04-22
JPH01295429A (ja) 1989-11-29

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