KR930018702A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR930018702A
KR930018702A KR1019930001632A KR930001632A KR930018702A KR 930018702 A KR930018702 A KR 930018702A KR 1019930001632 A KR1019930001632 A KR 1019930001632A KR 930001632 A KR930001632 A KR 930001632A KR 930018702 A KR930018702 A KR 930018702A
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bonding
power supply
line
semiconductor device
supply line
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KR1019930001632A
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KR100287827B1 (ko
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다까유끼 마에다
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윌리엄 이. 힐러
텍사스 인스트루먼츠 인코포레이티드
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Abstract

결합 패드(1)의 컬럼을 따라서, 버스 바(2,3)의 본딩 단자부(2c,3c,4a,5a) 및 신호선(4,5)가 배열되고; 주요와이어링부(2a,3a)는 신호선에 관하여 3차원 교차형으로 연장되며, 그들은 버스 바의 결합 단부에 접속되어 LOC형의 IC 패키지가 형성된다. 여러 본딩 단자부와 여러 본딩 패드 사이에는 버스 바의 주요 와이어링 부분이 없다. 결과적으로는, 본딩 와이어(6,7,8,9)는 버스 바 주요 와이어링부를 뛰어넘지 않는다. 결과적으로, 본딩 와이어가 들어올려지지 않더라도, 본딩 와이어는 버스 바 주요 와이어링부에 접촉하지 않기 때문에 회로 단락이 발생되지 않는다. 그러므로 반도체 장치의 신뢰성이 높아짐은 물론이 좀더 얇게 만들 수 있다.

Description

반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 양호한 실시예로서 LOC 구조로 된 IC 패키지의 주요 부분을 도시한 부분 확대 사시도.
제2도는 IC 패키지의 주요 부분을 도시한 평면도.
제3도는 제2도의 도시된 IC 패키지의 주요 성분을 선 Ⅲ-Ⅲ을 따라 절취하여 도시한 단면도.

Claims (9)

  1. 리드 프레임의 본딩 단자부에 접속된 다중 본딩 패드들은 반도체 칩의 회로-형성 면 상에 거의 원주형으로 배열되고; 리드 프레임의 다중 신호선용의 상기 본딩 단자부 및 다중전원선용 본딩 단자부는 상기 본딩 패드열 주변을 따라서 상기 반도체 칩 상의 전기 절연체를 통해 결합되고; 상기 전원선의 주요 부분은 상기 신호선과의 전기 절연을 위해 3차원 교차형으로 연장되며; 상기 전원선의 상기 주요 부분과 상기 전원선의 본딩 단자부는 연속해서 일체로 형성되고; 상기 여러 본딩 단자부 및 상기 본딩 패드는 전기적으로 접속되는 것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 상기 전원선의 본딩 단자부에 접속되 브랜치를 접철함으로써, 상기 전원선의 주요 부분을 신호선에 관하여 3차원 교차하도록 만들 수 있을 것을 특징으로 하는 장치.
  3. 제1항에 있어서, 신호선 상에 계단부를 위해 전원선의 주요 부분으로 부터 분기된 전원선의 본딩 단자부에 접속된 브랜치부를 약 180°만큼 뒤로 접철함으로써, 전원선의 주요 부분이 신호선 아래로 교차하는 것을 특징으로 하는 반도체 장치.
  4. 제2또는 3항에 있어서, 신호선의 본딩 단자부와 전원선의 접철된 부분에 접속된 리드부로부터, 이 리드부의 팁 부분이 반도체 장치의 주 본체 밖으로 나와 외부 리드가 되고, 외부 리드들은 반도체 장치의본체에 관하여 거의 동일한 레벨로 외부로 나와 있는 것을 특징으로 하는 반도체 장치.
  5. 제1 내지 4항 중 임의의 한 항에 있어서, 전원선과 신호선이 본딩 패드들의 열에 관하여 대칭이 되게 설정되는 것을 특징으로 하는 반도체 장치.
  6. 제1 내지 4항 중 임의의 한 항에 있어서, 전원선과 신호선의 본딩 단자부들과 본딩 패드들이 직접 본딩 와이어에 의해 연결되어 있는 것을 특징으로 하는 반도체 장치.
  7. 제1내지 6항중 임의의 한 항에 있어서, 홈이 신호선의 본딩 단자부에 만들어지고; 전원선의 주 섹션의 일부가 상기 홈 내부로 삽입되고; 이 홈에 삽입된 전원선의 주 섹션의 일부가 절연 재료를 통해 홈의 저부면과 접촉하는 것을 특징으로 하는 반도체 장치.
  8. 제2 내지 7항 중 임의의 한 항에 있어서, 전원선의 주 섹션은 일부는 줄어들고 상기 전원선의 주 섹션은 패드 열 주변에 위치하는 것을 특징으로 하는 반도체 장치.
  9. 제1 내지 8항 중 임의의 한 항에 있어서, 반도체 장치가 LOC(리드 온 칩)구조의 IC패키지인 것을 특징으로 하는 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930001632A 1992-02-07 1993-02-06 반도체 장치 KR100287827B1 (ko)

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JP4057066A JPH05218281A (ja) 1992-02-07 1992-02-07 半導体装置
JP92-57066 1992-02-07

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KR100287827B1 KR100287827B1 (ko) 2001-04-16

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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
EP0594299A3 (en) * 1992-09-18 1994-11-23 Texas Instruments Inc Multi-layer circuit grid unit and integrated circuit method.
JP3290869B2 (ja) * 1995-11-16 2002-06-10 株式会社東芝 半導体装置
US6462404B1 (en) 1997-02-28 2002-10-08 Micron Technology, Inc. Multilevel leadframe for a packaged integrated circuit
US5780923A (en) 1997-06-10 1998-07-14 Micron Technology, Inc. Modified bus bar with Kapton™ tape or insulative material on LOC packaged part
US6580157B2 (en) * 1997-06-10 2003-06-17 Micron Technology, Inc. Assembly and method for modified bus bar with Kapton™ tape or insulative material in LOC packaged part
US6144089A (en) 1997-11-26 2000-11-07 Micron Technology, Inc. Inner-digitized bond fingers on bus bars of semiconductor device package
JP3063847B2 (ja) * 1998-05-01 2000-07-12 日本電気株式会社 リードフレーム及びそれを用いた半導体装置
JP2000100814A (ja) * 1998-09-18 2000-04-07 Hitachi Ltd 半導体装置
JP2009289969A (ja) * 2008-05-29 2009-12-10 Nec Electronics Corp リードフレーム
US8608738B2 (en) 2010-12-06 2013-12-17 Soulor Surgical, Inc. Apparatus for treating a portion of a reproductive system and related methods of use
ITTO20150231A1 (it) 2015-04-24 2016-10-24 St Microelectronics Srl Procedimento per produrre lead frame per componenti elettronici, componente e prodotto informatico corrispondenti
JP7070070B2 (ja) * 2018-05-15 2022-05-18 株式会社デンソー 半導体装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4791473A (en) * 1986-12-17 1988-12-13 Fairchild Semiconductor Corporation Plastic package for high frequency semiconductor devices
US5068712A (en) * 1988-09-20 1991-11-26 Hitachi, Ltd. Semiconductor device
JPH088330B2 (ja) * 1989-07-19 1996-01-29 日本電気株式会社 Ｌｏｃ型リードフレームを備えた半導体集積回路装置
US4965654A (en) * 1989-10-30 1990-10-23 International Business Machines Corporation Semiconductor package with ground plane
JP2567961B2 (ja) * 1989-12-01 1996-12-25 株式会社日立製作所 半導体装置及びリ−ドフレ−ム
JP2528991B2 (ja) * 1990-02-28 1996-08-28 株式会社日立製作所 樹脂封止型半導体装置及びリ―ドフレ―ム
JPH04348045A (ja) * 1990-05-20 1992-12-03 Hitachi Ltd 半導体装置及びその製造方法
US5227232A (en) * 1991-01-23 1993-07-13 Lim Thiam B Conductive tape for semiconductor package, a lead frame without power buses for lead on chip package, and a semiconductor device with conductive tape power distribution
US5206536A (en) * 1991-01-23 1993-04-27 Texas Instruments, Incorporated Comb insert for semiconductor packaged devices
US5286999A (en) * 1992-09-08 1994-02-15 Texas Instruments Incorporated Folded bus bar leadframe
US5563443A (en) * 1993-03-13 1996-10-08 Texas Instruments Incorporated Packaged semiconductor device utilizing leadframe attached on a semiconductor chip
US5545920A (en) * 1994-09-13 1996-08-13 Texas Instruments Incorporated Leadframe-over-chip having off-chip conducting leads for increased bond pad connectivity

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DE69321276D1 (de) 1998-11-05
EP0560487B1 (en) 1998-09-30
KR100287827B1 (ko) 2001-04-16
US5804871A (en) 1998-09-08
JPH05218281A (ja) 1993-08-27
US5550401A (en) 1996-08-27
EP0560487A3 (en) 1993-12-08
EP0560487A2 (en) 1993-09-15
SG49206A1 (en) 1998-05-18
DE69321276T2 (de) 1999-02-18

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