JP7070070B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP7070070B2 JP7070070B2 JP2018093960A JP2018093960A JP7070070B2 JP 7070070 B2 JP7070070 B2 JP 7070070B2 JP 2018093960 A JP2018093960 A JP 2018093960A JP 2018093960 A JP2018093960 A JP 2018093960A JP 7070070 B2 JP7070070 B2 JP 7070070B2
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- signal
- semiconductor element
- signal terminal
- electrodes
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- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Inverter Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Power Conversion In General (AREA)
Description
12:第1導体板
14:第2導体板
16:封止体
22、24、26:半導体素子
22a、24a、26a:上面電極
22b、24b、24c:下面電極
22c、24c、26c:信号電極
28:温度センサ
30:電流センサ
32:第1電力端子
34:第2電力端子
36:信号端子
36a:第1信号端子
36b:第2信号端子
36c:第3信号端子
36d:共通信号端子
37:側方延伸部
38:支持部
40:ボンディングワイヤ
K:第2温度信号電極
A:第1温度信号電極
G:ゲート信号電極
SE:電流信号電極
KE:基準電圧信号電極
Claims (9)
- 複数の信号電極を有する第1半導体素子と、
複数の信号電極を有する第2半導体素子と、
前記第1半導体素子及び前記第2半導体素子を封止する封止体と、
前記封止体から突出する複数の信号端子と、を備え、
前記複数の信号端子には、第1信号端子と、第2信号端子と、共通信号端子が含まれており、
前記第1信号端子は、前記封止体の内部において、前記第1半導体素子の前記複数の信号電極の一つに接続されており、
前記第2信号端子は、前記封止体の内部において、前記第2半導体素子の前記複数の信号電極の一つに接続されており、
前記共通信号端子は、前記封止体の内部において、前記第1半導体素子の前記複数の信号電極の他の一つと、前記第2半導体素子の前記複数の信号電極の他の一つとの両者に接続されており、
前記共通信号端子は、前記複数の信号端子の配列方向に沿って延びる側方延伸部を、前記封止体の内部に有しており、
前記側方延伸部は、前記共通信号端子に隣接する他の前記信号端子と立体交差して、当該他の信号端子の反対側まで延びている、
半導体装置。 - 複数の信号電極を有する第1半導体素子と、
複数の信号電極を有する第2半導体素子と、
前記第1半導体素子及び前記第2半導体素子を封止する封止体と、
前記封止体から突出する複数の信号端子と、
支持部と、を備え、
前記複数の信号端子には、第1信号端子と、第2信号端子と、共通信号端子が含まれており、
前記第1信号端子は、前記封止体の内部において、前記第1半導体素子の前記複数の信号電極の一つに接続されており、
前記第2信号端子は、前記封止体の内部において、前記第2半導体素子の前記複数の信号電極の一つに接続されており、
前記共通信号端子は、前記封止体の内部において、前記第1半導体素子の前記複数の信号電極の他の一つと、前記第2半導体素子の前記複数の信号電極の他の一つとの両者に接続されており、
前記共通信号端子は、前記複数の信号端子の配列方向に沿って延びる側方延伸部を、前記封止体の内部に有しており、
前記支持部は、前記封止体の内部において、前記側方延伸部に接続されているとともに、前記第1信号端子と前記第2信号端子の間において、前記封止体から突出している、
半導体装置。 - 前記側方延伸部は、前記共通信号端子に隣接する他の前記信号端子の反対側まで延びる、請求項2に記載の半導体装置。
- 前記側方延伸部は、前記共通信号端子に隣接する他の前記信号端子と立体交差する、請求項3に記載の半導体装置。
- 前記側方延伸部は、前記共通信号端子に隣接する他の前記信号端子と、当該他の信号端子が接続された前記第1半導体素子又は前記第2半導体素子との間に位置する、請求項3に記載の半導体装置。
- 前記封止体によって封止されているとともに、複数の信号電極を有する第3半導体素子をさらに備え、
前記共通信号端子は、前記封止体の内部において、前記第3半導体素子の前記複数の信号電極の一つにさらに接続されている、請求項1から5のいずれか一項に記載の半導体装置。 - 前記第1半導体素子と前記第2半導体素子とのそれぞれは、温度検出部を有し、
前記第1半導体素子の前記複数の信号電極と、前記第2半導体素子の前記複数の信号電極とのそれぞれは、前記温度検出部の一端に接続された第1温度信号電極と、前記温度検出部の他端に接続された第2温度信号電極とを有し、
前記第1信号端子は、前記第1半導体素子の前記第1温度信号電極に接続されており、
前記第2信号端子は、前記第2半導体素子の前記第1温度信号電極に接続されており、
前記共通信号端子は、前記第1半導体素子の前記第2温度信号電極と、前記第2半導体素子の前記第2温度信号電極との両者に接続されている、請求項1から6のいずれか一項に記載の半導体装置。 - 前記第1半導体素子と前記第2半導体素子とのそれぞれは、電流検出部を有し、
前記第1半導体素子の前記複数の信号電極と、前記第2半導体素子の前記複数の信号電極とのそれぞれは、前記電流検出部の一端に接続された電流信号電極と、前記電流信号電極が出力する信号に対する基準電圧を出力する基準電圧信号電極とを有し、
前記第1信号端子は、前記第1半導体素子の前記電流信号電極に接続されており、
前記第2信号端子は、前記第2半導体素子の前記電流信号電極に接続されており、
前記共通信号端子は、前記第1半導体素子の前記基準電圧信号電極と、前記第2半導体素子の前記基準電圧信号電極との両者に接続されている、請求項1から6のいずれか一項に記載の半導体装置。 - 前記第1半導体素子と前記第2半導体素子とのそれぞれは、ゲートを有するスイッチング素子であり、
前記第1半導体素子の前記複数の信号電極と、前記第2半導体素子の前記複数の信号電極とのそれぞれは、前記ゲートに接続されたゲート信号電極を有し、
前記共通信号端子は、前記封止体の内部において、前記第1半導体素子の前記ゲート信号電極と、前記第2半導体素子の前記ゲート信号電極とに接続されている、請求項1から6のいずれか一項に記載の半導体装置。
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WO2014046058A1 (ja) | 2012-09-20 | 2014-03-27 | ローム株式会社 | パワーモジュール半導体装置およびインバータ装置、およびパワーモジュール半導体装置の製造方法、および金型 |
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WO2017169693A1 (ja) | 2016-04-01 | 2017-10-05 | 三菱電機株式会社 | 半導体モジュール |
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JP2003142689A (ja) | 2001-11-01 | 2003-05-16 | Mitsubishi Electric Corp | 半導体装置 |
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WO2015001648A1 (ja) | 2013-07-04 | 2015-01-08 | 三菱電機株式会社 | 半導体装置の製造方法、半導体装置 |
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