CN104282652A - 具有源极向下和感测配置的半导体裸片和封装体 - Google Patents

具有源极向下和感测配置的半导体裸片和封装体 Download PDF

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Publication number
CN104282652A
CN104282652A CN201410327670.4A CN201410327670A CN104282652A CN 104282652 A CN104282652 A CN 104282652A CN 201410327670 A CN201410327670 A CN 201410327670A CN 104282652 A CN104282652 A CN 104282652A
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pad
semiconductor body
sensing
electrically connected
conductive via
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CN104282652B (zh
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R·奥特雷姆巴
J·赫格劳尔
G·诺鲍尔
M·珀尔齐尔
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Abstract

一种半导体裸片，包括：半导体主体；晶体管器件，布置在所述半导体主体中并且具有栅极、源极和漏极；感测器件，布置在所述半导体主体中并且可操作用于感测与所述晶体管器件相关联的参数。该裸片进一步包括：源极焊盘，在所述半导体主体的第一侧处并且电连接到所述晶体管器件的源极；漏极焊盘，在与所述第一侧相对的所述半导体主体的第二侧处并且电连接到所述晶体管器件的漏极；以及感测焊盘，在所述半导体主体的第二侧处并且与所述漏极焊盘间隔开。所述感测焊盘电连接到所述感测器件。还公开了对应的封装体和制造方法。

Description

具有源极向下和感测配置的半导体裸片和封装体
技术领域
本申请涉及半导体裸片和对应的封装体，并且更具体地涉及具有感测的半导体裸片和对应的封装体。
背景技术
常规垂直功率晶体管裸片的漏极在裸片的背侧处直接连接到裸片焊盘。裸片的漏极焊盘直接连接到封装体的漏极引线。在许多应用中，期望感测晶体管源极电流或温度。用于感测源极电流或温度的常规技术典型地包含在晶体管裸片的前侧处与源极焊盘隔开地提供专用感测焊盘。裸片的前侧在裸片键合工艺期间被倒装，并且专用源极焊盘被直接焊接或胶粘。这样的裸片/封装体配置需要针对有关感测再分布的专用裸片焊盘设计，增加了封装体设计复杂度和封装体成本。
发明内容
根据半导体裸片的一个实施例，半导体裸片包括半导体主体。晶体管器件布置在半导体主体中。晶体管器件具有栅极、源极和漏极。感测器件也布置在半导体主体中。感测器件可操作用于感测与晶体管器件相关联的参数，例如诸如温度或源极电流。在半导体主体的第一侧处的源极焊盘电连接到晶体管器件的源极。在半导体主体的与第一侧相对的第二侧处的漏极焊盘电连接到晶体管器件的漏极。在半导体主体的第二侧处并与漏极焊盘间隔开的感测焊盘电连接到感测器件。
根据制造半导体裸片的方法的一个实施例，该方法包括：在半导体主体中形成晶体管器件，所述晶体管器件具有栅极、源极和漏极；在所述半导体主体中形成感测器件，所述感测器件可操作用于感测与所述晶体管器件相关联的参数；在所述半导体主体的第一侧处形成源极焊盘、在所述半导体主体的与所述第一侧相对的第二侧处形成漏极焊盘并且在所述半导体主体的第二侧处与所述漏极焊盘间隔开地形成感测焊盘；将所述源极焊盘电连接到所述晶体管器件的源极；将所述漏极焊盘电连接到所述晶体管器件的漏极；以及将所述感测焊盘电连接到所述感测器件。
根据半导体封装体的一个实施例，封装体包括第一裸片叶片(paddle)和半导体裸片。半导体裸片包括半导体主体，半导体主体具有面对所述第一裸片叶片的第一侧和与所述第一裸片叶片远离面对的第二侧。布置在所述半导体主体中的晶体管器件具有栅极、源极和漏极。也布置在所述半导体主体中的感测器件可操作用于感测与所述晶体管器件相关联的参数。在所述半导体主体的第一侧处的源极焊盘附接到所述第一裸片叶片并且电连接到所述晶体管器件的源极。在所述半导体主体的与所述第一侧相对的第二侧处的漏极焊盘电连接到所述晶体管器件的漏极。在所述半导体主体的第二侧处并与所述漏极焊盘间隔开的感测焊盘电连接到所述感测器件。
本领域技术人员通过阅读下列详细描述并通过查看附图将认识到附加特征和优势。
附图说明
图中的组件不一定按比例绘制，而是强调图示本发明的原理。而且，在图中类似的参考标号标示对应的部分。在附图中：
图1图示了具有源极向下和感测配置的半导体裸片的一个实施例的截面图；
图2图示了具有源极向下和感测配置的半导体裸片的另一实施例的截面图；
图3A至图3C图示了根据第一实施例的具有源极向下和感测配置的半导体裸片的不同透视图；
图4A至图4C图示了根据第二实施例的具有源极向下和感测配置的半导体裸片的不同透视图；
图5图示了包括具有源极向下和感测配置的半导体裸片的半导体封装体的一个实施例的俯视平面图；
图6图示了示例性半桥接电路的电路示意图；以及
图7图示了包括具有源极向下和感测配置的半导体裸片的半导体封装体的另一实施例的俯视平面图。
具体实施方式
这里描述的实施例提供具有源极向下配置的功率半导体裸片，其中裸片的源极焊盘附接到封装体的裸片叶片，并且漏极焊盘和专用感测焊盘设置在裸片的相对侧处。可以使用导电过孔将感测器件电连接到在裸片相对(漏极)侧处的专用感测焊盘，该感测器件可以布置在与功率晶体管的源极相同的裸片侧处。本文描述的源极向下半导体裸片实施例减少切换损耗，由此降低静态损耗。
图1图示了根据一个实施例的半导体裸片的局部截面图。该裸片包括半导体主体100。半导体主体100可以由适于制造半导体器件的任意半导体材料制成。举例而言，这种材料的示例包括但不限于：元素半导体材料，诸如硅(Si)或锗(Ge)；IV族化合物半导体材料，诸如碳化硅(SiC)或锗硅(SiGe)；二元、三元或四元III-V半导体材料，诸如氮化镓(GaN)、砷化镓(GaAs)、磷化钾(GaP)、磷化铟(InP)、铟镓磷(InGaP)、铝镓氮(AlGaN)、铝铟氮(AlInN)、铟镓氮(InGaN)、铝镓铟氮(AlGaInN)或铟镓砷磷(InGaAsP)；以及二元或三元II-VI半导体材料，诸如碲化镉(CdTe)和碲镉汞(HgCdTe)。
晶体管器件和感测器件二者布置在半导体主体100中。晶体管器件具有栅极102、源极104和漏极106。源极104布置在晶体管器件的漂移区域108中并且通过相反导电类型的体区域110与晶体管器件的漂移区域108隔开。晶体管器件的栅极102通过诸如SiO2之类的绝缘材料112与周围的半导体材料隔开。晶体管器件是根据本实施例的沟槽器件，其中栅极102布置在沟槽114中。通过沟槽绝缘材料112与栅极102隔开的场板116可以布置在栅极102下方的沟槽114中。备选地，栅极102可以按照平面栅极布局形成在半导体主体100的顶侧101上。在每种情况中，感测器件可操作用于感测与晶体管器件相关联的参数，诸如晶体管器件的温度或源极电流。在一个实施例中，感测器件是晶体管器件的缩小的更小版本，并且感测器件的对应区域在添加有撇号(’)的情况下具有与晶体管器件相同的图参考标号。
半导体裸片进一步包括在半导体主体100的第一(顶)侧101处的源极焊盘130和在半导体主体100的与第一侧101相对的第二(底)侧103处的漏极焊盘和专用感测焊盘150。源极焊盘130电连接到晶体管器件的源极104并且漏极焊盘140电连接到晶体管器件的漏极106。感测焊盘150在裸片的底侧103处与漏极焊盘140间隔开并且电连接到感测器件。
在图1所示的实施例中，晶体管器件是垂直晶体管器件。源极104布置在半导体主体100的顶侧101处，而漏极106布置在半导体主体100的底侧103处。源极焊盘130通过导电过孔(如图1所示)在半导体主体100的顶侧101处电连接到源极104，该导电过孔通过层间电介质层160从源极焊盘130延伸到晶体管器件的源极104。漏极焊盘140在半导体主体100的底侧103处连接到晶体管器件的漏极106。根据本实施例，电流在垂直方向上流过在源极104和漏极106之间的半导体主体100。诸如酰亚胺之类的钝化层162可以在顶侧101处设置在半导体主体100上。源极金属再分布层164通过导电过孔166连接到主晶体管器件的源极104，导电过孔166延伸通过层间电介质层160，从而将源极金属再分布层164与半导体主体100隔开。
在一个实施例中，感测焊盘150电连接到感测器件的源极104’并且感测器件感测主晶体管器件的源极电流。根据本实施例，裸片包括源极感测金属再分布层170，该源极感测金属再分布层170通过导电过孔172连接到感测器件的源极104’。导电过孔172延伸通过层间电介质层160，该层间电介质层160将感测再分布层170与半导体主体100隔开。
感测器件的源极感测金属再分布层170可以在半导体主体100的顶侧101处通过第一导电过孔180电连接到半导体主体100的底侧103处的感测焊盘150，该第一导电过孔180从顶侧101延伸到半导体主体100中。第一导电过孔180与半导体主体100的第二侧103处的感测焊盘150对准并且朝向感测焊盘150延伸。半导体主体100具有特定厚度(Tboby)，并且第一导电过孔180延伸到半导体主体100中的某深度(Dvia)，该深度小于主体100的厚度。就此而言，第一导电过孔180在垂直方向上通过半导体主体100的高掺杂区域107与感测焊盘150间隔开。垂直方向通常垂直于半导体主体100的主侧101、103。感测器件的源极感测金属再分布层170通过导电过孔182连接到第一导电过孔180，该导电过孔182延伸通过层间电介质层160，该层间电介质层160将感测再分布层170与半导体主体100隔开。感测焊盘150通过第一导电过孔180和插入在第一导电过孔180与感测焊盘150之间的半导体主体100的高掺杂区域107电连接到半导体主体100的顶侧101处的感测器件的源极感测金属再分布层170。第一导电过孔180的侧部181可以通过诸如氧化物之类的绝缘材料184与周围的半导体材料绝缘。在一个实施例中，半导体主体100包括硅，并且第一导电过孔180是包括多晶硅或金属的所谓的硅通孔。
可以设置至少一个附加导电过孔190，该至少一个附加导电过孔190从第一侧101延伸通过半导体主体100到第二侧103并且与第一导电过孔180间隔开。附加导电过孔190在半导体主体100的整个厚度(Tboby)上延伸，并且通过诸如氧化物之类的绝缘材料192与周围的半导体材料绝缘。附加导电过孔190提供器件隔离。为此，附加导电过孔190可以通过延伸通过层间电介质层160的导电过孔194连接到半导体主体100的顶侧101处的感测再分布层170。在一个实施例中，半导体主体100包括硅，并且附加导电过孔190是包括多晶硅或金属的所谓的硅通孔。
在图1所示的实施例中，感测焊盘150通过诸如氧化物之类的绝缘材料196与半导体主体100的第二侧103处的附加导电过孔190绝缘。绝缘材料196也将感测焊盘150与漏极焊盘140隔开。
图2图示了根据另一实施例的半导体裸片的局部截面图。图2所示的实施例类似于图1所示的实施例，但是半导体主体100的底侧103处的感测焊盘150也接触主体100的底侧103处的附加导电过孔190。
图3A至图3C图示了图1或图2所示的半导体裸片的不同透视图。图3A图示了半导体裸片的俯视平面图，图3B示出了不具有裸片焊盘和层间电介质的俯视平面图，图3C示出了半导体裸片的底部平面图。根据本实施例，栅极焊盘200设置在半导体主体100的顶侧处并且与源极焊盘130间隔开。栅极焊盘200电连接到主晶体管器件的栅极102。在图3B中，栅极焊盘连接到栅极金属再分布层202，栅极金属再分布层202与感测器件的源极感测金属再分布层170隔开(隔离)。通过导电过孔(为便于图示，未示出)形成至主晶体管器件的栅极102的电连接，该导电过孔从栅极金属再分布层202通过层间电介质层160延伸到晶体管栅极102，该层间电介质层160将栅极金属再分布层202与半导体主体100隔开。
在图3B中还示出的是源极金属再分布层204(图1和图2中的区域164)，该源极金属再分布层204通过导电过孔(图1和图2中的区域172)连接到主晶体管器件的源极104，该导电过孔从源极金属再分布层204通过层间电介质层160延伸到晶体管源极104。还示出的是感测器件的感测线206和抽头线208。在感测器件是缩放的且更小版本的晶体管器件并且感测器件可操作用于感测晶体管器件的源极电流的情况中，感测线206连接到更小的感测晶体管的源极104’并且抽头线208连接到更大的主晶体管器件的源极电位。感测线206可以具有与图1和图2所示的源极感测金属再分布层170相同或相似的构造。抽头线208可以具有与感测线206相同或相似的构造，除了抽头线连接到主晶体管器件的源极电位而不是感测器件的源极104’。
在如图3C所示的半导体主体100的底侧103处，第一导电过孔210从顶侧101向第一感测焊盘212延伸到半导体主体100中。第一导电过孔210可以具有与图1和图2所示的过孔180相同或相似的构造，并且第一感测焊盘212可以具有与图1和图2所示的感测焊盘150相同或相似的构造。如先前这里描述的那样，第一感测焊盘212通过第一导电过孔210和垂直插入在第一导电过孔210与第一感测焊盘212之间的半导体主体100的高掺杂区域电连接到抽头线208。
在如图3C所示的半导体主体100的底侧103处，第二导电过孔214类似地从顶侧101向第二感测焊盘216延伸到半导体主体100中。第二导电过孔214可以具有与图1和图2所示的过孔180相同或相似的构造，并且第一感测焊盘212可以具有与图1和图2所示感测焊盘150相同或相似的构造。如先前这里描述的那样，第二感测焊盘216通过第二导电过孔214和垂直插入在第二导电过孔214与第二感测焊盘216之间的半导体主体100的高掺杂区域电连接到感测线206。裸片焊盘140和感测焊盘212、216通过诸如酰亚胺之类的钝化层在半导体主体100的底侧103处彼此隔离，为容易图示起见，在图3C中未示出钝化层(例如参见图1和图2中的层196)。
图4A至图4C图示了根据另一实施例的图1或图2所示半导体裸片的不同透视图。图4A图示了半导体裸片的俯视平面图，图4B示出了不具有裸片焊盘和层间电介质的俯视平面图，图4C示出了半导体裸片的底部平面图。图4A至图4C所示的实施例类似于图3A至图3C所示的实施例，但栅极焊盘200设置在具有漏极焊盘140和感测焊盘212、216的半导体主体100的底侧103处，而不是具有源极焊盘130的半导体主体100的顶侧101处。为此，如图4B和图4C所示，设置附加导电过孔218用于将半导体主体100的顶侧101处的栅极金属再分布层202与半导体主体100的底侧103处的栅极焊盘200连接。根据本实施例，如图4A所示，仅源极焊盘130布置在半导体主体100的顶侧101处。漏极焊盘140、栅极焊盘200和感测焊盘212、216均例如通过钝化层彼此隔离地设置在半导体主体100的底侧103处，该钝化层诸如酰亚胺，为容易图示起见未示出该钝化层(例如参见图1和图2中的层196)。
这里描述的制造半导体裸片的方法包括：在半导体主体中形成晶体管器件，所述晶体管器件具有栅极、源极和漏极；在所述半导体主体中形成感测器件，所述感测器件可操作用于感测与所述晶体管器件相关联的参数；在所述半导体主体的第一侧处形成源极焊盘、在所述半导体主体的与所述第一侧相对的第二侧处形成漏极焊盘并且在所述半导体主体的第二侧处与所述漏极焊盘间隔开地形成感测焊盘；将所述源极焊盘电连接到所述晶体管器件的源极；将所述漏极焊盘电连接到所述晶体管器件的漏极；以及将所述感测焊盘电连接到所述感测器件。
通过形成第一导电过孔，可以将感测焊盘电连接到感测器件，该第一导电过孔从第一侧延伸到半导体主体中并且通过半导体主体的高掺杂区域与感测焊盘间隔开。感测焊盘通过第一导电过孔和插入在第一导电过孔与感测焊盘之间的半导体主体的高掺杂区域电连接到感测器件。
可以在半导体主体的第二侧处并且与另一感测焊盘和漏极焊盘间隔开地形成附加感测焊盘。例如通过形成如下导电过孔，可以将附加感测焊盘电连接到晶体管器件的源极，该导电过孔从第一侧延伸到半导体主体中并且通过半导体主体的高掺杂区域与附加感测焊盘间隔开。附加感测焊盘通过该导电过孔和插入在该导电过孔与附加感测焊盘之间的半导体主体的高掺杂区域电连接到晶体管器件的源极。
本文描述的半导体裸片可以组装成封装体。当将半导体裸片组装成封装体时，裸片的源极侧面向下放置在封装体中，使得焊盘附接到封装体的裸片叶片。漏极焊盘和感测焊盘与裸片叶片远离面对。如先前这里描述的那样，栅极焊盘可以在裸片的源极侧或漏极侧处。
图5图示了半导体封装体的俯视平面图，该半导体封装体包括图4A至图4C所示的半导体裸片300和附加半导体裸片302、304。为便于说明和图示，仅诸如盖体和模制化合物或其它密封材料之类的特定封装体部分未示出，并且由包括在图5的封装体中的组件实现的电路是如图6所示的半桥接转换器电路。半桥接电路包括对应于裸片300的低侧晶体管(LS)、对应于裸片302的高侧晶体管(HS)和耦合在半桥接电路的正向输入(VIN)与负向输入(PGND)之间的输入电容器(Cin)。在一些配置中负向输入可以接地。低侧晶体管LS对应于图4A至图4C所示的半导体裸片300，其中栅极焊盘200和源极焊盘130布置在裸片300的同一侧处。在图6所示的示例性电路图中，晶体管是均具有栅极(G)端子、漏极(D)端子和源极(S)端子的MOSFET。
低侧晶体管LS的栅极端子、漏极端子和源极端子分别对应于图4A至图4C所示的栅极焊盘200、漏极焊盘140和源极焊盘130。高侧晶体管HS的漏极端子电连接到半桥接电路的正向输入(VIN)。高侧晶体管HS的源极端子电连接到低侧晶体管LS的漏极端子以形成半桥接电路的输出(SW)。低侧晶体管LS的源极端子电连接到负向输入(PGND)。晶体管栅极(G)用作控制信号输入(IN1，IN2)。代替MOSFET，可以使用IGBT，其中IGBT的集电极连接将对应于MOSFET的漏极连接，并且IGBT的发射极连接将对应于MOSFET的源极连接。封装体还包括具有各种(信号和功率)输入和输出(例如PHASE、GL、BOOT、AGND、VCC、PWM、EN、PHFLT#、PVCC、CGND、GL)的控制器裸片304，用于控制半桥接电路的操作。通常包括在封装体中的半导体裸片的类型和数目依赖于封装体设计用于的特定应用，并且在每种情况下可以使用这里描述的裸片间互连的实施例。
封装体还包括第一裸片叶片306和第二裸片叶片308。低侧晶体管裸片300的源极焊盘130附接到第一裸片叶片306并电连接到包括在裸片300中的低侧晶体管LS的源极端子。控制器裸片304还具有面对第一裸片叶片306并连接到第一裸片叶片306的焊盘。低侧晶体管裸片300的漏极焊盘140布置在与第一裸片叶片306远离面对的裸片300的相对侧处。漏极焊盘140电连接到低侧晶体管的漏极(D)。感测焊盘212、216和栅极焊盘300布置在与漏极焊盘140相同的裸片300侧处，并与漏极焊盘140间隔开。因此仅低侧晶体管裸片300的源极焊盘130面对第一裸片叶片306。键合导线漏极310将低侧晶体管裸片300的栅极焊盘200和感测焊盘212、216连接到控制器裸片304。低侧晶体管裸片300的漏极焊盘140通过金属夹312连接到封装体的输出引线(SW)。
高侧晶体管裸片302的漏极焊盘(视线之外)连接到封装体的第二裸片叶片308。键合导线连接310设置在高侧晶体管裸片302的栅极焊盘314与控制器裸片304的一个或多个对应焊盘316之间。键合导线连接310也设置在裸片300、302、304与封装体的各种引线之间。高侧晶体管裸片302的源极焊盘316与第二裸片叶片308远离面对并且通过金属夹318连接到低侧晶体管裸片300的漏极焊盘140，以形成图6所示的半桥接电路连接(为便于图示，从图5中省略输入电容器Cin)。根据图6的实施例，低侧晶体管裸片300的栅极焊盘200布置在与漏极焊盘140和感测焊盘212、216相同的裸片300侧处。就此而言，低侧晶体管裸片300的栅极焊盘200与第一裸片叶片306远离面对。低侧晶体管裸片300的栅极焊盘200通过一个或多个键合导线连接310连接到控制器裸片304的对应焊盘316。
图7图示了与图5所示实施例类似的半导体封装体的另一实施例的俯视平面图，但低侧晶体管裸片300对应于图3A至图3C所示的半导体裸片，而不是图4A至图4C所示的半导体裸片。根据本实施例，低侧晶体管裸片300的栅极焊盘200布置在与源极焊盘130相同的裸片侧处。就此而言，根据本实施例，低侧晶体管裸片300的栅极焊盘200面向第一裸片叶片306。栅极焊盘200与源极焊盘130间隔开，并附接到与第一裸片叶片306相同平面中的封装体的引线(GL)。在图5和图7二者中，低侧晶体管裸片以具有感测的源极向下配置附接到封装体的裸片叶片。
为便于描述，使用诸如“下方”、“之下”、“更低”、“上方”、“上面”等之类的空间相对术语来说明一个元件相对于第二元件的定位。除了与图中描绘的方向不同的方向之外，这些术语旨在于涵盖器件的不同方向。此外，也使用诸如“第一”、“第二”等的术语来描述各种元件、区域、部分等并且也并不旨在于进行限定。贯穿整个描述，类似的术语指代类似的元件。
如这里使用的，术语“具有”、“含有”、“包括”、“包含”等是开放式术语，指示所述元件或特征的存在，而并不排除附加的元件或特征。除非上下文另外清楚指出，否则冠词“一个”、“一”和“该”旨在于包括复数以及单数。
考虑到上述变型和应用的范围，应理解到的是，本发明并不由前面的描述限定，也不由附图限定。相反，本发明仅由下面的权利要求和其合法等同方案限定。

Claims (22)

1.一种半导体裸片，包括：
半导体主体；
晶体管器件，布置在所述半导体主体中并且具有栅极、源极和漏极；
感测器件，布置在所述半导体主体中并且可操作用于感测与所述晶体管器件相关联的参数；
源极焊盘，在所述半导体主体的第一侧处并且电连接到所述晶体管器件的所述源极；
漏极焊盘，在所述半导体主体的与所述第一侧相对的第二侧处并且电连接到所述晶体管器件的所述漏极；以及
感测焊盘，在所述半导体主体的第二侧处并且与所述漏极焊盘间隔开，所述感测焊盘电连接到所述感测器件。
2.根据权利要求1所述的半导体裸片，进一步包括第一导电过孔，所述第一导电过孔从所述第一侧延伸到所述半导体主体中并且通过所述半导体主体的高掺杂区域与所述感测焊盘间隔开，其中所述感测焊盘通过所述第一导电过孔和插入在所述第一导电过孔和所述感测焊盘之间的所述半导体主体的高掺杂区域电连接到所述感测器件。
3.根据权利要求2所述的半导体裸片，进一步包括至少一个附加导电过孔，所述至少一个附加导电过孔从所述第一侧延伸通过所述半导体主体到所述第二侧并与所述第一导电过孔间隔开。
4.根据权利要求3所述的半导体裸片，其中所述感测焊盘接触在所述半导体主体的第二侧处的所述至少一个附加导电过孔。
5.根据权利要求3所述的半导体裸片，其中所述感测焊盘与在所述半导体主体的第二侧处的所述至少一个附加导电过孔绝缘。
6.根据权利要求2所述的半导体裸片，进一步包括：
绝缘层，在所述半导体主体的所述第一侧上；
金属层，在所述绝缘层上；以及
导电过孔，延伸通过所述绝缘层并将所述金属层电连接到所述第一导电过孔。
7.根据权利要求6所述的半导体裸片，其中所述源极焊盘连接到所述金属层并且所述感测器件可操作用于感测所述晶体管器件的源极处的电流。
8.根据权利要求2所述的半导体裸片，其中所述半导体主体包括硅并且所述第一导电过孔包括多晶硅或金属。
9.根据权利要求1所述的半导体裸片，其中所述晶体管器件是垂直晶体管器件，所述源极布置在所述半导体主体的第一侧处，所述漏极布置在所述半导体主体的第二侧处，所述源极焊盘连接到所述半导体主体的所述第一侧处的所述源极，并且所述漏极焊盘连接到所述半导体主体的所述第二侧处的所述漏极。
10.根据权利要求1所述的半导体裸片，进一步包括附加感测焊盘，所述附加感测焊盘在所述半导体主体的第二侧处并且与另一感测焊盘和所述漏极焊盘间隔开，所述附加感测焊盘电连接到所述晶体管器件的所述源极。
11.根据权利要求10所述的半导体裸片，进一步包括导电过孔，所述导电过孔从所述第一侧延伸到所述半导体主体中并且通过所述半导体主体的高掺杂区域与所述附加感测焊盘间隔开，其中所述附加感测焊盘通过所述导电过孔和插入在所述导电过孔和所述附加感测焊盘之间的所述半导体主体的所述高掺杂区域电连接到所述晶体管器件的所述源极。
12.根据权利要求1所述的半导体裸片，进一步包括栅极焊盘，所述栅极焊盘在所述半导体主体的第二侧处并且与所述感测焊盘和所述漏极焊盘间隔开，所述栅极焊盘电连接到所述晶体管器件的所述栅极。
13.根据权利要求1所述的半导体裸片，进一步包括栅极焊盘，所述栅极焊盘在所述半导体主体的所述第一侧处并且与所述源极焊盘间隔开，所述栅极焊盘电连接到所述晶体管器件的所述栅极。
14.一种制造半导体裸片的方法，所述方法包括：
在半导体主体中形成晶体管器件，所述晶体管器件具有栅极、源极和漏极；
在所述半导体主体中形成感测器件，所述感测器件可操作用于感测与所述晶体管器件相关联的参数；
在所述半导体主体的第一侧处形成源极焊盘、在所述半导体主体的与所述第一侧相对的第二侧处形成漏极焊盘并且在所述半导体主体的第二侧处与所述漏极焊盘间隔开地形成感测焊盘；
将所述源极焊盘电连接到所述晶体管器件的所述源极；
将所述漏极焊盘电连接到所述晶体管器件的所述漏极；以及
将所述感测焊盘电连接到所述感测器件。
15.根据权利要求14所述的方法，其中将所述感测焊盘电连接到所述感测器件包括：
形成第一导电过孔，所述第一导电过孔从所述第一侧延伸到所述半导体主体中并且通过所述半导体主体的高掺杂区域与所述感测焊盘间隔开，所述感测焊盘通过所述第一导电过孔和插入在所述第一导电过孔与所述感测焊盘之间的所述半导体主体的所述高掺杂区域电连接到所述感测器件。
16.根据权利要求14所述的方法，进一步包括：
在所述半导体主体的第二侧处并且与另一感测焊盘和所述漏极焊盘间隔开地形成附加感测焊盘；以及
将所述附加感测焊盘电连接到所述晶体管器件的所述源极。
17.根据权利要求16所述的方法，其中将所述附加感测焊盘电连接到所述晶体管器件的所述源极包括：
形成导电过孔，所述导电过孔从所述第一侧延伸到所述半导体主体中并且通过所述半导体主体的高掺杂区域与所述附加感测焊盘间隔开，所述附加感测焊盘通过所述导电过孔和插入在所述导电过孔和所述附加感测焊盘之间的所述半导体主体的所述高掺杂区域电连接到所述晶体管器件的所述源极。
18.一种半导体封装体，包括：
第一裸片叶片；以及
半导体裸片，包括：
半导体主体，具有面对所述第一裸片叶片的第一侧和与所述第一裸片叶片远离面对的第二侧；
晶体管器件，布置在所述半导体主体中并且具有栅极、源极和漏极；
感测器件，布置在所述半导体主体中并且可操作用于感测与所述晶体管器件相关联的参数；
源极焊盘，在所述半导体主体的所述第一侧处，所述源极焊盘附接到所述第一裸片叶片并且电连接到所述晶体管器件的所述源极；
漏极焊盘，在所述半导体主体的与所述第一侧相对的第二侧处并且电连接到所述晶体管器件的所述漏极；以及
感测焊盘，在所述半导体主体的第二侧处并且与所述漏极焊盘间隔开，所述感测焊盘电连接到所述感测器件。
19.根据权利要求18所述的半导体封装体，进一步包括附加感测焊盘，所述附加感测焊盘在所述半导体主体的第二侧处并且与另一感测焊盘和所述漏极焊盘间隔开，所述附加感测焊盘电连接到所述晶体管器件的所述源极。
20.根据权利要求18所述的半导体封装体，进一步包括栅极焊盘，所述栅极焊盘在所述半导体主体的第二侧处并且与所述感测焊盘和所述漏极焊盘间隔开，所述栅极焊盘电连接到所述晶体管器件的所述栅极。
21.根据权利要求18所述的半导体封装体，进一步包括：
导电引线，在与所述第一裸片叶片相同的平面中；以及
栅极焊盘，在所述半导体主体的所述第一侧处并且与所述源极焊盘间隔开，所述栅极焊盘附接到所述引线并且电连接到所述晶体管器件的所述栅极。
22.根据权利要求18所述的半导体封装体，其中所述半导体裸片是半桥接电路的低侧功率晶体管裸片，所述半导体封装体进一步包括：
控制器裸片，具有附接到所述第一裸片叶片的第一焊盘和在所述控制器裸片的与所述第一裸片叶片远离面对的侧处的多个附加焊盘，所述控制器裸片可操作用于控制所述半桥接电路的操作；
第二裸片叶片，与所述第一裸片叶片间隔开；以及
所述半桥接电路的高侧功率晶体管裸片，所述高侧功率晶体管裸片具有附接到所述第二裸片叶片的漏极焊盘、电连接到所述控制器裸片的所述附加端子的第一端子的栅极焊盘和电连接到所述低侧功率晶体管裸片的所述漏极焊盘的源极焊盘。
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CN107275316A (zh) * 2016-04-04 2017-10-20 英飞凌科技股份有限公司 具有源极在下配置的晶体管管芯和漏极在下配置的晶体管管芯的半导体封装

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