WO2018159018A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
WO2018159018A1
WO2018159018A1 PCT/JP2017/039806 JP2017039806W WO2018159018A1 WO 2018159018 A1 WO2018159018 A1 WO 2018159018A1 JP 2017039806 W JP2017039806 W JP 2017039806W WO 2018159018 A1 WO2018159018 A1 WO 2018159018A1
Authority
WO
WIPO (PCT)
Prior art keywords
source
gate
terminal
semiconductor chip
pad
Prior art date
Application number
PCT/JP2017/039806
Other languages
English (en)
French (fr)
Inventor
築野　孝
Original Assignee
住友電気工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 住友電気工業株式会社 filed Critical 住友電気工業株式会社
Priority to US16/488,665 priority Critical patent/US20200111727A1/en
Priority to JP2019502456A priority patent/JPWO2018159018A1/ja
Publication of WO2018159018A1 publication Critical patent/WO2018159018A1/ja

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4801—Structure
    • H01L2224/48011—Length
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H01L2224/48096—Kinked the kinked part being in proximity to the bonding area on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H01L2224/48097—Kinked the kinked part being in proximity to the bonding area outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present disclosure relates to a semiconductor device.
  • Patent Document 1 discloses a power semiconductor device in which the aspect ratio of a power semiconductor element is 1.5 or more, the number of wires for extracting a main current from a source electrode is 14 or more, and the directions are distributed in two different directions. It is disclosed.
  • a semiconductor device is a packaged semiconductor device, a die pad, a substrate having a drain terminal extending in one direction from the die pad in a top view, drain terminals on both sides of the drain terminal, and A gate terminal and a source terminal are provided to extend in one direction in parallel.
  • the semiconductor device has a semiconductor chip having a rectangular shape, a short side being parallel to the drain terminal, and a center of gravity being closer to the source terminal than the gate terminal.
  • a gate pad is disposed on the gate terminal side of the upper surface of the semiconductor chip.
  • a plurality of source pads are arranged from the source terminal side of the semiconductor chip toward the gate terminal side.
  • the gate pad and the gate terminal are connected by a gate wire, and the plurality of source pads and the source terminal are connected by a plurality of source wires.
  • FIG. 1 is a top view showing an example of the semiconductor device according to the present embodiment.
  • FIG. 2 is a cross-sectional view showing an example of the configuration of the semiconductor chip of the semiconductor device according to the present embodiment.
  • FIG. 3 is a diagram for explaining the back electromotive force generated when the MOS transistor is switching-driven.
  • FIG. 4 is a cross-sectional view showing an example of a connection state between a source terminal and a source pad of the semiconductor device according to the present embodiment.
  • a semiconductor device is a packaged semiconductor device, and includes a die pad, a substrate having a drain terminal extending in one direction from the die pad in a top view, and both sides of the drain terminal.
  • a gate terminal and a source terminal extending in one direction in parallel with the drain terminal, and having a rectangular shape with a short side parallel to the drain terminal and a center of gravity from the gate terminal to the source terminal
  • the inductance of the source wire By reducing the inductance of the source wire, the back electromotive force generated between the gate and the source at the time of switching of the semiconductor device can be reduced, and the switching speed can be increased.
  • At least one of the plurality of source wires is shorter than the gate wire.
  • Two or more of the plurality of source wires are shorter than the gate wires.
  • the semiconductor chip is a wide gap semiconductor chip.
  • the present embodiment an embodiment of the present disclosure (hereinafter referred to as “the present embodiment”) will be described in detail, but the present embodiment is not limited thereto.
  • FIG. 1 is a top view showing an example of a semiconductor device according to the present embodiment.
  • the semiconductor device according to the present embodiment includes a substrate 10, a gate terminal 20, a source terminal 30, a semiconductor chip 40, a gate pad 50, a source pad 60, a gate wire 70, and a source wire 80. And a package 100.
  • the substrate 10 has a die pad 11 and a drain terminal 12.
  • the semiconductor chip 40 is mounted on the die pad 11 of the substrate 10.
  • a gate pad 50 provided on the upper surface of the semiconductor chip 40 and the gate terminal 20 are connected by a gate wire 70, and a plurality of source pads 60 are connected to the source terminal 30 by a plurality of source wires 80.
  • the semiconductor chip 40 and the die pad 11 are entirely sealed by the package 100, and the gate terminal 20, the drain terminal 12, and the source terminal 30 are exposed from the package 100.
  • the substrate 10 is a metal substrate for mounting the semiconductor chip 40 on the surface.
  • the substrate 10 includes a die pad 11 that is a region on which the semiconductor chip 40 is mounted, and a drain terminal 12 that extends from the die pad 11 in one direction in a top view.
  • a semiconductor chip 40 having a structure in which a gate and a source are disposed on the upper surface and a drain is disposed on the lower surface is mounted on the substrate 10. Therefore, the substrate 10 has the drain terminal 12 that extends directly from the die pad 11 and plays a role of drawing out the drain terminal 12 electrically connected to the drain on the lower surface of the semiconductor chip 40.
  • the drain terminal 12 only needs to extend in one direction when viewed from above, and may be bent in the vertical direction.
  • the drain terminal 12 may be bent upward from below.
  • the die pad 11 may be of any shape and size as long as the semiconductor chip 40 can be mounted on the surface.
  • substrate 10 is formed from a metal material with high electroconductivity, for example, may be comprised with copper or a copper alloy.
  • the gate terminal 20 is electrically connected to a gate pad 50 provided on the upper surface of the semiconductor chip 40, and functions as a control terminal for enabling voltage application from the outside of the package 100 to the gate of the semiconductor chip 40.
  • the gate pad 50 and the gate terminal 20 are electrically connected via the gate wire 70.
  • the gate terminal 20 has a gate wire connection portion 21 in an end region on the die pad 10 side in the package 100.
  • the gate wire connection portion 21 is a portion to which the gate wire 70 is connected, and is provided in a region close to the die pad 10 in a portion of the gate terminal 20 in the package 100.
  • One end of the gate wire 70 is connected to the gate pad 50 and the other end is connected to the gate wire connecting portion 21, thereby electrically connecting the gate pad 50 and the gate terminal 20.
  • the gate terminal 20 is provided apart from the die pad 10 and the drain terminal 12 and is also electrically insulated.
  • the gate terminal 20 is provided in parallel with the drain terminal 12 along the extending direction of the drain terminal 12.
  • the gate terminal 20 is also made of a highly conductive metal material.
  • the gate terminal 20 may be formed from the same material as the drain terminal 12, and may be formed from, for example, copper or a copper alloy.
  • the source terminal 30 is electrically connected to a plurality of source pads 60 provided on the upper surface of the semiconductor chip 40, and functions as an external terminal for extracting the source current output from the source of the semiconductor chip 40 to the outside of the package 100. To do.
  • the plurality of source pads 60 and the source terminals 30 are electrically connected to each other via a plurality of source wires 80.
  • the source terminal 30 also has a source wire connection portion 31 in an end region on the die pad 10 side in the package 100.
  • the source wire connecting portion 31 is a portion to which the source wire 80 is connected, and is provided in a region close to the die pad 10 in a portion of the source terminal 30 in the package 100.
  • One end of each source wire 80 is connected to the source pad 60, and the other end is connected to the source wire connection portion 31, thereby electrically connecting each source pad 60 and the source terminal 30.
  • the source terminal 30 is also provided apart from the die pad 10 and the drain terminal 12, and is also electrically insulated.
  • the source terminal 30 is also provided in parallel with the drain terminal 12 along the extending direction of the drain terminal 12. Therefore, the gate terminal 20 and the source terminal 30 are provided on both sides of the drain terminal 12 so as to sandwich the drain terminal 12.
  • the source terminal 30 is also made of a highly conductive metal material.
  • the source terminal 30 may also be formed from the same material as the drain terminal 12, and may be formed from, for example, copper or a copper alloy. Although a plurality of source pads 60 and source wires 80 are provided, only one source terminal 30 that functions as an external terminal of the semiconductor device is provided.
  • the gate terminal 20 and the source terminal 30 may be variously arranged on both sides of the drain terminal 12 as long as they extend in one direction parallel to the drain terminal.
  • the gate terminal 20 and the source terminal 30 are preferably provided so that the distance between the gate terminal 20 and the drain terminal 12 and the distance between the source terminal 30 and the drain terminal 12 are equal. This is because the applicable range of the semiconductor device is expanded when the shape conforms to a general standard.
  • the semiconductor chip 40 is a semiconductor element that functions as a switching element, and may be configured as, for example, a DMOSFET (Double-Diffused Metal Oxide Semiconductor Field Effect Transistor).
  • the semiconductor chip 40 has a structure in which a gate and a source are formed on the upper surface and a drain is disposed on the lower surface.
  • FIG. 2 is a cross-sectional view showing an example of the configuration of the semiconductor chip 40 of the semiconductor device according to the present embodiment.
  • a drift layer 402 is formed on an n-type semiconductor substrate 401.
  • a body region 403 having a p-type conductivity is formed on the drift layer 402, and a source region 404 having an n-type conductivity is formed on the top of the p-type body region 403.
  • a gate insulating film 406 is formed above the source region 404, the body region 403, and the drift layer 402 so as to straddle the left and right source regions 404, and a gate electrode 405 is provided in the gate insulating film 406. .
  • a metal layer 407 is formed so as to cover the source region 404 and the gate insulating film 406.
  • the metal layer 407 forms the source pad 60 described in FIG. 1 on the upper surface of the semiconductor chip 40.
  • a metal pad electrically connected to the gate electrode 405 and provided on the upper surface of the semiconductor chip 40 constitutes the gate pad 50 in FIG.
  • a metal layer 408 is formed on the back surface of the n-type semiconductor substrate 401, and is joined to the die pad 11 shown in FIG.
  • the n-type semiconductor substrate 401 may be made of various semiconductor materials, but may be made of a wide gap semiconductor material such as silicon carbide (SiC) or gallium nitride (GaN).
  • the drift layer 402 may be made of various semiconductor materials, but may be made of a wide gap semiconductor material such as silicon carbide (SiC) or gallium nitride (GaN). By using a wide gap semiconductor material, it is possible to form a semiconductor device with low loss and high breakdown voltage.
  • the drift layer 402 formed on the n-type semiconductor substrate 401 may be formed by, for example, epitaxial growth.
  • the body region 403 and the source region 404 may be formed by general ion implantation, for example.
  • the gate insulating film 406 may be provided by forming a silicon oxide film (SiO 2 ) by, for example, thermal oxidation treatment.
  • SiO 2 silicon oxide film
  • the gate electrode 405 for example, polysilicon whose conductivity is improved by impurity diffusion may be used.
  • metal layers 407 and 408 for example, a metal material for wiring such as aluminum or copper may be used.
  • the semiconductor chip 40 may be made of a material including a wide gap semiconductor such as silicon carbide (SiC) or gallium nitride (GaN). That is, the semiconductor chip 40 may be a wide gap semiconductor chip. Thereby, a low-loss / high-breakdown-voltage MOS transistor can be formed.
  • a wide gap semiconductor such as silicon carbide (SiC) or gallium nitride (GaN). That is, the semiconductor chip 40 may be a wide gap semiconductor chip.
  • the semiconductor chip 40 of the semiconductor device has a rectangular shape.
  • the semiconductor chip 40 has short sides 41a and 41b and long sides 42a and 42b facing each other.
  • the short side 41a is disposed on the gate terminal 20 side
  • the short side 41b is disposed on the source terminal 30 side.
  • the short sides 41 a and 41 b are arranged so as to be parallel to the extending direction of the gate terminal 20, the drain terminal 12 and the source terminal 30.
  • the gate terminal 20, the drain terminal 12, and the source terminal 30 are disposed only on the long side 42a side of the semiconductor chip 40, and only the die pad 11 exists on the long side 42b side.
  • a gate pad 50 extending in parallel with the short side 41a is disposed. Further, a plurality of source pads 60 are arranged in parallel with the short side 41b from the vicinity of the short side 41b on the source terminal 30 side on the upper surface of the semiconductor chip 40 toward the short side 41a on the opposite side.
  • the number of source pads 60 is four, but this is only an example until it gets tired. The number of source pads 60 may be less or more than four as long as it is plural.
  • the gate pad 50 is extended in parallel with the short side 41a, the shape of the gate pad 50 does not necessarily need to be vertically long.
  • the gate pad 50 may be square, for example.
  • the semiconductor chip 40 has a rectangular shape, and the long sides 42a and 42b of the semiconductor chip 40 extend or cross across the gate terminal 20 and the source terminal 30, whereby the gate pad 50 is gated.
  • the source pad 60 can be brought close to the source wire connection portion 31 of the source terminal 30 without being far away from the terminal 20. That is, the short sides 41 a and 41 b of the semiconductor chip 40 are parallel to the extending direction of the gate terminal 20 and the source terminal 30, and the long sides 42 a and 42 b of the semiconductor chip 40 extend between the gate terminal 20 and the source terminal 30. With the arrangement, the distance between the source pad 60 and the source wire connection portion 31 of the source terminal 30 can be shortened.
  • the semiconductor chip 40 is arranged so that the center of gravity 43 of the semiconductor chip 40 is closer to the source wire connection portion 31 of the source terminal 30 than to the gate wire connection portion 21 of the gate terminal 20. That is, the semiconductor chip 40 is not disposed so that the center of gravity 43 of the semiconductor chip 40 coincides with the center of the drain terminal 12, but is disposed close to the source terminal 30 side.
  • the semiconductor device is arranged such that the short side 41 b on the source terminal 30 side of the semiconductor chip 40 and the source of the source terminal 30 in the arrangement direction of the end of the gate terminal 20, the drain terminal 12 and the end of the source terminal 30 in the package 100.
  • the distance from the wire connection part 31 can be configured to be shorter than the distance between the short side 41a on the gate terminal 20 side and the gate wire connection part 21 of the gate terminal.
  • FIG. 3 is a diagram for explaining the back electromotive force generated when the MOS transistor is switching-driven.
  • a circuit diagram of an n-type MOS transistor is shown, in which the inductance of the gate wire 50 is indicated by Lg and the inductance of the source wire 60 is indicated by Ls.
  • the gate voltage obtained by already subtracting the voltage drop of the inductance Lg of the gate wire 50 is Vgs
  • the gate voltage is expressed by Vgs ⁇ Ls (dI / dt).
  • the semiconductor device according to the present embodiment is configured to reduce the inductance Ls of the source wire 60 by bringing the center of gravity 43 of the semiconductor chip 40 having a rectangular shape closer to the source terminal 30 side. Thereby, the switching speed of the semiconductor device can be increased.
  • At least two of the plurality of source wires 80 are configured to be shorter than the gate wire 70. In this way, by setting at least one, preferably a plurality of source wires 80 shorter than the gate wire 70, the inductance Ls of the source wire 80 can be reduced and the switching speed can be improved.
  • the gate wire 70 also has the inductance Lg, but the source current is much larger than the gate current, and there is a difference of 10 times or more.
  • the priority is given to reducing the inductance Ls of the source wire 80 in line with the intention of increasing the switching speed.
  • the semiconductor chip 40 may be arranged to be much closer to the source terminal 30 than in FIG. 1, and for example, the leftmost source pad 60 may be aligned with the center of the drain terminal 12.
  • the degree to which the semiconductor chip 40 is brought closer to the source terminal 30 can be variously arranged in consideration of the balance between the size of the semiconductor chip 40 and the die pad 11, the length of the gate wire 70, and the like.
  • the ratio of the lengths of the long sides 42a, 42b and the short sides 41a, 41b of the semiconductor chip 40 can also be determined as appropriate according to the application. Good. When the shape approximates a square, it is impossible to adopt a configuration in which the source wire 80 is shortened without making the gate wire 70 so long. Therefore, the semiconductor chip 40 is preferably a rectangle satisfying the long side / short side ⁇ 1.6.
  • a wiring metal material such as aluminum or copper can be used for the gate pad 50 and the source pad 60 depending on the application.
  • the gate wire 70 and the source wire 80 can be made of gold, aluminum or the like, but aluminum may be used from the viewpoint of cost or the like. In the case of bonding an aluminum wire, the bonding is performed with a slight extension along the extending direction of the pad, but the lengths of the gate wire 70 and the source wire 80 are not bonded to the gate pad 50 or the source pad 60. The wire alone may be considered.
  • All of the die pad 11 and the semiconductor chip 40 and the base portions of the gate terminal 20, the drain terminal 12 and the source terminal 30 are sealed by the package 100, but an appropriate resin is selected as the sealing resin depending on the application. can do.
  • the gate terminal 20, the drain terminal 12, and the source terminal 30 are packaged as a three-pin type that extends like a pin outside the package 100, but the gate terminal 20, the drain terminal 12, and the source are packaged.
  • the shape of the terminal 30 can also have various configurations depending on the application.
  • FIG. 4 is a cross-sectional view showing an example of a connection state between the source terminal 30 and the source pad 60 of the semiconductor device according to the present embodiment.
  • the semiconductor chip 40 is bonded onto the die pad 11 by solder 90.
  • the source terminal 30 is provided at a position higher than the semiconductor chip 40, and the source pad 60 and the source wire connection portion 31 of the source terminal 30 are connected via the source wire 80.
  • the die pad 11, the semiconductor chip 40, the source wire connecting portion 31, and the source wire 80 are sealed with the package 100.
  • the drain terminal 12 and the gate terminal 20 may also be disposed at the same height as the source terminal 30.
  • the source wire 80 since the source wire 80 is connected and used with a certain margin, the length becomes longer than the distance between the source pad 60 and the source terminal 30. Therefore, forming the semiconductor chip 40 in a rectangular shape, bringing the center of gravity 43 closer to the source terminal 30 and shortening the source wire 80 to reduce the inductance Ls greatly contributes to the speeding up of switching.
  • tip of the semiconductor device conventionally used has a square shape or some vertically long shape, and is arrange
  • the source wire 80 can be shortened, and the inductance Ls of the source wire 80 can be reduced.
  • the switching speed can be increased.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

パッケージングされた半導体装置であって、ダイパッドと、ダイパッドから上面視にて一方向に延びるドレイン端子を有する基板と、ドレイン端子の両側に、一方向に延びて設けられたゲート端子及びソース端子とを有する。また、半導体装置は、長方形状を有し、短辺がドレイン端子と平行になり、重心が前記ゲート端子より前記ソース端子に近くなるようにダイパッド上に配置された半導体チップを有する。半導体チップの上面のゲート端子側には、ゲートパッド配置される。また、半導体チップのソース端子側から、前記ゲート端子側に向かって複数のソースパッドが配列される。ゲートパッドとゲート端子はゲートワイヤにより接続され、複数のソースパッドとソース端子は複数のソースワイヤにより接続される。

Description

半導体装置
　本開示は、半導体装置に関する。
　本出願は、2017年3月1日出願の日本出願2017-038443号に基づく優先権を主張し、前記日本出願に記載された全ての記載内容を援用するものである。
　特許文献１には、パワー半導体素子の縦横比を１．５以上にするとともに、ソース電極から主電流を取り出すワイヤの本数を１４本以上とし、方向を異なる２方向に分散させたパワー半導体装置が開示されている。
特開２００６－１５６４７９号公報
　本開示の一態様に係る半導体装置は、パッケージングされた半導体装置であって、ダイパッドと、ダイパッドから上面視にて一方向に延びるドレイン端子を有する基板と、ドレイン端子の両側に、ドレイン端子と平行に一方向に延びて設けられたゲート端子及びソース端子とを有する。また、半導体装置は、長方形状を有し、短辺がドレイン端子と平行になり、重心が前記ゲート端子より前記ソース端子に近くなるようにダイパッド上に配置された半導体チップを有する。半導体チップの上面のゲート端子側には、ゲートパッドが配置される。また、半導体チップのソース端子側から、ゲート端子側に向かって複数のソースパッドが配列される。ゲートパッドとゲート端子はゲートワイヤにより接続され、複数のソースパッドとソース端子は複数のソースワイヤにより接続される。
図１は、本実施形態に係る半導体装置の一例を示した上面図である。 図２は、本実施形態に係る半導体装置の半導体チップの構成の一例を示した断面図である。 図３は、ＭＯＳトランジスタをスイッチング駆動させる際に発生する逆起電力を説明するための図である。 図４は、本実施形態に係る半導体装置のソース端子とソースパッドとの接続状態の一例を示した断面図である。
　以下、図面を参照して、本開示を実施するための形態の説明を行う。
　［本開示の実施形態の説明］
　最初に本開示の実施態様を列記して説明する。
　〔１〕　本開示の一態様に係る半導体装置は、パッケージングされた半導体装置であって、ダイパッドと、前記ダイパッドから上面視にて一方向に延びるドレイン端子を有する基板と、前記ドレイン端子の両側に、前記ドレイン端子と平行に前記一方向に延びて設けられたゲート端子及びソース端子と、長方形状を有し、短辺が前記ドレイン端子と平行になり、重心が前記ゲート端子より前記ソース端子に近くなるように前記ダイパッド上に配置された半導体チップと、前記半導体チップの上面の前記ゲート端子側に配置されたゲートパッドと、前記半導体チップの上面の前記ソース端子側から、前記ゲート端子側に向かって配列された複数のソースパッドと、前記ゲートパッドと前記ゲート端子とを接続するゲートワイヤと、前記複数のソースパッドと前記ソース端子とを接続する複数のソースワイヤと、を有する。
　これにより、半導体チップをソース端子寄りに配置してソースワイヤを短くすることができ、ソースワイヤのインダクタンスを低減させることができる。ソースワイヤのインダクタンスを低減させることにより、半導体装置のスイッチングの際にゲートとソース間に発生する逆起電力を低減させることができ、スイッチングの高速化が可能となる。
　〔２〕　前記複数のソースワイヤの少なくとも１本は前記ゲートワイヤよりも短い。
　〔３〕　前記複数のソースワイヤの２本以上が前記ゲートワイヤよりも短い。
　〔４〕　前記半導体チップはワイドギャップ半導体チップである。
　［本開示の実施形態の詳細］
　以下、本開示の一実施形態（以下「本実施形態」と記す）について詳細に説明するが、本実施形態はこれらに限定されるものではない。
　図１は、本実施形態に係る半導体装置の一例を示した上面図である。図１において、本実施形態に係る半導体装置は、基板１０と、ゲート端子２０と、ソース端子３０と、半導体チップ４０と、ゲートパッド５０と、ソースパッド６０と、ゲートワイヤ７０と、ソースワイヤ８０と、パッケージ１００とを有する。また、基板１０は、ダイパッド１１と、ドレイン端子１２とを有する。
　本実施形態に係る半導体装置において、基板１０のダイパッド１１上に半導体チップ４０が搭載されている。半導体チップ４０の上面に設けられたゲートパッド５０とゲート端子２０とがゲートワイヤ７０により接続され、複数のソースパッド６０が複数のソースワイヤ８０によりソース端子３０と接続されている。半導体チップ４０及びダイパッド１１は、全体がパッケージ１００により封止され、パッケージ１００からゲート端子２０、ドレイン端子１２及びソース端子３０が露出している。
　基板１０は、表面上に半導体チップ４０を搭載するための金属基板である。基板１０は、半導体チップ４０を搭載する領域であるダイパッド１１と、ダイパッド１１から上面視にて一方向に延びるドレイン端子１２とを有する。本実施形態に係る半導体装置においては、上面にゲート及びソース、下面にドレインが配置された構造の半導体チップ４０を基板１０に搭載する。よって、基板１０は、ダイパッド１１から直接延びるドレイン端子１２を有し、半導体チップ４０の下面のドレインと電気的に接続されたドレイン端子１２を外部に引き出す役割を果たす。ドレイン端子１２は、上面視において一方向に延びていれば良く、上下方向においては屈曲していてもよい。例えば、ドレイン端子１２は、下方から上方に屈曲していてもよい。ダイパッド１１は、表面上に半導体チップ４０を搭載することができれば、形状や大きさは問わない。また、基板１０は、導電性の高い金属材料から形成され、例えば銅又は銅合金で構成されてもよい。
　ゲート端子２０は、半導体チップ４０の上面に設けられたゲートパッド５０と電気的に接続され、パッケージ１００の外部から半導体チップ４０のゲートへの電圧印加を可能とするための制御端子として機能する。なお、ゲートパッド５０とゲート端子２０とは、ゲートワイヤ７０を介して電気的に接続される。ゲート端子２０は、ゲートワイヤ接続部２１をパッケージ１００内のダイパッド１０側の端部領域に有する。ゲートワイヤ接続部２１は、ゲートワイヤ７０が接続される部分であり、ゲート端子２０のパッケージ１００内の部分のダイパッド１０に接近した領域に設けられる。ゲートワイヤ７０の一端はゲートパッド５０に接続され、他端はゲートワイヤ接続部２１に接続され、これによりゲートパッド５０とゲート端子２０とを電気的に接続する。
　ゲート端子２０は、ダイパッド１０及びドレイン端子１２と離間して設けられ、電気的にも絶縁される。また、ゲート端子２０は、ドレイン端子１２の延在方向に沿って、ドレイン端子１２と平行になるように設けられる。ゲート端子２０も、ドレイン端子１２と同様、導電性の高い金属材料から形成される。ゲート端子２０は、ドレイン端子１２と同じ材料から形成されてもよく、例えば、銅又は銅合金から形成されてもよい。
　ソース端子３０は、半導体チップ４０の上面に設けられた複数のソースパッド６０と電気的に接続され、半導体チップ４０のソースから出力されたソース電流をパッケージ１００の外部に取り出すための外部端子として機能する。複数のソースパッド６０とソース端子３０とは、複数のソースワイヤ８０を介して各々が電気的に接続される。ソース端子３０も、ゲート端子２０と同様に、ソースワイヤ接続部３１をパッケージ１００内のダイパッド１０側の端部領域に有する。ソースワイヤ接続部３１は、ソースワイヤ８０が接続される部分であり、ソース端子３０のパッケージ１００内の部分のダイパッド１０に接近した領域に設けられる。各々のソースワイヤ８０の一端はソースパッド６０に接続され、他端はソースワイヤ接続部３１に接続され、これにより各々のソースパッド６０とソース端子３０とを電気的に接続する。
　ソース端子３０も、ゲート端子２０と同様、ダイパッド１０及びドレイン端子１２と離間して設けられ、電気的にも絶縁される。また、ソース端子３０も、ドレイン端子１２の延在方向に沿って、ドレイン端子１２と平行になるように設けられる。よって、ゲート端子２０及びソース端子３０は、ドレイン端子１２の両側に、ドレイン端子１２を挟むようにして設けられる。ソース端子３０も、ドレイン端子１２と同様、導電性の高い金属材料から形成される。ソース端子３０も、ドレイン端子１２と同じ材料から形成されてもよく、例えば、銅又は銅合金から形成されてもよい。なお、ソースパッド６０及びソースワイヤ８０は複数設けられるが、半導体装置の外部端子として機能するソース端子３０は、１つだけ設けられる。
　ゲート端子２０及びソース端子３０は、ドレイン端子１２の両側に、ドレイン端子と平行に一方向に延びる限り、種々の配置としてよい。しかしながら、ゲート端子２０及びソース端子３０は、ゲート端子２０とドレイン端子１２との間隔と、ソース端子３０とドレイン端子１２との間隔が等間隔となるように設けられることが好ましい。一般的な規格に沿わせた形状とする方が、半導体装置の適用範囲が拡大されるからである。
　半導体チップ４０は、スイッチング素子として機能する半導体素子であり、例えば、ＤＭＯＳＦＥＴ（Double-Diffused Metal Oxide Semiconductor Field Effect Transistor）として構成されてもよい。半導体チップ４０は、上面にはゲート及びソースが形成され、下面にはドレインが配置された構造を有する。
　図２は、本実施形態に係る半導体装置の半導体チップ４０の構成の一例を示した断面図である。図２に示されるように、ｎ型半導体基板４０１の上にドリフト層４０２が形成されている。ドリフト層４０２の上部には、ｐ型の導電型を有するボディ領域４０３が形成され、ｐ型ボディ領域４０３内の上部にｎ型の導電型を有するソース領域４０４が形成されている。また、左右両側のソース領域４０４同士を跨ぐように、ソース領域４０４、ボディ領域４０３及びドリフト層４０２の上方にゲート絶縁膜４０６が形成され、ゲート絶縁膜４０６内にゲート電極４０５が設けられている。また、ソース領域４０４及びゲート絶縁膜４０６を覆うように金属層４０７が形成されている。金属層４０７は、半導体チップ４０の上面において、図１で説明したソースパッド６０を構成する。また、ゲート電極４０５と電気的に接続され、半導体チップ４０の上面に設けられる金属パッドが図１におけるゲートパッド５０を構成する。また、ｎ型半導体基板４０１の裏面には、金属層４０８が形成され、図１で示したダイパッド１１上に半田等で接合され、ドレイン端子１２に電気的に接続される。
　なお、ｎ型半導体基板４０１は、種々の半導体材料から構成されてよいが、例えば、炭化珪素（ＳｉＣ）、窒化ガリウム（ＧａＮ）等のワイドギャップ半導体材料から構成されてもよい。同様に、ドリフト層４０２も、種々の半導体材料から構成されてよいが、例えば、炭化珪素（ＳｉＣ）、窒化ガリウム（ＧａＮ）等のワイドギャップ半導体材料から構成されてもよい。ワイドギャップ半導体材料を用いることにより、低損失で高耐圧の半導体装置を形成することが可能となる。
　なお、ｎ型半導体基板４０１上に形成するドリフト層４０２は、例えば、エピタキシャル成長により形成してもよい。ボディ領域４０３、ソース領域４０４は、例えば、一般的なイオン注入により形成してもよい。また、ゲート絶縁膜４０６は、例えば熱酸化処理により、シリコン酸化膜（ＳｉＯ２）を形成して設けてもよい。ゲート電極４０５には、例えば、不純物拡散により導電性を高めたポリシリコンを用いてもよい。金属層４０７、４０８には、例えば、アルミニウム、銅等の配線用の金属材料を用いてもよい。
　このように、半導体チップ４０は、炭化珪素（ＳｉＣ）、窒化ガリウム（ＧａＮ）等のワイドギャップ半導体を含む材料から構成されてもよい。つまり、半導体チップ４０は、ワイドギャップ半導体チップであってもよい。これにより、低損失・高耐圧のＭＯＳトランジスタを形成することができる。
　図１の説明に戻る。図１に示されるように、本実施形態に係る半導体装置の半導体チップ４０は、長方形の形状を有する。半導体チップ４０は、互いに対向する短辺４１ａ、４１ｂ及び長辺４２ａ、４２ｂを有する。短辺４１ａはゲート端子２０側に配置され、短辺４１ｂはソース端子３０側に配置されている。また、短辺４１ａ、４１ｂは、ゲート端子２０、ドレイン端子１２及びソース端子３０の延在する方向と平行になるように配置されている。そして、ゲート端子２０、ドレイン端子１２及びソース端子３０は、半導体チップ４０の長辺４２ａ側にのみ配置され、長辺４２ｂ側には、ダイパッド１１しか存在しない。
　半導体チップ４０の上面のゲート端子２０側の短辺４１ａ付近には、短辺４１ａに平行に延在したゲートパッド５０が配置されている。また、半導体チップ４０の上面のソース端子３０側の短辺４１ｂ付近から反対側の短辺４１ａに向かって、複数のソースパッド６０が短辺４１ｂと平行に配列されている。図１においては、ソースパッド６０の数は４個であるが、これは飽くまで一例に過ぎない。ソースパッド６０の数は、複数である限り、４個より少なくても多くてもよい。また、ゲートパッド５０は、短辺４１ａに平行に延在しているが、ゲートパッド５０の形状は必ずしも縦長である必要は無い。ゲートパッド５０は例えば正方形であってもよい。
　半導体チップ４０の形状を長方形とし、半導体チップ４０の長辺４２ａ、４２ｂがゲート端子２０とソース端子３０との間を跨ぐように延びる、或いは横切るような配置とすることにより、ゲートパッド５０をゲート端子２０からあまり離すことなく、ソースパッド６０をソース端子３０のソースワイヤ接続部３１に接近させることができる。つまり、半導体チップ４０の短辺４１ａ、４１ｂがゲート端子２０及びソース端子３０の延在方向と平行になり、半導体チップ４０の長辺４２ａ、４２ｂがゲート端子２０とソース端子３０との間に延びる配置とすることにより、ソースパッド６０とソース端子３０のソースワイヤ接続部３１との距離を短くすることができる。
　図１において、半導体チップ４０の重心４３がゲート端子２０のゲートワイヤ接続部２１よりもソース端子３０のソースワイヤ接続部３１に近くなるように半導体チップ４０が配置されている。即ち、半導体チップ４０の重心４３がドレイン端子１２の中心と一致するように半導体チップ４０を配置するのではなく、ソース端子３０側に接近させて半導体チップ４０を配置する。これにより半導体装置を、パッケージ１００内のゲート端子２０の端部、ドレイン端子１２及びソース端子３０の端部の配列方向において、半導体チップ４０のソース端子３０側の短辺４１ｂとソース端子３０のソースワイヤ接続部３１との距離が、ゲート端子２０側の短辺４１ａとゲート端子のゲートワイヤ接続部２１との距離よりも短くなる構成とすることができる。このような構成とすることにより、ソースパッド６０とソース端子３０のソースワイヤ接続部３１とを接続するソースワイヤ８０を短くすることができ、ソースワイヤ８０のインダクタンスを低減させることができる。これにより、半導体装置をスイッチング駆動する際のゲート－ソース間電圧（ソースは接地されているため、以下、「ゲート電圧」と呼ぶ）の逆起電力を低減させ、スイッチングの高速化を図ることができる。
　図３は、ＭＯＳトランジスタをスイッチング駆動させる際に発生する逆起電力を説明するための図である。図３において、ｎ型ＭＯＳトランジスタの回路図が示されており、ゲートワイヤ５０のインダクタンスをＬｇ、ソースワイヤ６０のインダクタンスをＬｓで示す。ここで、ゲートワイヤ５０のインダクタンスＬｇの電圧降下分を既に引いたゲート電圧をＶｇｓとすると、ゲート電圧は、Ｖｇｓ－Ｌｓ（ｄＩ／ｄｔ）で表される。
　ゲートに正電圧が印加され、ＭＯＳトランジスタがターンオンする際には、（ｄＩ／ｄｔ）は正となり、ＭＯＳトランジスタに印加されるゲート電圧はゲートドライバーの出力よりも減少し、ターンオン速度を遅くする。一方、ＭＯＳトランジスタをオフする際には、（ｄＩ／ｄｔ）は負となるため、ゲートドライバーの出力よりも増加し、やはりターンオフ速度を低下させる。
　このように、ＭＯＳトランジスタをターンオン・ターンオフさせる際には、（－Ｌ（ｄＩ／ｄｔ））の逆起電力が発生するため、ソースワイヤ６０のインダクタンスＬｓを低減させることにより、逆起電力（－Ｌ（ｄＩ／ｄｔ））を低減させることができる。これにより、ＭＯＳトランジスタのスイッチングの高速化を図ることができる。
　図１の説明に戻る。本実施形態に係る半導体装置では、長方形状を有する半導体チップ４０の重心４３をソース端子３０側に接近させ、ソースワイヤ６０のインダクタンスＬｓを低減する構成となっている。これにより、半導体装置のスイッチングの高速化を図ることができる。
　図１においては、複数のソースワイヤ８０のうち、少なくとも右端の２本はゲートワイヤ７０よりも短く構成されている。このように、少なくとも１本、好ましくは複数本のソースワイヤ８０をゲートワイヤ７０よりも短い構成とすることにより、ソースワイヤ８０のインダクタンスＬｓを低減させ、スイッチング速度を向上させることができる。
　なお、ゲートワイヤ７０もインダクタンスＬｇを有するが、ソース電流の方がゲート電流よりも遥かに大きく、１０倍以上の差がある。また、１本のゲートワイヤ７０に対してソースワイヤ８０は複数本存在するので、ソースワイヤ８０のインダクタンスＬｓを低減させることを優先させた方が、スイッチングの高速化の意図に沿う。
　よって、図１よりも更に大幅にソース端子３０に半導体チップ４０を接近させて配置し、例えば、一番左側のソースパッド６０が、ドレイン端子１２の中心と一致するような構成としてもよい。半導体チップ４０をどの程度ソース端子３０に接近させるかは、半導体チップ４０とダイパッド１１の大きさ、ゲートワイヤ７０の長さとのバランス等を考慮して、種々の配置構成とすることができる。
　半導体チップ４０の長辺４２ａ、４２ｂと短辺４１ａ、４１ｂとの長さの比も、用途に応じて適宜定めることができるが、例えば、長辺／短辺≧１．６を満たす長方形としてもよい。正方形に近似した形状であると、ゲートワイヤ７０をあまり長くせずにソースワイヤ８０を短くするという構成をとれなくなる。よって、半導体チップ４０は、長辺／短辺≧１．６を満たす長方形であることが好ましい。
　なお、ゲートパッド５０及びソースパッド６０は、上述のように、アルミニウム、銅等の配線金属材料を用途に応じて用いることができる。
　ゲートワイヤ７０及びソースワイヤ８０は、金、アルミニウム等を用いることができるが、コスト等の観点から、アルミニウムを用いるようにしてもよい。アルミニウムのワイヤをボンディングする場合、パッドの延在方向に沿って少し延びた状態でボンディングされるが、ゲートワイヤ７０及びソースワイヤ８０の長さは、ゲートパッド５０又はソースパッド６０に接合されていない、ワイヤ単独の部分で考えるようにしてよい。
　ダイパッド１１、半導体チップ４０の総てと、ゲート端子２０、ドレイン端子１２及びソース端子３０の根元の部分はパッケージ１００により封止されるが、封止樹脂は、用途に応じて適切な樹脂を選択することができる。
　また、図１においては、ゲート端子２０、ドレイン端子１２及びソース端子３０がパッケージ１００の外においてピンのように延びた３ピンタイプとしてパッケージングされているが、ゲート端子２０、ドレイン端子１２及びソース端子３０の形状も、用途に応じて種々の構成とすることができる。
　図４は、本実施形態に係る半導体装置のソース端子３０とソースパッド６０との接続状態の一例を示した断面図である。図４に示される通り、半導体チップ４０はダイパッド１１上に半田９０により接合されている。ソース端子３０は、半導体チップ４０よりも高い位置に設けられ、ソースワイヤ８０を介して、ソースパッド６０とソース端子３０のソースワイヤ接続部３１とが接続されている。そして、ダイパッド１１、半導体チップ４０、ソースワイヤ接続部３１及びソースワイヤ８０はパッケージ１００により封止されている。なお、ドレイン端子１２及びゲート端子２０も、ソース端子３０と同じ高さに配置されてもよい。
　図４に示されるように、ソースワイヤ８０はある程度の余裕を持って接続使用されるので、長さもソースパッド６０とソース端子３０との間の距離以上に長くなる。よって、半導体チップ４０を長方形に形成し、重心４３をソース端子３０に接近させ、ソースワイヤ８０を短くしてインダクタンスＬｓを低減させることは、スイッチングの高速化に大きく寄与する。
　なお、従来から用いられている半導体装置のチップは正方形又は若干縦長の形状を有し、重心がドレイン端子の中心と一致するよう左右対称に配置される。このため、ソースパッドとソース端子とを接続するソースワイヤの長さが長くなってしまう。このような構成では、十分にソースワイヤのインダクタンスＬｓを低減させることができず、逆起電力がスイッチングの高速化を妨げてしまう。
　一方、図１に示される通り、本実施形態に係る半導体装置によれば、ソースワイヤ８０を短くすることができ、ソースワイヤ８０のインダクタンスＬｓを低減させることができる。そして、スイッチングの高速化が可能となる。
　今回開示された実施の形態はすべての点で例示であって、どのような面からも制限的なものではないと理解されるべきである。本発明はこれらの例示に限定されるものではなく、請求の範囲によって示され、請求の範囲と均等の意味及び範囲内でのすべての変更が含まれることが意図される。
　１０　　基板
　１１　　ダイパッド
　１２　　ドレイン端子
　２０　　ゲート端子
　２１　　ゲートワイヤ接続部
　３０　　ソース端子
　３１　　ソースワイヤ接続部
　４０　　半導体チップ
　４１ａ、４１ｂ　　短辺
　４２ａ、４２ｂ　　長辺
　４３　　重心
　５０　　ゲートパッド
　６０　　ソースパッド
　７０　　ゲートワイヤ
　８０　　ソースワイヤ
　９０　　半田
　１００　　パッケージ
　４０１　　ｎ型半導体基板
　４０２　　ドリフト層
　４０３　　ボディ層
　４０４　　ソース領域
　４０５　　ゲート電極
　４０６　　ゲート絶縁膜
　４０７、４０８　　金属層

Claims (4)

  1. 　パッケージングされた半導体装置であって、
    　ダイパッドと、前記ダイパッドから上面視にて一方向に延びるドレイン端子を有する基板と、
    　前記ドレイン端子の両側に、前記一方向に延びて設けられたゲート端子及びソース端子と、
    　長方形状を有し、短辺が前記ドレイン端子と平行になり、重心が前記ゲート端子より前記ソース端子に近くなるように前記ダイパッド上に配置された半導体チップと、
    　前記半導体チップの上面の前記ゲート端子側に配置されたゲートパッドと、
    　前記半導体チップの上面の前記ソース端子側から、前記ゲート端子側に向かって配列された複数のソースパッドと、
    　前記ゲートパッドと前記ゲート端子とを接続するゲートワイヤと、
    　前記複数のソースパッドと前記ソース端子とを接続する複数のソースワイヤと、を有する半導体装置。
  2. 　前記複数のソースワイヤの少なくとも１本が前記ゲートワイヤよりも短い請求項１に記載の半導体装置。
  3. 　前記複数のソースワイヤの２本以上が前記ゲートワイヤよりも短い請求項２に記載の半導体装置。
  4. 　前記半導体チップはワイドギャップ半導体チップである請求項１～３のいずれか一項に記載の半導体装置。
PCT/JP2017/039806 2017-03-01 2017-11-02 半導体装置 WO2018159018A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US16/488,665 US20200111727A1 (en) 2017-03-01 2017-11-02 Semiconductor device
JP2019502456A JPWO2018159018A1 (ja) 2017-03-01 2017-11-02 半導体装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017-038443 2017-03-01
JP2017038443 2017-03-01

Publications (1)

Publication Number Publication Date
WO2018159018A1 true WO2018159018A1 (ja) 2018-09-07

Family

ID=63369956

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2017/039806 WO2018159018A1 (ja) 2017-03-01 2017-11-02 半導体装置

Country Status (3)

Country Link
US (1) US20200111727A1 (ja)
JP (1) JPWO2018159018A1 (ja)
WO (1) WO2018159018A1 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019198800A1 (ja) * 2018-04-11 2019-10-17 ローム株式会社 半導体装置
JP7313197B2 (ja) * 2019-06-11 2023-07-24 ローム株式会社 半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005026294A (ja) * 2003-06-30 2005-01-27 Renesas Technology Corp 半導体装置およびその製造方法
US20050073012A1 (en) * 2003-03-17 2005-04-07 Analog Power Intellectual Properties Limited Transistor having multiple gate pads
US20060255362A1 (en) * 2005-04-22 2006-11-16 Ralf Otremba Semiconductor Component in a Standard Housing and Method for the Production Thereof
US20110169144A1 (en) * 2010-01-13 2011-07-14 Tomas Moreno Die package including multiple dies and lead orientation

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015097237A (ja) * 2013-11-15 2015-05-21 住友電気工業株式会社 半導体装置
JP2016072376A (ja) * 2014-09-29 2016-05-09 ルネサスエレクトロニクス株式会社 半導体装置
JP6591302B2 (ja) * 2016-01-29 2019-10-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050073012A1 (en) * 2003-03-17 2005-04-07 Analog Power Intellectual Properties Limited Transistor having multiple gate pads
JP2005026294A (ja) * 2003-06-30 2005-01-27 Renesas Technology Corp 半導体装置およびその製造方法
US20060255362A1 (en) * 2005-04-22 2006-11-16 Ralf Otremba Semiconductor Component in a Standard Housing and Method for the Production Thereof
US20110169144A1 (en) * 2010-01-13 2011-07-14 Tomas Moreno Die package including multiple dies and lead orientation

Also Published As

Publication number Publication date
US20200111727A1 (en) 2020-04-09
JPWO2018159018A1 (ja) 2019-12-26

Similar Documents

Publication Publication Date Title
US9502388B2 (en) Switching element with a series-connected junction FET (JFET) and MOSFET achieving both improved withstand voltage and reduced on-resistance
US9087829B2 (en) Semiconductor arrangement
US11037847B2 (en) Method of manufacturing semiconductor module and semiconductor module
US9899328B2 (en) Power semiconductor module
KR102379289B1 (ko) 몰딩된 지능형 전력 모듈
US10032736B2 (en) Semiconductor device
US9431394B2 (en) Power semiconductor package with gate and field electrode leads
US11335627B2 (en) Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact
US9263440B2 (en) Power transistor arrangement and package having the same
US20140210061A1 (en) Chip arrangement and chip package
JP5824135B2 (ja) 半導体装置
WO2018159018A1 (ja) 半導体装置
CN104282652A (zh) 具有源极向下和感测配置的半导体裸片和封装体
US10411126B2 (en) Semiconductor device having a first through contact structure in ohmic contact with the gate electrode
US10727228B2 (en) Stacked integrated circuit
TW202226485A (zh) 半導體裝置
CN115668508A (zh) 半导体装置
WO2023145317A1 (ja) 半導体モジュールおよび半導体ユニット
CN109994445B (zh) 半导体元件和半导体装置
JP2010183018A (ja) 半導体装置
JP2005064532A (ja) 半導体装置
CN114144965A (zh) 电路装置
CN109671687A (zh) 功率模块
JP2008085369A (ja) 半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17899137

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2019502456

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17899137

Country of ref document: EP

Kind code of ref document: A1