JPS5571030A - Mounting system for semiconductor device - Google Patents

Mounting system for semiconductor device

Info

Publication number
JPS5571030A
JPS5571030A JP14418778A JP14418778A JPS5571030A JP S5571030 A JPS5571030 A JP S5571030A JP 14418778 A JP14418778 A JP 14418778A JP 14418778 A JP14418778 A JP 14418778A JP S5571030 A JPS5571030 A JP S5571030A
Authority
JP
Japan
Prior art keywords
ground terminals
terminals
terminal
isolated
whereat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14418778A
Other languages
Japanese (ja)
Inventor
Hiromitsu Handa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14418778A priority Critical patent/JPS5571030A/en
Publication of JPS5571030A publication Critical patent/JPS5571030A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To prevent a capacity load from exerting an influence upon other circuits by a system wherein ground terminals for each circuit are isolated each other, a bonding pad is provided on each of them, from which they are connected to a lead terminal with the fore end split into two parts by way of a bonding wire.
CONSTITUTION: Ground terminals for a driving circuit unit 1 and an internal constant voltage power unit 2 are isolated to ground terminals 10, 11. The terminals 10, 11 are allowed to have bonding pads 20, 21 on a semiconductor chip. One lead terminal is isolated into two independent lead terminals covering the section from the part whereat a bonding wire is connected to that whereat it enters a through hole of a printed substrate, which are connected in one lead terminal at the part whereat it enters through hole of the substrate. Since the terminal 11 for the voltage power unit 2 is independent thoroughly from the terminal 10 for the circuit unit 1, the ground terminals are free from noises due to a discharge transient current for capacity driving.
COPYRIGHT: (C)1980,JPO&Japio
JP14418778A 1978-11-24 1978-11-24 Mounting system for semiconductor device Pending JPS5571030A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14418778A JPS5571030A (en) 1978-11-24 1978-11-24 Mounting system for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14418778A JPS5571030A (en) 1978-11-24 1978-11-24 Mounting system for semiconductor device

Publications (1)

Publication Number Publication Date
JPS5571030A true JPS5571030A (en) 1980-05-28

Family

ID=15356217

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14418778A Pending JPS5571030A (en) 1978-11-24 1978-11-24 Mounting system for semiconductor device

Country Status (1)

Country Link
JP (1) JPS5571030A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57195830U (en) * 1981-06-04 1982-12-11
JPS59171152A (en) * 1983-03-17 1984-09-27 Nec Corp Semiconductor device
JPS6134746U (en) * 1984-07-31 1986-03-03 関西日本電気株式会社 electronic components
JPS61144655U (en) * 1985-02-28 1986-09-06
JPS6214748U (en) * 1985-07-11 1987-01-29
JPS62120056A (en) * 1985-11-20 1987-06-01 Mitsubishi Electric Corp Metal mold frame of semiconductor device
JPS62134255U (en) * 1986-02-17 1987-08-24
JPS6420747U (en) * 1987-07-27 1989-02-01
JPH01295429A (en) * 1988-05-24 1989-11-29 Toshiba Corp Semiconductor integrated circuit
JPH04260341A (en) * 1991-02-15 1992-09-16 Nec Corp Semiconductor integrated circuit device
US5834837A (en) * 1997-01-03 1998-11-10 Lg Semicon Co., Ltd. Semiconductor package having leads with step-shaped dimples

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57195830U (en) * 1981-06-04 1982-12-11
JPS59171152A (en) * 1983-03-17 1984-09-27 Nec Corp Semiconductor device
JPH0234458B2 (en) * 1983-03-17 1990-08-03 Nippon Electric Co
JPS6134746U (en) * 1984-07-31 1986-03-03 関西日本電気株式会社 electronic components
JPS61144655U (en) * 1985-02-28 1986-09-06
JPS6214748U (en) * 1985-07-11 1987-01-29
JPS62120056A (en) * 1985-11-20 1987-06-01 Mitsubishi Electric Corp Metal mold frame of semiconductor device
JPS62134255U (en) * 1986-02-17 1987-08-24
JPS6420747U (en) * 1987-07-27 1989-02-01
JPH01295429A (en) * 1988-05-24 1989-11-29 Toshiba Corp Semiconductor integrated circuit
JPH04260341A (en) * 1991-02-15 1992-09-16 Nec Corp Semiconductor integrated circuit device
US5834837A (en) * 1997-01-03 1998-11-10 Lg Semicon Co., Ltd. Semiconductor package having leads with step-shaped dimples

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