JPS5571030A - Mounting system for semiconductor device - Google Patents
Mounting system for semiconductor deviceInfo
- Publication number
- JPS5571030A JPS5571030A JP14418778A JP14418778A JPS5571030A JP S5571030 A JPS5571030 A JP S5571030A JP 14418778 A JP14418778 A JP 14418778A JP 14418778 A JP14418778 A JP 14418778A JP S5571030 A JPS5571030 A JP S5571030A
- Authority
- JP
- Japan
- Prior art keywords
- ground terminals
- terminals
- terminal
- isolated
- whereat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
PURPOSE: To prevent a capacity load from exerting an influence upon other circuits by a system wherein ground terminals for each circuit are isolated each other, a bonding pad is provided on each of them, from which they are connected to a lead terminal with the fore end split into two parts by way of a bonding wire.
CONSTITUTION: Ground terminals for a driving circuit unit 1 and an internal constant voltage power unit 2 are isolated to ground terminals 10, 11. The terminals 10, 11 are allowed to have bonding pads 20, 21 on a semiconductor chip. One lead terminal is isolated into two independent lead terminals covering the section from the part whereat a bonding wire is connected to that whereat it enters a through hole of a printed substrate, which are connected in one lead terminal at the part whereat it enters through hole of the substrate. Since the terminal 11 for the voltage power unit 2 is independent thoroughly from the terminal 10 for the circuit unit 1, the ground terminals are free from noises due to a discharge transient current for capacity driving.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14418778A JPS5571030A (en) | 1978-11-24 | 1978-11-24 | Mounting system for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14418778A JPS5571030A (en) | 1978-11-24 | 1978-11-24 | Mounting system for semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5571030A true JPS5571030A (en) | 1980-05-28 |
Family
ID=15356217
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14418778A Pending JPS5571030A (en) | 1978-11-24 | 1978-11-24 | Mounting system for semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5571030A (en) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57195830U (en) * | 1981-06-04 | 1982-12-11 | ||
JPS59171152A (en) * | 1983-03-17 | 1984-09-27 | Nec Corp | Semiconductor device |
JPS6134746U (en) * | 1984-07-31 | 1986-03-03 | 関西日本電気株式会社 | electronic components |
JPS61144655U (en) * | 1985-02-28 | 1986-09-06 | ||
JPS6214748U (en) * | 1985-07-11 | 1987-01-29 | ||
JPS62120056A (en) * | 1985-11-20 | 1987-06-01 | Mitsubishi Electric Corp | Metal mold frame of semiconductor device |
JPS62134255U (en) * | 1986-02-17 | 1987-08-24 | ||
JPS6420747U (en) * | 1987-07-27 | 1989-02-01 | ||
JPH01295429A (en) * | 1988-05-24 | 1989-11-29 | Toshiba Corp | Semiconductor integrated circuit |
JPH04260341A (en) * | 1991-02-15 | 1992-09-16 | Nec Corp | Semiconductor integrated circuit device |
US5834837A (en) * | 1997-01-03 | 1998-11-10 | Lg Semicon Co., Ltd. | Semiconductor package having leads with step-shaped dimples |
-
1978
- 1978-11-24 JP JP14418778A patent/JPS5571030A/en active Pending
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57195830U (en) * | 1981-06-04 | 1982-12-11 | ||
JPS59171152A (en) * | 1983-03-17 | 1984-09-27 | Nec Corp | Semiconductor device |
JPH0234458B2 (en) * | 1983-03-17 | 1990-08-03 | Nippon Electric Co | |
JPS6134746U (en) * | 1984-07-31 | 1986-03-03 | 関西日本電気株式会社 | electronic components |
JPS61144655U (en) * | 1985-02-28 | 1986-09-06 | ||
JPS6214748U (en) * | 1985-07-11 | 1987-01-29 | ||
JPS62120056A (en) * | 1985-11-20 | 1987-06-01 | Mitsubishi Electric Corp | Metal mold frame of semiconductor device |
JPS62134255U (en) * | 1986-02-17 | 1987-08-24 | ||
JPS6420747U (en) * | 1987-07-27 | 1989-02-01 | ||
JPH01295429A (en) * | 1988-05-24 | 1989-11-29 | Toshiba Corp | Semiconductor integrated circuit |
JPH04260341A (en) * | 1991-02-15 | 1992-09-16 | Nec Corp | Semiconductor integrated circuit device |
US5834837A (en) * | 1997-01-03 | 1998-11-10 | Lg Semicon Co., Ltd. | Semiconductor package having leads with step-shaped dimples |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5089876A (en) | Semiconductor ic device containing a conductive plate | |
US6667560B2 (en) | Board on chip ball grid array | |
EP0875935A3 (en) | Semiconductor device having a projecting electrode | |
JPS5662352A (en) | Semiconductor integrated circuit device for acoustic amplification circuit | |
TW371733B (en) | Memory module | |
EP0803906A3 (en) | Tape carrier package and liquid crystal display device | |
SG60099A1 (en) | Semiconductor package and manufacturing method of lead frame | |
JPS5571030A (en) | Mounting system for semiconductor device | |
KR960032705A (en) | Semiconductor integrated circuit device | |
EP0346061A3 (en) | Integrated circuit device having an improved package structure | |
JPS5553446A (en) | Container of electronic component | |
EP0276940A3 (en) | Semiconductor chip having external terminals connected to corresponding leads by wires | |
JPS6011462B2 (en) | semiconductor equipment | |
EP0825647A3 (en) | Chip size package | |
JPS54133878A (en) | Semiconductor device | |
JPS5561046A (en) | Packaging device for semiconductor integrated circuit | |
JPS57138170A (en) | Semiconductor integrated circuit device | |
EP0300434A3 (en) | Overcurrent protection circuit for semiconductor device | |
JPS6464347A (en) | Semiconductor integrated circuit | |
JPH02119171A (en) | Semiconductor integrated circuit device | |
SE9904622L (en) | Module comprising one or more chips | |
JPH0360050A (en) | Semiconductor device | |
JPS5571053A (en) | Circuit device | |
KR980006216A (en) | Semiconductor device with lead terminals only on one side of package | |
JPS61180470A (en) | Semiconductor integrated circuit device |