JPH01295429A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To suppress noises generated in paths of power source voltage and to prevent the occurrence of erroneous operations, by making the area for the inner lead parts of lead frame terminals for supplying at least the power source voltage to a semiconductor chip larger than other inner lead parts. CONSTITUTION:The area of inner lead parts 32 for lead frame terminals for supplying a power source voltage is made large. Thus, power-source-current supplying capability in the inner lead parts 32 is increased. Noises generated in pad electrodes 20 and 21 on a semiconductor chip 31 are absorbed in the inner lead parts 32. Each of the inner lead parts 32 which are divided into a plurality of parts is independently connected to the pad electrodes 20 and 21 on the semiconductor chip 31. Therefore, the effects of the noises between the divided inner leads parts 32 are largely alleviated. In this way, the occurrence of erroneous operation can be suppressed to be of a low ratio.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor integrated circuit designed to alleviate the effects of power supply noise based on transient currents.

(Prior Art) An integrated circuit device that has a single function by assembling many semiconductor elements, so-called IC, is formed by enclosing a semiconductor chip with a large number of elements in an envelope. . A plurality of pad electrodes are provided on this semiconductor chip for inputting and outputting signals, supplying power supply voltage, and the like.

FIG. 8 is a block diagram showing the circuit configuration of a typical memory IC chip. An address signal is input to the address pad electrode 11 from outside the chip. The address signal input to this pad electrode 11 is sent to the address buffer 1.
2 to the address decoder 13, and the memory circuit 1 corresponds to the decoded output of the address decoder 13.
Data is read from address 4. The data read from the memory circuit 14 is amplified by the sense amplifier 15, and then sent to the output buffer 17 via the output circuit 16.
is input. Then, data is outputted from this output buffer 17 to the outside via a pad electrode 18 for data output.

By the way, in order to operate the memory IC chip, it is necessary to apply a power supply voltage and a base voltage from the outside. Among these, the power supply voltage VCC is applied to the power supply pad electrode 19, and two types of reference voltages, vssl and vsS2, are respectively applied to the dedicated power supply pad electrodes 20.21.

Note that a load capacitor 24 is parasitically attached to the pad electrode 18 for data output.

Here, the power supply voltage VCC applied to the power supply pad electrode 19 is applied to an internal circuit 22 consisting of an address buffer 12, an address decoder 13, a memory circuit 14, and a sense amplifier 15, and a peripheral circuit consisting of an output circuit 1B and an output buffer 17. Although it is commonly supplied to the circuit 23, two types of reference voltages, Vssl and vsS2, are independently supplied to the internal circuit 22 and peripheral circuit 23. The reason for this is as follows.

There are various configurations of memory ICs, but the typical S
Many RAMs (static RAM), ROMs, and the like have multi-bit output data, typically 8 bits or 16 bits. Normally, the value of the load capacitance 24 attached to the output pad electrode from which each bit data is output is usually about 100 pF. With multi-bit memory, multiple load capacitors can be charged at the same time.
It is necessary to discharge the power, and the power supply wiring inside the chip is
A large current flows due to discharge. For this reason, when a large current as described above flows through a reference voltage wiring having a particularly long wiring length and a large resistance component or inductance component within the chip, the reference voltage within the chip fluctuates greatly.

Therefore, the internal circuit 22 is supplied with the base voltage Vssl, and the peripheral circuit 2 which has an output buffer through which a large current flows.
By independently supplying the reference voltage V9S2 to the reference voltage vsS2, the reference voltage Vssl is not affected even if noise occurs in the reference voltage vsS2. In addition, in FIG. 8, the reference voltage of the output circuit 16 and the output buffer 17 is set to vsS2, but when the reference voltage for the internal circuit of the output circuit 16 is set to vsS1 and only the output buffer 17 is connected to the reference voltage Vss2. There is also.

On the other hand, in addition to the semiconductor chip, an IC is provided with a plurality of lead frame terminals each including an inner lead portion and an outer lead portion integrally formed with the inner lead portion. Then, the tip of the inner lead part and the pad electrode provided on the semiconductor chip are electrically connected with a thin metal wire called a bonding wire made of, for example, Au or Al. It is enclosed together with a semiconductor chip in an envelope.

On the other hand, the outer lead portion led out from the envelope is cut and bent into a predetermined shape, so that it can be used, for example, as a DI.
Used as a P-type external terminal.

FIG. 9 is a plan view showing the conventional internal structure of an envelope in which the memory IC chip is encapsulated and has 28 external terminals. 31 is an IC chip, on which are pad electrodes 19 for power supply voltage VCC, reference voltages Vssl, vsS.
Various pad electrodes including pad electrodes 20 and 21 for 2 are provided.

Further, 32 is an inner lead portion of a lead frame terminal, 33 is a bonding wire, and 34 is an envelope. Note that pad electrodes other than those for power supply voltage and outer lead portions of lead frame terminals are omitted.

As shown in the figure, conventionally the reference voltage for circuits through which large current flows, such as output buffers, is separated from other circuits on the semiconductor chip, but the lead frame terminals are common to both the inner and outer leads. I have to.

By the way, in recent years, high-speed memories have been designed to shorten access times.
Due to the discharge, fluctuations in the reference voltage due to inductance components at the lead frame terminals for supplying the reference voltage can no longer be ignored.

For example, let us find the value of inductance in the inner lead portion 32 of the lead frame terminal for supplying the reference voltage of an IC as shown in FIG. The self-inductance of the inner lead part is determined by the length of the inner lead part and the width of the inner lead part.
1 thickness is approximately expressed by the following equation.

(nH)...1 Here, examples of typical values include no 1.5 (cm), w
When -0,05(c+a) and t-0,02(c+a) are substituted into the above equation 1, the value of L becomes 12.8 (nH).

On the other hand, the discharge current of the output buffer 17 in the memory will be determined in FIG. FIG. 10 is an equivalent circuit of a portion related to the output buffer 17 in FIG. 8. In Figure 10, C is the load capacitance, Q is the N-channel output transistor in the output buffer for discharging this load capacitance C, and L is the self-inductance present in the inner lead of the lead frame terminal for supplying the reference voltage. It is an ingredient.

In this case, we are considering discharging the load capacitance C, and the P-channel charging output transistor connected to the power supply voltage VCC in the output buffer is turned off, so it is omitted here. When this memory has an 8-bit configuration, the value of the load capacitance C is 800 pF, which is eight times the value of 1 bit, 100 pF. In addition, the dimensions of the channel width W and channel length for one output transistor are usually W-
300 (μm) and L-2.2 (μm), the equivalent channel width W of the output transistor Q for 8 bits is 2400 (μm) and the channel length is 2.300 (μm).
2 (μm).

Here, the signal D out at the load capacitance C is set to 5 (
V) and Dout is at level 10, a signal Din as shown in the waveform diagram of FIG. The results obtained by computer simulation of the change in current Is are shown in the characteristic diagram in Figure 12.The noise generated in the reference voltage vs52 is determined by the ratio of the temporal change in the discharge current Is, that is, d I s / d t Proportional, its maximum value d
is/dt(a+ax) is approximately 7 points at the position indicated by the straight line in the figure.
8X 106 (A/5ee). Therefore, the maximum voltage Vs s 2 (IIla
x) is expressed by the following formula.

Vss2(wax)-L-dls/dt(iax)
-2Here, what was calculated earlier, L-12,8(nH), d
I s/d t (s+ax) -7sx 106
Substituting (A/5ee), we get V5 S 2 (Il
ax ): 1 (V). That is, in the conventional IC shown in FIG. 9, the pad electrode 21 on the chip, which would normally be 0 (v), rises to a maximum of 1 (v). Therefore, since the pad electrode 20 is also affected by this voltage fluctuation, the conventional method has a drawback in that the internal circuit is likely to malfunction.

(Problem to be Solved by the Invention) As described above, in conventional semiconductor integrated circuits, pad electrodes for power supply voltage supply are provided independently on the semiconductor chip for circuits where a large amount of current flows and circuits where a large amount of current flows, and circuits where a current does not flow. Efforts have been made to prevent malfunctions due to this, but this is still not enough.

This invention was made in consideration of the above circumstances, and its purpose is to provide a semiconductor integrated circuit that can minimize the occurrence of malfunctions by suppressing noise generated in the power supply voltage path. Our goal is to provide the following.

[Structure of the Invention] (Means for Solving the Problems) The semiconductor integrated circuit of the present invention has at least an inner lead portion of a lead frame terminal for supplying power supply voltage to a semiconductor chip whose area is larger than other inner lead portions. It is characterized by being enlarged.

The semiconductor integrated circuit of the present invention is characterized in that at least an inner lead portion from an outer lead portion of a lead frame terminal for supplying a power supply voltage to a semiconductor chip is divided into a plurality of portions.

(Function) By increasing the area of the inner lead part of the lead frame terminal for power supply voltage supply, the ability to supply power supply current in the inner lead part increases, and the noise generated in the pad electrode on the semiconductor chip is transferred to this inner lead part. It is absorbed by.

Furthermore, by independently connecting each of the inner lead parts divided into a plurality of parts to the pad electrodes on the semiconductor chip, the influence of noise between the divided inner lead parts can be significantly reduced.

(Examples) Hereinafter, the present invention will be explained by examples with reference to the drawings.

FIG. 1 is a plan view showing the internal structure of an envelope according to a first embodiment of the present invention. The IC according to this embodiment uses a memory IC chip 31 provided with pad electrodes 20 and 21 for two reference voltages Vssl and Vss2 as in FIG. 8 above. As in FIG. 9, 32 is the inner lead portion of each lead frame terminal, 33 is a bonding wire, and 34 is an envelope. Note that although pad electrodes other than those for reference voltage on the chip and the outer leads of the lead frame terminals are omitted in Figure 1, each outer lead is shown in Figure 2 as a perspective view showing the overall structure of the IC. The portion 35 is led out to the outside of the envelope 34,
By cutting and bending into a predetermined shape, for example, DI
Used as a P (dual-in-0 line) type external terminal.

In the IC according to this embodiment, the reference voltages Vs s l, V
The inner lead portion 32 of the lead frame terminal for s s Z has two inner lead portions 32A starting from the outer lead portion of the lead frame terminal (not shown in FIG. 1).
, 32B, and each bonding wire 33 is separated between the tip of each inner lead part 32A, 32B and two pad electrodes 20, 21 on the chip.
are connected to each other.

In such a configuration, a large current flows through the peripheral circuit 23 (both shown in FIG. 8) in which the output buffer 17 is provided, and the base *tS pressure at the pad 21 vs.
Suppose that 2 instantaneously floats by about 1 (v) as described above.

Voltage fluctuations in the reference voltage v882 at this time are transmitted to the inner lead portion 32B of the lead frame terminal. However, the pad 20 to which the internal circuit 22 (shown in FIG. 8) is connected is connected to the same lead frame terminal via an independent bonding wire 33 and an inner lead portion 32A that is separated from the inner lead portion 32B. It is connected to an outer lead portion 35 (shown in FIG. 2).

Therefore, voltage fluctuations in the reference voltage VS S 2 transmitted to the inner lead portion 32B are not transmitted to the inner lead portion 32A to which the internal circuit 22 is connected. Therefore, the reference voltage vsS1 is always stable without being affected by the current flowing through the output buffer, and the internal circuit 22 operates normally without causing any malfunction.

In IC memories that require high-speed operation, it is necessary to instantaneously flow a large amount of current especially to the output buffer, and dividing the inner lead part for the reference voltage in this way has the effect of reducing power supply noise on the internal circuit. big.

FIG. 3 shows an envelope 34 according to a second embodiment of the invention;
FIG. 3 is a plan view showing the structure of a lead frame terminal sealed inside the envelope 34. FIG. In the figure, 3B is a bed portion on which the semiconductor chip is placed, and 37 and 38
Reference numeral 39 indicates a hanging bottle portion for holding the bed portion 3B, and 39 indicates a holding portion for fixing the capacitor pin portions 37 and 38, respectively.

In the IC according to this embodiment, as in the embodiment shown in FIG. In addition, the inner lead part 32C for the power supply voltage VCC is configured to have a larger area than other inner lead parts for signal input/output (not shown).

Furthermore, in this embodiment, each inner lead part 32 disposed at the four corners of the envelope 34, including the inner lead parts for the reference voltage and the power supply voltage, is molded by, for example, a transfer molding method. When forming by resin molding, a reinforcing hanging pin part 40 is added to prevent each inner lead part from shifting from a predetermined position.

In this way, the inner lead portion 32 for power supply voltage VCC
By increasing the area of C, noise in the power supply voltage VCC can also be alleviated. Furthermore, by adding the reinforcing hanging pin portion 40, even if the number or area of the inner lead portions 82 increases, it is possible to prevent the strength of each inner lead portion from decreasing.

FIG. 4 shows an envelope 34 according to a third embodiment of the invention;
A lead frame end sealed inside this envelope 34,
It is a top view showing the structure of a child. In this embodiment, the first
Similarly to the embodiment shown in the figure, the inner lead section 32 for the reference voltage is divided into an inner lead section 32A for one reference voltage Vss and an inner lead section 32B for the other reference voltage vss2. The inner lead part for power supply voltage VCC is also inner lead part 32D and 32E.
It is divided into two parts. In this case, two or only one VCC electrode pad may be provided on the semiconductor chip (not shown). When only one VCC electrode pad is provided on a chip, the inner lead portions 32D and 32E are connected to the same electrode pad on the chip using separate bonding wires. In addition, also in the case of this embodiment, the hanging pin portions 37, 3. '& are each fixed by a holding part 3g, and a reinforcing hanging pin part 4 is attached to each inner lead part 32 arranged at the four corners of the envelope 34.
0 is added.

FIG. 5 shows an envelope 34 according to a fourth embodiment of the invention;
FIG. 3 is a plan view showing the structure of a lead frame terminal sealed inside the envelope 34. FIG. In this embodiment, the third
In the example shown in the figure, the basic voltage is divided into two.
The inner lead parts 32A and 32B for sl are integrated as an inner lead part 32F, and this inner lead part 32F is used as the inner lead part 3 for power supply voltage VCC.
Similar to 2C, it is configured to have a larger area than other inner lead portions for signal input/output.

FIG. 6 shows an envelope 34 according to a fifth embodiment of the invention;
FIG. 3 is a plan view showing the structure of a lead frame terminal sealed inside the envelope 34. FIG. In this embodiment, the third
By providing a connection part 41 that connects one inner lead part 32A for the reference voltage Vssl and one hanging pin part 38 that holds the bed part 36 in the illustrated embodiment, the inner lead part 32A transmits the voltage. The reference voltage VSSI is led to the hanging pin part 37 on the other side through the connecting part 41, the hanging pin part 38 and the bed part 88, and a new inner lead part 32G is provided in this hanging pin part 37. It is something. This inner lead part 3
By providing 2G, one more electrode pad for VSS can be provided on the chip.

FIG. 7 shows an envelope 34 according to a sixth embodiment of the invention;
FIG. 3 is a plan view showing the structure of a lead frame terminal sealed inside the envelope 34. FIG. As in the embodiment shown in FIG. 3, the inner leads for the reference voltage are connected to the inner lead part 32A for vssl and the inner lead part 3 for v8S2.
2B, the number of inner lead parts provided on the lower side in the figure with the hanging pin part 38 at the center becomes greater than the number of inner lead parts provided on the upper side. In this case, as shown in FIG.
If the lead frame terminal is led out from the center, it may be difficult to design the lead frame terminal due to the balance and strength of the arrangement of the upper and lower inner lead parts.

Therefore, in this embodiment, the number of the upper and lower inner lead parts is taken into consideration, and the hanging pin part 38 is shifted from the center of the bed part 3B.

As described above, according to each of the above embodiments, the inner lead section that supplies the reference voltage or the power supply voltage is divided, or the area of this inner lead section is made larger than the inner lead sections for other signals. Therefore, noise generated in the power supply voltage path can be suppressed, and malfunctions due to noise can be prevented.

Further, in each of the above embodiments, all the inner leads other than the inner leads 32A and 32B for the reference voltage and the inner lead 32C for the power supply voltage VCC are arranged vertically symmetrically, as shown in FIG. 3, for example. There is. With this arrangement, when molding the lead frame terminal by press working, the number of press blades can be reduced, and the cost required for mold design can be reduced.

It goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways. For example, in the above embodiment, a case has been described in which the inner lead portion for reference voltage or power supply voltage is divided into two, but it may be divided into two or more.

[Effects of the Invention] As explained above, according to the present invention, it is possible to suppress the noise generated in the path of the power supply voltage, thereby providing a semiconductor integrated circuit in which the occurrence of malfunctions is kept extremely low. can.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing the internal structure of the envelope according to the first embodiment of the present invention, FIG. 2 is a perspective view showing the overall structure of the IC in the above embodiment, and FIGS. 3 to 7 are FIG. 8 is a block diagram showing the circuit structure of a typical memory IC chip, and FIG. 9 is a plan view showing the internal structure of an envelope according to another embodiment of the present invention. 10 is an equivalent circuit diagram of a part of the circuit of the memory IC chip in FIG. 8, FIG. 11 is a waveform diagram of a signal used in the circuit in FIG. 10, and FIG. 12 is a diagram showing the waveform of a signal used in the circuit in FIG. It is a characteristic diagram of a circuit. 20, 21... Pad electrode for reference voltage, 31...
Memory IC chip, 32.32A, 32B, 32C
, 32D, 32E. 32F, 32G... Inner lead part of lead frame terminal, 33... Bonding wire, 34... Envelope, 35... Outer lead part of lead frame terminal, 36... Bed part, 37. 38... Hanging bottle part, 39... Holding part, 40... Hanging pin part, 41...
・Connection part. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 Vss2 vss2 Figure 10 5 1 (nsec)

Claims (1)

[Claims] 1. A semiconductor chip having a plurality of pad electrodes formed on its surface, an envelope housing the semiconductor chip, and a plurality of leads each including an inner lead portion and an outer lead portion. The frame terminal includes a thin metal wire connecting the tip of the inner lead portion of each of the plurality of lead frame terminals to a pad electrode formed on the surface of the semiconductor chip, and the metal wire connects at least a power supply voltage to the semiconductor chip. A semiconductor integrated circuit characterized in that the area of an inner lead portion of a lead frame terminal for supplying a lead frame is larger than other inner lead portions. 2. A semiconductor chip having a plurality of pad electrodes formed on its surface; an envelope housing the semiconductor chip; a plurality of lead frame terminals each comprising an inner lead portion and an outer lead portion; A lead frame for supplying at least a power supply voltage to the semiconductor chip, comprising a thin metal wire connecting the tip of the inner lead portion of each lead frame terminal and a pad electrode formed on the surface of the semiconductor chip. A semiconductor integrated circuit characterized in that an inner lead part of a terminal from an outer lead part is divided into a plurality of parts.