JPS6420747U - - Google Patents

Info

Publication number
JPS6420747U
JPS6420747U JP1987115425U JP11542587U JPS6420747U JP S6420747 U JPS6420747 U JP S6420747U JP 1987115425 U JP1987115425 U JP 1987115425U JP 11542587 U JP11542587 U JP 11542587U JP S6420747 U JPS6420747 U JP S6420747U
Authority
JP
Japan
Prior art keywords
island
leads
lead frame
branched
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987115425U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987115425U priority Critical patent/JPS6420747U/ja
Publication of JPS6420747U publication Critical patent/JPS6420747U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例とアイランドに載置
されたＩＣチツプの平面模式図、第２図は第１図
の実施例を組立たＩＣの効果を説明するための等
価回路図、第３図は従来のリードフレームの一例
とアイランドに載置されたＩＣチツプの平面模式
図、第４図は第３図の実施例を組立たＩＣの問題
点を説明するための等価回路図である。 ２……アイランド、Ｌ……外部ピン、ｌｐ……
電流パルス用内部リード、ｌｓ……小信号用内部
リード。 FIG. 1 is a schematic plan view of an embodiment of the present invention and an IC chip mounted on an island, FIG. 2 is an equivalent circuit diagram for explaining the effect of an IC assembled from the embodiment of FIG. 1, and FIG. Fig. 3 is a schematic plan view of an example of a conventional lead frame and an IC chip mounted on an island, and Fig. 4 is an equivalent circuit diagram for explaining the problems of the IC assembled using the embodiment shown in Fig. 3. . 2...Island, L...External pin, lp...
Internal lead for current pulse, ls...Internal lead for small signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] アイランドの周辺を複数リードが取囲む領域を
金属帯板に連続して設けたリードフレームにおい
て、少なくとも１つの前記リードの前記アイラン
ド側が分岐されていることを特徴とするリードフ
レーム。 1. A lead frame in which a region in which a plurality of leads surround an island is continuously provided on a metal band plate, wherein at least one of the leads is branched on the island side.
JP1987115425U 1987-07-27 1987-07-27 Pending JPS6420747U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987115425U JPS6420747U (en) 1987-07-27 1987-07-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987115425U JPS6420747U (en) 1987-07-27 1987-07-27

Publications (1)

Publication Number Publication Date
JPS6420747U true JPS6420747U (en) 1989-02-01

Family

ID=31357069

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987115425U Pending JPS6420747U (en) 1987-07-27 1987-07-27

Country Status (1)

Country Link
JP (1) JPS6420747U (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5571030A (en) * 1978-11-24 1980-05-28 Hitachi Ltd Mounting system for semiconductor device
JPS5878448A (en) * 1982-10-18 1983-05-12 Hitachi Ltd Package for integrated circuit
JPS6119151A (en) * 1984-07-05 1986-01-28 Nec Corp Semiconductor device
JPS6211256A (en) * 1985-07-09 1987-01-20 Fujitsu Ltd Semiconductor integrated circuit device
JPS6214748B2 (en) * 1984-02-08 1987-04-03 Hitachi Ltd

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5571030A (en) * 1978-11-24 1980-05-28 Hitachi Ltd Mounting system for semiconductor device
JPS5878448A (en) * 1982-10-18 1983-05-12 Hitachi Ltd Package for integrated circuit
JPS6214748B2 (en) * 1984-02-08 1987-04-03 Hitachi Ltd
JPS6119151A (en) * 1984-07-05 1986-01-28 Nec Corp Semiconductor device
JPS6211256A (en) * 1985-07-09 1987-01-20 Fujitsu Ltd Semiconductor integrated circuit device

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