JPS6298244U - - Google Patents
Info
- Publication number
- JPS6298244U JPS6298244U JP19090985U JP19090985U JPS6298244U JP S6298244 U JPS6298244 U JP S6298244U JP 19090985 U JP19090985 U JP 19090985U JP 19090985 U JP19090985 U JP 19090985U JP S6298244 U JPS6298244 U JP S6298244U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- lead
- sealing resin
- lead parts
- parts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 238000007789 sealing Methods 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Wire Bonding (AREA)
- Electric Clocks (AREA)
Description
図面は本考案の実施例を示す平面図である。
１……回路板、３，４，５，７，８，９，１１
……リード部分、６，１０……ダミーリード、１
４……ＩＣ、１５……封止樹脂。
The drawing is a plan view showing an embodiment of the present invention. 1... Circuit board, 3, 4, 5, 7, 8, 9, 11
...Lead part, 6,10...Dummy lead, 1
4...IC, 15... Sealing resin.
Claims (1)
ード部分を設けた回路板と、上記回路板に固着さ
れたＩＣと、上記ＩＣの封止樹脂とを含み、上記
リード部分は上記封止樹脂により支持され、上記
リード部分の中少なくとも一つは上記ＩＣと接続
していないダミーリードとしたことを特徴とする
回路ブロツク。 The circuit board includes a circuit board patterned with a conductive metal and provided with a plurality of lead parts, an IC fixed to the circuit board, and a sealing resin for the IC, the lead parts being supported by the sealing resin. . A circuit block characterized in that at least one of the lead portions is a dummy lead not connected to the IC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19090985U JPS6298244U (en) | 1985-12-11 | 1985-12-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19090985U JPS6298244U (en) | 1985-12-11 | 1985-12-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6298244U true JPS6298244U (en) | 1987-06-23 |
Family
ID=31144559
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19090985U Pending JPS6298244U (en) | 1985-12-11 | 1985-12-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6298244U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS569756B2 (en) * | 1972-03-29 | 1981-03-03 | ||
| JPS5989447A (en) * | 1982-11-15 | 1984-05-23 | Matsushita Electric Ind Co Ltd | Semiconductor device |
-
1985
- 1985-12-11 JP JP19090985U patent/JPS6298244U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS569756B2 (en) * | 1972-03-29 | 1981-03-03 | ||
| JPS5989447A (en) * | 1982-11-15 | 1984-05-23 | Matsushita Electric Ind Co Ltd | Semiconductor device |