JPH0158959U - - Google Patents

Info

Publication number
JPH0158959U
JPH0158959U JP15340387U JP15340387U JPH0158959U JP H0158959 U JPH0158959 U JP H0158959U JP 15340387 U JP15340387 U JP 15340387U JP 15340387 U JP15340387 U JP 15340387U JP H0158959 U JPH0158959 U JP H0158959U
Authority
JP
Japan
Prior art keywords
island
chip
lead frame
lead
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15340387U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15340387U priority Critical patent/JPH0158959U/ja
Publication of JPH0158959U publication Critical patent/JPH0158959U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a及びbは本考案の第1の実施例の平面
図及びそのアイランドにICチツプを載置してボ
ンデイングした半導体装置に対応するA―A′線
断面図、第2図a及びbは本考案の第2の実施例
の平面図及びそのアイランドにICチツプを載置
してボンデイングした半導体装置に対応するA―
A′線断面図、第3図は従来のリードフレームの
一例のアイランドにICチツプを載置してボンデ
イングした半導体装置に対応するA―A′線断面
図である。 1……ICチツプ、2及び2……アイランド
、D……リード板厚、d……アイランド板厚、l
……リード。
Figures 1a and b are a plan view of the first embodiment of the present invention, a sectional view taken along the line A-A' corresponding to a semiconductor device in which an IC chip is mounted and bonded on the island, and Figures 2a and b is a plan view of the second embodiment of the present invention, and A--corresponding to a semiconductor device in which an IC chip is mounted and bonded on the island.
FIG. 3 is a cross-sectional view taken along line A--A' corresponding to a semiconductor device in which an IC chip is placed and bonded on an island of an example of a conventional lead frame. 1...IC chip, 2 and 2 a ...Island, D...Lead plate thickness, d...Island plate thickness, l
1 ...Lead.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ICチツプを載置するアイランドと、該アイラ
ンドを囲んで配置された複数のリードとを含むリ
ードフレームにおいて、前記アイランドの前記I
Cチツプを載置する領域の板厚が前記リードの板
厚よりも薄いことを特徴とするリードフレーム。
In a lead frame including an island on which an IC chip is mounted and a plurality of leads arranged surrounding the island, the I of the island
A lead frame characterized in that a region on which a C chip is placed has a thickness thinner than the lead.
JP15340387U 1987-10-06 1987-10-06 Pending JPH0158959U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15340387U JPH0158959U (en) 1987-10-06 1987-10-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15340387U JPH0158959U (en) 1987-10-06 1987-10-06

Publications (1)

Publication Number Publication Date
JPH0158959U true JPH0158959U (en) 1989-04-13

Family

ID=31429210

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15340387U Pending JPH0158959U (en) 1987-10-06 1987-10-06

Country Status (1)

Country Link
JP (1) JPH0158959U (en)

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