JPS6119151A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6119151A
JPS6119151A JP59139629A JP13962984A JPS6119151A JP S6119151 A JPS6119151 A JP S6119151A JP 59139629 A JP59139629 A JP 59139629A JP 13962984 A JP13962984 A JP 13962984A JP S6119151 A JPS6119151 A JP S6119151A
Authority
JP
Japan
Prior art keywords
power supply
semiconductor element
metal wiring
power
branching sections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59139629A
Other languages
Japanese (ja)
Inventor
Katsu Sanada
真田　克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59139629A priority Critical patent/JPS6119151A/en
Publication of JPS6119151A publication Critical patent/JPS6119151A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Abstract

PURPOSE:To stabilize bonding strength, and to reduce the effect of a parasitic inductance component by discretely bonding power-supply connecting small-gage wires separately lead out of a semiconductor element with branching sections in metallic wirings. CONSTITUTION:Bonding wires 7a-7c individually lead out of power-supply pads 4a-4c shaped onto a semiconductor element 3 placed in an island 2 on a substrate 1 are bonded severally to branching sections 5b, 5c in metallic wirings. Consequently, bonding strength is stabilized. Since a feeder has two branching sections 5b, 5c, each feeder can be operated as if they were fed from independent external lead terminals. Accordingly, the transient variation section (depending upon parasitic inductance and resistance) of a power supply for an input/ output circuit having an effect on a logic-arithmetic circuit section for the element 3 can be reduced extremely up to the branching sections 5b, 5c in the metallic wiring.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体装置の構造に関し、特に内部論理演算回
路を備えた大規模半導体装置の構成に適するものである
。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the structure of a semiconductor device, and is particularly suitable for the structure of a large-scale semiconductor device equipped with an internal logic operation circuit.

（従来の技術） 内部に論理演算回路を持つ半導体装置では、その集積度
がますます大規模化されるに伴ない、入出力回路部と内
部論理演算回路部への電源供給源を分離し、それぞれ個
別に設けた方が良いことが知られている。それは例えば
論理演算回路を構成するクリップ・７０ツブ回路が雑音
に弱く、電源の過渡変動分が大きな入出力回路部の影響
で、論理内容を容易に反転させる、誤動作の原因が知ら
れているからである。しかし、半導体容器から引出し得
る外部リード（以下ピンという）数に制限があること、
また使用者の便宜上から電源端子を個別に設けることは
好ましくないので、これら２つの回路への電源の給電は
一本のビンを共有させ。(Prior art) As the degree of integration of semiconductor devices with internal logic operation circuits becomes larger and larger, it is necessary to separate the power supply sources for the input/output circuit section and the internal logic operation circuit section. It is known that it is better to provide each separately. This is because, for example, the clip/70-tube circuit that makes up the logic operation circuit is susceptible to noise, and the logic content can easily be reversed due to the influence of the input/output circuit section, which has large transient fluctuations in the power supply, which is a known cause of malfunction. It is. However, there is a limit to the number of external leads (hereinafter referred to as pins) that can be drawn out from the semiconductor container;
Further, for the convenience of the user, it is not desirable to provide separate power supply terminals, so the power supply to these two circuits is shared by one bottle.

一つの電源から行なうよう妥協がはかられる。すなわち
、半導体素子上に形成された２つの回路に供給される電
源パッドは、半導体素子を載置する基板上の一つの金属
配線にボンディングされる。A compromise is made to operate from a single power source. That is, power pads supplied to two circuits formed on a semiconductor element are bonded to one metal wiring on a substrate on which the semiconductor element is mounted.

（発明が解決しようとする問題点） 通常用いられている半導体容器には、半導体素子を中心
に金属配線が放射状に形成されているので、上記２つの
回路に供給されるそれぞれの電源のパッドは、これらの
一本の金属配線上にまとめてボンディングされる。(Problem to be Solved by the Invention) In a commonly used semiconductor container, metal wiring is formed radially around the semiconductor element, so the pads of each power supply supplied to the above two circuits are , are collectively bonded onto one metal wiring.

しかしながら、金属配線の線幅そのものがすでに狭いの
で、複数個のボンディングに耐えられないものが少なく
なく、生産歩溜シを著しく低下させる。また雑音周波数
が高周波になると従来問題とされなかった金属配線の寄
生インダクタンス成分の影響が顕在化し、電源電圧の過
度変動分がよ）一層大きくなるため本来、電源変動が起
ってはならない内部論理演算回路への電源に前記過渡変
動分がそのまま伝達してしまう。However, since the line width of the metal wiring itself is already narrow, many of them cannot withstand multiple bondings, which significantly reduces production yield. Furthermore, when the noise frequency becomes high, the influence of the parasitic inductance component of the metal wiring, which has not been considered a problem in the past, becomes apparent, and the transient fluctuations in the power supply voltage become even larger (internal logic that should not cause power fluctuations). The transient fluctuation amount is transmitted as is to the power supply to the arithmetic circuit.

従来、これらの問題点には、回路設計段階でマージンを
設けるか或いは使用規格に制限条項を作るなどの対策が
便宜的に行なわれているのみで、抜本的解決策がとられ
たことはない。Conventionally, countermeasures to these problems have only been taken expediently, such as providing margins at the circuit design stage or creating restrictive clauses in usage standards, but no fundamental solutions have been taken. .

（発明の目的） 本発明の目的は、上記の情況に鑑み、電源パッドとのボ
ンディング強度が安定し、且つ寄生インダクタンス成分
の影響を減少せしめ得る形状の金属配線を絶縁基板上に
備えた半導体装置を提供することである。(Object of the Invention) In view of the above-mentioned circumstances, an object of the present invention is to provide a semiconductor device equipped with metal wiring on an insulating substrate in a shape that can stabilize bonding strength with a power supply pad and reduce the influence of parasitic inductance components. The goal is to provide the following.

（発明の構成） 本発明の半導体装置は、半導体素子と、前記半導体素子
を載置する絶縁基板と、前記絶縁基板上に一つの基幹部
と複数個の分岐部とを備えて形成され、前記半導体素子
の入出力回路部および論理演算回路部からそれぞれ個別
に引出される電源接続細線を、前記複数個の分岐部を介
し、一つの基幹部から共用する一つの外部引出しリード
に接続する金属配線とを含む。(Structure of the Invention) A semiconductor device of the present invention is formed to include a semiconductor element, an insulating substrate on which the semiconductor element is placed, one main body and a plurality of branch parts on the insulating substrate, and the semiconductor device includes: Metal wiring that connects thin power supply connection wires drawn out individually from the input/output circuit section and logic operation circuit section of the semiconductor element to one external lead lead shared from one main body via the plurality of branch sections. including.

（問題点を解決するための手段） すなわち、本発明によれば、半導体素子を載置する絶縁
基板には、外部引出しリードの一つに接続する基幹部と
複数個の分岐部とを備えた金属配線が従来の金属配線形
状に代えて形成される。ここで、半導体素子の入出力回
路部および論理演算回路部から電源パッドを介しそれぞ
れ個別に引出される電源接続細線は、金属配線が備える
複数個の分岐部にそれぞれ個別にボンディングされ、そ
れぞれが一つの基幹部を通って一つの外部引出しリード
に接続されることによシ、一つの共通電源から給電され
る。(Means for Solving the Problems) That is, according to the present invention, an insulating substrate on which a semiconductor element is mounted is provided with a main portion connected to one of the external lead leads and a plurality of branch portions. A metal wire is formed in place of the conventional metal wire shape. Here, the power supply connection thin wires that are individually drawn out from the input/output circuit section and the logic operation circuit section of the semiconductor element via the power supply pads are individually bonded to a plurality of branch sections provided in the metal wiring, and each They are powered by one common power source by being connected through two trunks to one external extraction lead.

（作用） 本発明によれば、半導体素子から個別に引出される電源
接続細線は、金属配線の分岐部にそれぞれ個別にボンデ
ィングされるので、ボンディング作業効率および強度を
著しく向上せしめ得る。また、金属配線のボンディング
部は複数個の分岐部からなるので、電源の過渡変動分は
変動する回路にのみ影響を与え他の同一電源への過渡変
動分はｉしく減少せしめる事ができる。(Function) According to the present invention, the power supply connection thin wires individually drawn out from the semiconductor element are individually bonded to the branch portions of the metal wiring, so that the bonding work efficiency and strength can be significantly improved. Further, since the bonding part of the metal wiring is made up of a plurality of branch parts, transient fluctuations in the power supply only affect the circuit that fluctuates, and transient fluctuations to other same power supplies can be effectively reduced.

（実施例） 第１図は本発明半導体装置の、一実施例を示す上部欠截
傾視図で、絶縁基板上における金属配線の形状が良く理
解し得るよう拡大して表わされている。本実施例では、
絶縁基板１と、アイランド２と、その領域内に載置され
た半導体素子３と、半導体素子３に設けられた電源パッ
ド４ａ、４ｂおよび４Ｃと、一つの基幹部５ａおよび２
つの分岐部５ｂ、５ｃとを備える絶縁基板１上の金属配
線と、通常の金属配線６と、上記電源パッドと金属配線
の分岐部間を接続するボンディング線７ｍ、７ｂ。(Embodiment) FIG. 1 is a top cutaway perspective view showing one embodiment of the semiconductor device of the present invention, and is shown enlarged so that the shape of metal wiring on an insulating substrate can be clearly understood. In this example,
An insulating substrate 1, an island 2, a semiconductor element 3 placed within the area, power supply pads 4a, 4b and 4C provided on the semiconductor element 3, and one main body 5a and 2
A metal wiring on the insulating substrate 1 having two branch parts 5b and 5c, a normal metal wiring 6, and bonding lines 7m and 7b connecting the power supply pad and the branch parts of the metal wiring.

７Ｃと、金属配線の基幹部５ａに接続する外部引出シリ
ード（ビン）８および通常の金属配線６に接続するビン
９とを含む。ここで、半導体素子３は、ＴＴＬ回路で構
成される入出力部とＥＣＬ回路で構成される論理演算部
とからなシ、それぞれの電源配線パターンは互いに分離
して形成されている。一般にＴＴＬ＠−Ｍは動作速度は
遅いが論理振巾が大きいため外部からの到来雑音の影響
を受ける程度が小さく、１０１回路はこれとは全く逆の
性質を持つ。従って、電源電圧の過渡変動は論理演算回
路部に致命的影響を与える。特に集積度が大きくなシ入
出力部の回路数が増えて外部信号間とのやシとシが活発
となって、駆動電流も大きくなると、電源の過渡変動に
よる論理演算回路部への影響の危険は一層増大する。こ
れは勿論、２つの回路への供給電源が一つの電源および
ビンを共用しているからである。一般に、この給電回路
構成では、電源の過渡変動分ΔＶは絶縁基板上の金属配
線が有する寄生インダクタンスＬおよび抵抗Ｒｉの大き
さに関係し、 ΔＶ　＝　Ｌ　　　ｄ　ｉ／ｄ　ｔ　＋　Ｒｉで表わす
ことができる。すなわち、出力回路の同時動作個数の増
大によるｄｉ酸成分増大や、周波数の増加によるｄｔ　
成分の減少は金属配線の寄生インダクタンス成分を無視
し得りくシ、電源の過渡変動分を急激に増大させ、論理
演算回路部の演算内容を反転させた）、論理不良をおこ
したシするようになる。7C, an external drawer series lead (bin) 8 connected to the main body 5a of the metal wiring, and a bin 9 connected to the normal metal wiring 6. Here, the semiconductor element 3 consists of an input/output section made up of a TTL circuit and a logic operation section made up of an ECL circuit, and their respective power supply wiring patterns are formed separately from each other. In general, TTL@-M has a slow operating speed but a large logic amplitude and is therefore less affected by external noise, whereas the 101 circuit has completely opposite characteristics. Therefore, transient fluctuations in the power supply voltage have a fatal effect on the logic operation circuit section. In particular, when the number of circuits in the input/output section of a device with a large degree of integration increases, communication between external signals becomes active, and the drive current also increases, the influence of transient fluctuations in the power supply on the logic operation circuit section increases. The danger increases further. This is of course because the power supplies to the two circuits share one power supply and bin. Generally, in this power supply circuit configuration, the transient fluctuation ΔV of the power supply is related to the parasitic inductance L and the resistance Ri of the metal wiring on the insulating substrate, and can be expressed as ΔV = L d i /d t + Ri. can. In other words, the di-acid component increases due to an increase in the number of simultaneously operating output circuits, and the dt decreases due to an increase in frequency.
The decrease in the parasitic inductance component of the metal wiring could not be ignored, but the transient fluctuation of the power supply suddenly increased, and the calculation content of the logic operation circuit was reversed), causing a logic failure. Become.

本実施例の給電配線は２個の分岐部５ｂ、５ｃを備える
ので、あたかも各々が独立した外部リード端子より供給
されているかのように動作させる事ができる。勿論分岐
部の数は任意に定めることができる。従って、論理演算
回路部に影響を与える入出力回路部での電源の過渡変動
分は、金属配線の分岐点までで非常に小さくすることが
できる。Since the power supply wiring of this embodiment includes two branch parts 5b and 5c, it can be operated as if each branch part were supplied from independent external lead terminals. Of course, the number of branch parts can be determined arbitrarily. Therefore, transient fluctuations in the power supply in the input/output circuit section that affect the logic operation circuit section can be made extremely small up to the branch point of the metal wiring.

また、ボンディング面積も大きくとれるので、その強度
は大であシ高信頼性の半導体装置を構成し得る。Further, since the bonding area can be increased, a semiconductor device with high strength and high reliability can be constructed.

（発明の効果） 以上詳細に説明したように、本発明Ｋかかる給電回路構
成の半導体装置は、ボンディングがし易く歩溜シ向上が
はかられ信頼性を高め得ること。(Effects of the Invention) As described above in detail, the semiconductor device of the present invention K having the power supply circuit configuration can be easily bonded, yield can be improved, and reliability can be improved.

内部論理演算回路が電源の入出力回路部によシ発生する
過渡変動に対して可成シ自由に設計し得ること、使用規
格に制限条項を入れる必要がないこと、更には入出力部
の取扱い電力を大きくでき、大規模且つ高速の論理演算
素子を容易に得ることができるなど、きわめて顕著なる
効果を有する。The internal logic arithmetic circuit can be designed freely to cope with transient fluctuations caused by the input/output circuit of the power supply, there is no need to include restrictions in the usage standards, and furthermore, the handling of the input/output section has been improved. It has extremely significant effects, such as increased power and the ability to easily obtain large-scale, high-speed logical operation elements.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明半導体装置の一実施例を示す上部欠截傾
視図である。 １・・・・・・絶縁基板、２・・・・・・アイランド、
３・・・・・・半導体素子、４ａ、４ｂ、４ｃ・・・・
・・電源パッド、５ａ・・・：・・金属配線の基幹部、
５ｂ、５ｃ・・・・・・金属配線の分岐部、８・・・・
・・電源用ピン。 代理人　弁理士　　内　原　　　晋 箭　１図FIG. 1 is a top cutaway perspective view showing an embodiment of the semiconductor device of the present invention. 1...Insulating substrate, 2...Island,
3...Semiconductor element, 4a, 4b, 4c...
...Power supply pad, 5a...: ...Main part of metal wiring,
5b, 5c... Branch portion of metal wiring, 8...
...Power pin. Agent Patent Attorney Shinsaku Uchihara Figure 1

Claims (1)

【特許請求の範囲】[Claims] 半導体素子と、前記半導体素子を載置する絶縁基板と、
前記絶縁基板上に一つの基幹部と複数個の分岐部とを備
えて形成され、前記半導体素子の入出力回路部および論
理演算回路部からそれぞれ個別に引出される電源接続細
線を、前記複数個の分岐部をそれぞれ介し、一つの基幹
部から共用する一つの外部引出しリードに接続する金属
配線とを含むことを特徴とする半導体装置。a semiconductor element; an insulating substrate on which the semiconductor element is placed;
The plurality of thin power supply connection wires are formed on the insulating substrate with one main body and a plurality of branch parts, and are individually drawn out from the input/output circuit section and the logic operation circuit section of the semiconductor element. 1. A semiconductor device comprising: metal wiring connected from one main body to one shared external lead through branch parts of the semiconductor device.
JP59139629A 1984-07-05 1984-07-05 Semiconductor device Pending JPS6119151A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59139629A JPS6119151A (en) 1984-07-05 1984-07-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59139629A JPS6119151A (en) 1984-07-05 1984-07-05 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6119151A true JPS6119151A (en) 1986-01-28

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP59139629A Pending JPS6119151A (en) 1984-07-05 1984-07-05 Semiconductor device

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Country Link
JP (1) JPS6119151A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6420747U (en) * 1987-07-27 1989-02-01
JPH02170547A (en) * 1988-12-23 1990-07-02 Toshiba Corp Semiconductor integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6420747U (en) * 1987-07-27 1989-02-01
JPH02170547A (en) * 1988-12-23 1990-07-02 Toshiba Corp Semiconductor integrated circuit

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