KR860003657A - 집적회로 패키지 - Google Patents

집적회로 패키지 Download PDF

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Publication number
KR860003657A
KR860003657A KR1019850005546A KR850005546A KR860003657A KR 860003657 A KR860003657 A KR 860003657A KR 1019850005546 A KR1019850005546 A KR 1019850005546A KR 850005546 A KR850005546 A KR 850005546A KR 860003657 A KR860003657 A KR 860003657A
Authority
KR
South Korea
Prior art keywords
cover
integrated circuit
annular groove
cross
electrically insulating
Prior art date
Application number
KR1019850005546A
Other languages
English (en)
Inventor
제이 임즈 로버어트 (외 1)
Original Assignee
로버어트 티이 오어너
지이티이이이 프로닥츠 코오포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 로버어트 티이 오어너, 지이티이이이 프로닥츠 코오포레이션 filed Critical 로버어트 티이 오어너
Publication of KR860003657A publication Critical patent/KR860003657A/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)
  • Control And Other Processes For Unpacking Of Materials (AREA)
  • Casings For Electric Apparatus (AREA)

Abstract

내용 없음

Description

집적회로 패키지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 집적회로 패키지(Package) 를 위한 기부의 평면도.
제2도는 제1도의 기부를 위한 커버(cover)의 확대 평면도.
제3도는 제2도의 커버의 부분적으로 단면이 보여지는 정면도.
도면의 주요부분에 대한 부호의 설명
11:기부 12,24,25:리세스(recess) 16,30:돌출부 17:골 23:커버 26:홈 27:구멍 36:와샤.

Claims (3)

  1. 외측표면과 내측표면을 가진 전기절연성 몸체로 구성되어 있는 집적회로 패키지용 커버로서, 상기 내측표면은 실제적으로 중앙에 위치한 사각형 함몰부를 가지고 있고, 상기 함몰부 주위에는 환상홈이 있는데, 상기 환상홈은 상기 함몰부의 최대 대각선 길이보다 더 큰 최소직경을 가지고 있으며, 또한 상기 환상홈은 횡단면이 사각형인 커버.
  2. 제1항에 있어서, 상기 환상홈은 그 횡단면과 짝을 이루는 횡단면을 가진 변형가능한 자체지지 인입도선 밀봉와샤를 포함하고 있는 커버.
  3. 다수의 전기전도성 인입도선을 전기절연성 기부에 부착하고, 집적회로칩을 상기 기부에 고정시키고, 상기 칩과 상기 인입도선 사이의 전기적 연결을 이루고, 변형가능함 자체지지 인입도선 밀봉와샤를 전기 절연성 커버내에 고정시키고, 상기 커버를 상기 기부위에 장착함으로써 상기 다수의 인입도선이 상기 와샤를 관통하는 단계들로 구성되는 집적회로 패키지를 제조하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019850005546A 1984-10-09 1985-08-01 집적회로 패키지 KR860003657A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/659,212 US4611398A (en) 1984-10-09 1984-10-09 Integrated circuit package
US659212 1984-10-09

Publications (1)

Publication Number Publication Date
KR860003657A true KR860003657A (ko) 1986-05-28

Family

ID=24644521

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850005546A KR860003657A (ko) 1984-10-09 1985-08-01 집적회로 패키지

Country Status (5)

Country Link
US (1) US4611398A (ko)
EP (1) EP0177948A3 (ko)
JP (1) JPS6191950A (ko)
KR (1) KR860003657A (ko)
CA (1) CA1231182A (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5152057A (en) * 1987-11-17 1992-10-06 Mold-Pac Corporation Molded integrated circuit package
US4868635A (en) * 1988-01-13 1989-09-19 Texas Instruments Incorporated Lead frame for integrated circuit
US4829669A (en) * 1988-04-28 1989-05-16 Nec Corporation Method of manufacturing a chip carrier
US5369059A (en) * 1989-12-08 1994-11-29 Cray Research, Inc. Method for constructing a reduced capacitance chip carrier
US5780924A (en) * 1996-05-07 1998-07-14 Lsi Logic Corporation Integrated circuit underfill reservoir
US5821607A (en) * 1997-01-08 1998-10-13 Orient Semiconductor Electronics, Ltd. Frame for manufacturing encapsulated semiconductor devices

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE202925C (ko) * 1969-04-30 1900-01-01
US3265806A (en) * 1965-04-05 1966-08-09 Sprague Electric Co Encapsulated flat package for electronic parts
US3684818A (en) * 1970-10-20 1972-08-15 Sprague Electric Co Multi-layer beam-lead wiring for semiconductor packages
US3714370A (en) * 1972-01-24 1973-01-30 North American Rockwell Plastic package assembly for electronic circuit and process for producing the package
US3981074A (en) * 1974-08-23 1976-09-21 Nitto Electric Industrial Co., Ltd. Method for producing plastic base caps for split cavity type package semi-conductor units
US4139859A (en) * 1975-06-30 1979-02-13 Burroughs Corporation Semiconductor device package
US4285002A (en) * 1978-01-19 1981-08-18 International Computers Limited Integrated circuit package
GB2127740B (en) * 1982-09-30 1985-10-23 Burr Brown Res Corp Improved hermetic sealing process
US4499333A (en) * 1983-03-28 1985-02-12 Printed Circuits International, Inc. Electronic component cap and seal

Also Published As

Publication number Publication date
US4611398A (en) 1986-09-16
EP0177948A3 (en) 1988-01-20
EP0177948A2 (en) 1986-04-16
JPS6191950A (ja) 1986-05-10
CA1231182A (en) 1988-01-05

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