KR900010985A - 반도체 장치 - Google Patents

반도체 장치 Download PDF

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Publication number
KR900010985A
KR900010985A KR1019890019558A KR890019558A KR900010985A KR 900010985 A KR900010985 A KR 900010985A KR 1019890019558 A KR1019890019558 A KR 1019890019558A KR 890019558 A KR890019558 A KR 890019558A KR 900010985 A KR900010985 A KR 900010985A
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South Korea
Prior art keywords
wire portion
low resistance
fine wire
semiconductor device
resistance wire
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KR1019890019558A
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English (en)
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도시오 나가이
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아오이 죠이찌
가부시끼가이샤 도시바
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Priority claimed from JP32534688A external-priority patent/JPH02203554A/ja
Priority claimed from JP32534488A external-priority patent/JPH02170560A/ja
Application filed by 아오이 죠이찌, 가부시끼가이샤 도시바 filed Critical 아오이 죠이찌
Publication of KR900010985A publication Critical patent/KR900010985A/ko

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음

Description

반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 실시예의 반도체장치의 패키지 구조를 도시한 사시도, 제3도는 제2도의 패키지에 반도체 소자를 설치한 반도체 장치를 도시한 단면도, 제6도는 공면(coplanar) 구조의 특성 임피던스를 설명하는 개요도이다.

Claims (14)

  1. 반도체 소자를 하우징시키기 위해 다층으로 된 절연기판, 반도체 소자의 주변부에 배치되어 그 한쪽 끝상에서 반도체 소자에 전기적으로 연결되는 미세 와이어부 및 미세 와이어부의 다른쪽에 전기적으로 연결되는 저저항 와이어부를 가진, 절연기판에 배치되는 내부 와이어층, 마이크로 스트립 구조로 저저항 와이어부를 형성하기 위하여 절연기판에 배치되는 제1그라운드층, 및 마이크로 스트립 구조로 미세 와이어부를 형성하기 위하여 제1라운드층과는 다르게 절연기판내의 평면 위치에 배치되는 제2그라운드층으로 이루어진 것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 미세 와이어부 및 저저항 와이어부는 동일 면상에 연속적으로 형성되고, 미세 와이어부 및 저저항 와이어부가 형성되는 면과, 제2그라운드층간의 거리는 미세 와이어부의 특성 임피던스가 저저항 와이어부의 특성 임피던스와 거의 같게 되도록 정해지는 것을 특징으로 하는 반도체 장치.
  3. 제1항에 있어서, 전도체 저항을 감소시키기 위해 저저항 와이어부의 선폭이 미세 와이어부의 선폭보다 넓으며, 미세 와이어부가 저저항 와이어부에 연결되어, 선폭을 점차적으로 변화시키도록 된 것을 특징으로 하는 반도체 장치.
  4. 제1항에 있어서, 전도체 저항을 감소시키기 위해 저저항 와이어부의 층이 미세 와이어부의 층보다 두꺼운 것을 특징으로 하는 반도체 장치.
  5. 제1항에 있어서, 절연기판은 내부 와이어층에 전기적으로 연결된 I/O 핀들은 가지며, I/O 핀들은 이음부없이 미세 와이어부의 반도체 소자의 연결부에 와이어링되는 것을 특징으로 하는 반도체 장치.
  6. 제1항에 있어서, 절연기판이 질화 알루미늄으로 구성된 것을 특징으로 하는 반도체 장치.
  7. 반도체 소자를 하우징시키기 위해 다층으로 된 절연기판, 반도체 소자의 주변부에 배치되어 그 한쪽 끝상에서 반도체 소자에 전기적으로 연결되는 미세 와이어부 및 미세 와이어부의 다른쪽에 전기적으로 연결되는 저저항 와이어부를 가진, 절연기판에 배치되는 내부 와이어층, 마이크로 스트립 구조로 미세 와이어부를 형성하기 위하여 절연기판에 배치되는 제1그라운드층, 및 공면(coplanar) 구조로 저저항 와이어부를 형성하기 위하여 절연기판에 배치되는 제2그라운드층으로 이루어진 것을 특징으로 하는 반도체 장치.
  8. 제7항에 있어서, 제1그라운드층과 제2그라운드층이 동일 면상에 형성되고, 제2그라운드층은 빗살 형태로 제1그라운드층으로부터 돌출되어 있는 것을 특징으로 하는 반도체 장치.
  9. 제7항에 있어서, 미세 와이어부와 저저항 와이어부가 상이한 면상에 형성되고, 미세 와이어부와 저저항 와이어부는 관통구멍들을 경유하여 전기적으로 연결된 것을 특징으로 하는 반도체 장치.
  10. 제7항에 있어서, 전도체 저항을 감소시키기 위하여 저저항 와이어부의 선폭이 미세 와이어부의 선폭보다 넓은 것을 특징으로 하는 반도체 장치.
  11. 제7항에 있어서, 저저항 와이어부의 두께가 미세 와이어부의 두께보다 두꺼운 것을 특징으로 하는 반도체 장치.
  12. 제7항에 있어서, 미세 와이어부와 제1그라운드층간의 거리 및, 저저항 와이어부와 제2그라운드층간의 거리는 미세 와이어부의 특성 임피던스가 저저항 와이어부의 특성 임피던스와 거의 동일하게 되도록 정해지는 것을 특징으로 하는 반도체 장치.
  13. 제7항에 있어서, 절연기판은 내부 와이어층에 전기적으로 연결된 I/O 핀들을 가지며, I/O 핀들은 이음부없이 미세 와이어부의 반도체 소자의 연결부에 와이어링되는 것을 특징으로 하는 반도체 장치.
  14. 제7항에 있어서, 절연기판이 질화 알루미늄으로 구성된 것을 특징으로 하는 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890019558A 1988-12-23 1989-12-23 반도체 장치 KR900010985A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP32534688A JPH02203554A (ja) 1988-12-23 1988-12-23 半導体装置とその製造方法
JP88-325346 1988-12-23
JP88-325344 1988-12-23
JP32534488A JPH02170560A (ja) 1988-12-23 1988-12-23 半導体装置

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KR900010985A true KR900010985A (ko) 1990-07-11

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US5721454A (en) * 1995-12-20 1998-02-24 Intel Corporation Integrated circuit package with a plurality of vias that are electrically connected to an internal ground plane and thermally connected to an external heat slug
TW366570B (en) * 1997-03-26 1999-08-11 Matsushita Electric Ind Co Ltd Semiconductor device and the wiring unit
US6127728A (en) * 1999-06-24 2000-10-03 Lsi Logic Corporation Single reference plane plastic ball grid array package

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US4551746A (en) * 1982-10-05 1985-11-05 Mayo Foundation Leadless chip carrier apparatus providing an improved transmission line environment and improved heat dissipation
US4866507A (en) * 1986-05-19 1989-09-12 International Business Machines Corporation Module for packaging semiconductor integrated circuit chips on a base substrate
KR900008995B1 (ko) * 1986-12-19 1990-12-17 페어차일드 세미콘덕터 코포레이션 고주파 반도체 소자용 세라믹 패키지

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